f141cc31dc
RK3399 PLLs have three modes : - Normal, where they behave normally and their freq is calculated based on the registers values. - Slow, where the PLL freq is 24Mhz (well, the external oscillator). - Deep Slow, used for suspend where the freq is 32Khz. We used to put every CPU related PLL in normal mode but it can cause problem if the firmware didn't setup the clocks register correctly. And even if it did but left the pll in slow or deep slow mode that might be because the PMIC suppling voltage for the CPU haven't been configured yet and we cannot do that at this point. So remove the ability to set PLLs to normal mode at boot to avoid any problems. |
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acpica | ||
arm64 | ||
cavium | ||
cloudabi32 | ||
cloudabi64 | ||
conf | ||
coresight | ||
include | ||
intel | ||
linux | ||
qualcomm | ||
rockchip |