dc4ee6ca91
make use of it where possible. This primarily brings in support for newer hardware, and FreeBSD is not yet able to support the abundance of IRQs on new hardware and many features in the Ethernet driver. Because of the changes to IRQs in the Simple Executive, we have to maintain our own list of Octeon IRQs now, which probably can be pared-down and be specific to the CIU interrupt unit soon, and when other interrupt mechanisms are added they can maintain their own definitions. Remove unmasking of interrupts from within the UART device now that the function used is no longer present in the Simple Executive. The unmasking seems to have been gratuitous as this is more properly handled by the buses above the UART device, and seems to work on that basis.
325 lines
10 KiB
C
325 lines
10 KiB
C
/***********************license start***************
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* Copyright (c) 2003-2010 Cavium Inc. (support@cavium.com). All rights
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* reserved.
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*
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* * Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials provided
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* with the distribution.
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* * Neither the name of Cavium Inc. nor the names of
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* its contributors may be used to endorse or promote products
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* derived from this software without specific prior written
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* permission.
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* This Software, including technical data, may be subject to U.S. export control
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* laws, including the U.S. Export Administration Act and its associated
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* regulations, and may be subject to export or import regulations in other
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* countries.
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* TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
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* AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
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* WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
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* THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
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* DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
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* SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
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* MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
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* VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
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* CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR
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* PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
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***********************license end**************************************/
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/**
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* @file
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*
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* Interface to the TWSI / I2C bus
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*
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* Note: Currently on 7 bit device addresses are supported
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*
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* <hr>$Revision: 70030 $<hr>
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*
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*/
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#ifndef __CVMX_TWSI_H__
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#define __CVMX_TWSI_H__
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Extra TWSI Bus Opcodes */
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#define TWSI_SLAVE_ADD 0
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#define TWSI_DATA 1
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#define TWSI_CTL 2
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#define TWSI_CLKCTL_STAT 3 /* R=0 selects CLKCTL, R=1 selects STAT */
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#define TWSI_STAT 3 /* when R = 1 */
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#define TWSI_SLAVE_ADD_EXT 4
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#define TWSI_RST 7
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/**
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* Do a twsi read from a 7 bit device address using an (optional) internal address.
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* Up to 8 bytes can be read at a time.
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*
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* @param twsi_id which Octeon TWSI bus to use
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* @param dev_addr Device address (7 bit)
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* @param internal_addr
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* Internal address. Can be 0, 1 or 2 bytes in width
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* @param num_bytes Number of data bytes to read
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* @param ia_width_bytes
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* Internal address size in bytes (0, 1, or 2)
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* @param data Pointer argument where the read data is returned.
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*
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* @return read data returned in 'data' argument
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* Number of bytes read on success
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* -1 on failure
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*/
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int cvmx_twsix_read_ia(int twsi_id, uint8_t dev_addr, uint16_t internal_addr, int num_bytes, int ia_width_bytes, uint64_t *data);
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/**
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* A convenience wrapper function around cvmx_twsix_read_ia() that
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* only supports 8 bit internal addresses.
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* Reads up to 7 bytes, and returns both the value read or error
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* value in the return value
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*
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* @param twsi_id which Octeon TWSI bus to use
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* @param dev_addr Device address (7 bit only)
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* @param internal_addr
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* Internal address (8 bit only)
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* @param num_bytes Number of bytes to read (0-7)
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*
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* @return Value read from TWSI on success
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* -1 on error
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*/
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static inline int64_t cvmx_twsix_read_ia8(int twsi_id, uint8_t dev_addr, uint8_t internal_addr, int num_bytes)
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{
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uint64_t data;
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if (num_bytes < 1 || num_bytes > 7)
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return -1;
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if (cvmx_twsix_read_ia(twsi_id,dev_addr,internal_addr,num_bytes, 1, &data) < 0)
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return -1;
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return data;
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}
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/**
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* A convenience wrapper function around cvmx_twsix_read_ia() that
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* only supports 16 bit internal addresses.
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* Reads up to 7 bytes, and returns both the value read or error
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* value in the return value
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*
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* @param twsi_id which Octeon TWSI bus to use
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* @param dev_addr Device address (7 bit only)
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* @param internal_addr
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* Internal address (16 bit only)
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* @param num_bytes Number of bytes to read (0-7)
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*
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* @return Value read from TWSI on success
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* -1 on error
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*/
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static inline int64_t cvmx_twsix_read_ia16(int twsi_id, uint8_t dev_addr, uint16_t internal_addr, int num_bytes)
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{
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uint64_t data;
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if (num_bytes < 1 || num_bytes > 7)
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return -1;
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if (cvmx_twsix_read_ia(twsi_id, dev_addr, internal_addr, num_bytes, 2, &data) < 0)
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return -1;
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return data;
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}
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/**
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* Read from a TWSI device (7 bit device address only) without generating any
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* internal addresses.
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* Read from 1-8 bytes and returns them in the data pointer.
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*
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* @param twsi_id TWSI interface on Octeon to use
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* @param dev_addr TWSI device address (7 bit only)
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* @param num_bytes number of bytes to read
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* @param data Pointer to data read from TWSI device
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*
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* @return Number of bytes read on success
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* -1 on error
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*/
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int cvmx_twsix_read(int twsi_id, uint8_t dev_addr, int num_bytes, uint64_t *data);
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/**
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* Perform a twsi write operation to a 7 bit device address.
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*
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* Note that many eeprom devices have page restrictions regarding address boundaries
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* that can be crossed in one write operation. This is device dependent, and this routine
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* does nothing in this regard.
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* This command does not generate any internal addressess.
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*
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* @param twsi_id Octeon TWSI interface to use
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* @param dev_addr TWSI device address
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* @param num_bytes Number of bytes to write (between 1 and 8 inclusive)
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* @param data Data to write
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*
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* @return 0 on success
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* -1 on failure
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*/
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int cvmx_twsix_write(int twsi_id, uint8_t dev_addr, int num_bytes, uint64_t data);
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/**
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* Write 1-8 bytes to a TWSI device using an internal address.
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*
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* @param twsi_id which TWSI interface on Octeon to use
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* @param dev_addr TWSI device address (7 bit only)
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* @param internal_addr
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* TWSI internal address (0, 8, or 16 bits)
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* @param num_bytes Number of bytes to write (1-8)
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* @param ia_width_bytes
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* internal address width, in bytes (0, 1, 2)
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* @param data Data to write. Data is written MSB first on the twsi bus, and only the lower
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* num_bytes bytes of the argument are valid. (If a 2 byte write is done, only
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* the low 2 bytes of the argument is used.
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*
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* @return Number of bytes read on success,
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* -1 on error
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*/
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int cvmx_twsix_write_ia(int twsi_id, uint8_t dev_addr, uint16_t internal_addr, int num_bytes, int ia_width_bytes, uint64_t data);
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/***********************************************************************
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** Functions below are deprecated, and not recomended for use.
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** They have been superceded by more flexible functions that are
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** now provided.
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************************************************************************/
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/**
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* Read 8-bit from a device on the TWSI / I2C bus
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*
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* @param twsi_id Which TWSI bus to use. CN3XXX, CN58XX, and CN50XX only
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* support 0. CN56XX and CN57XX support 0-1.
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* @param dev_addr I2C device address (7 bit)
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* @param internal_addr
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* Internal device address
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*
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* @return 8-bit data or < 0 in case of error
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*/
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static inline int cvmx_twsix_read8(int twsi_id, uint8_t dev_addr, uint8_t internal_addr)
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{
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return cvmx_twsix_read_ia8(twsi_id, dev_addr, internal_addr, 1);
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}
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/**
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* Read 8-bit from a device on the TWSI / I2C bus
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*
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* Uses current internal address
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*
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* @param twsi_id Which TWSI bus to use. CN3XXX, CN58XX, and CN50XX only
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* support 0. CN56XX and CN57XX support 0-1.
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* @param dev_addr I2C device address (7 bit)
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*
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* @return 8-bit value or < 0 in case of error
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*/
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static inline int cvmx_twsix_read8_cur_addr(int twsi_id, uint8_t dev_addr)
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{
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uint64_t data;
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if (cvmx_twsix_read(twsi_id,dev_addr, 1, &data) < 0)
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return -1;
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return(data & 0xff);
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}
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/**
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* Write 8-bit to a device on the TWSI / I2C bus
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*
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* @param twsi_id Which TWSI bus to use. CN3XXX, CN58XX, and CN50XX only
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* support 0. CN56XX and CN57XX support 0-1.
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* @param dev_addr I2C device address (7 bit)
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* @param internal_addr
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* Internal device address
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* @param data Data to be written
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*
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* @return 0 on success and < 0 in case of error
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*/
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static inline int cvmx_twsix_write8(int twsi_id, uint8_t dev_addr, uint8_t internal_addr, uint8_t data)
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{
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if (cvmx_twsix_write_ia(twsi_id,dev_addr,internal_addr, 1, 1,data) < 0)
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return -1;
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return 0;
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}
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/**
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* Read 8-bit from a device on the TWSI / I2C bus zero.
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*
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* This function is for compatibility with SDK 1.6.0 and
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* before which only supported a single TWSI bus.
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*
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* @param dev_addr I2C device address (7 bit)
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* @param internal_addr
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* Internal device address
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*
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* @return 8-bit data or < 0 in case of error
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*/
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static inline int cvmx_twsi_read8(uint8_t dev_addr, uint8_t internal_addr)
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{
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return cvmx_twsix_read8(0, dev_addr, internal_addr);
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}
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/**
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* Read 8-bit from a device on the TWSI / I2C bus zero.
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*
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* Uses current internal address
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*
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* This function is for compatibility with SDK 1.6.0 and
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* before which only supported a single TWSI bus.
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*
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* @param dev_addr I2C device address (7 bit)
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*
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* @return 8-bit value or < 0 in case of error
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*/
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static inline int cvmx_twsi_read8_cur_addr(uint8_t dev_addr)
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{
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return cvmx_twsix_read8_cur_addr(0, dev_addr);
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}
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/**
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* Write 8-bit to a device on the TWSI / I2C bus zero.
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* This function is for compatibility with SDK 1.6.0 and
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* before which only supported a single TWSI bus.
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*
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* @param dev_addr I2C device address (7 bit)
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* @param internal_addr
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* Internal device address
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* @param data Data to be written
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*
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* @return 0 on success and < 0 in case of error
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*/
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static inline int cvmx_twsi_write8(uint8_t dev_addr, uint8_t internal_addr, uint8_t data)
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{
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return cvmx_twsix_write8(0, dev_addr, internal_addr, data);
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}
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#ifdef __cplusplus
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}
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#endif
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#endif /* __CVMX_TWSI_H__ */
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