590 lines
18 KiB
C
590 lines
18 KiB
C
/*-
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* SPDX-License-Identifier: ISC
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*
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* Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
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* Copyright (c) 2002-2008 Atheros Communications, Inc.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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* $FreeBSD$
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*/
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#include "opt_ah.h"
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#include "ah.h"
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#include "ah_internal.h"
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#include "ah_eeprom_v14.h"
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#include "ar5416/ar5416.h"
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#include "ar5416/ar5416reg.h"
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#include "ar5416/ar5416phy.h"
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#define N(a) (sizeof(a)/sizeof(a[0]))
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struct ar2133State {
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RF_HAL_FUNCS base; /* public state, must be first */
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uint16_t pcdacTable[1];
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uint32_t *Bank0Data;
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uint32_t *Bank1Data;
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uint32_t *Bank2Data;
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uint32_t *Bank3Data;
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uint32_t *Bank6Data;
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uint32_t *Bank7Data;
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/* NB: Bank*Data storage follows */
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};
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#define AR2133(ah) ((struct ar2133State *) AH5212(ah)->ah_rfHal)
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#define ar5416ModifyRfBuffer ar5212ModifyRfBuffer /*XXX*/
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void ar5416ModifyRfBuffer(uint32_t *rfBuf, uint32_t reg32,
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uint32_t numBits, uint32_t firstBit, uint32_t column);
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static void
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ar2133WriteRegs(struct ath_hal *ah, u_int modesIndex, u_int freqIndex,
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int writes)
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{
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(void) ath_hal_ini_write(ah, &AH5416(ah)->ah_ini_bb_rfgain,
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freqIndex, writes);
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}
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/*
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* Fix on 2.4 GHz band for orientation sensitivity issue by increasing
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* rf_pwd_icsyndiv.
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*
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* Theoretical Rules:
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* if 2 GHz band
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* if forceBiasAuto
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* if synth_freq < 2412
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* bias = 0
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* else if 2412 <= synth_freq <= 2422
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* bias = 1
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* else // synth_freq > 2422
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* bias = 2
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* else if forceBias > 0
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* bias = forceBias & 7
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* else
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* no change, use value from ini file
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* else
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* no change, invalid band
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*
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* 1st Mod:
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* 2422 also uses value of 2
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* <approved>
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*
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* 2nd Mod:
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* Less than 2412 uses value of 0, 2412 and above uses value of 2
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*/
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static void
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ar2133ForceBias(struct ath_hal *ah, uint16_t synth_freq)
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{
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uint32_t tmp_reg;
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int reg_writes = 0;
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uint32_t new_bias = 0;
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struct ar2133State *priv = AR2133(ah);
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/* XXX this is a bit of a silly check for 2.4ghz channels -adrian */
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if (synth_freq >= 3000)
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return;
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if (synth_freq < 2412)
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new_bias = 0;
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else if (synth_freq < 2422)
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new_bias = 1;
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else
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new_bias = 2;
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/* pre-reverse this field */
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tmp_reg = ath_hal_reverseBits(new_bias, 3);
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HALDEBUG(ah, HAL_DEBUG_ANY, "%s: Force rf_pwd_icsyndiv to %1d on %4d\n",
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__func__, new_bias, synth_freq);
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/* swizzle rf_pwd_icsyndiv */
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ar5416ModifyRfBuffer(priv->Bank6Data, tmp_reg, 3, 181, 3);
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/* write Bank 6 with new params */
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ath_hal_ini_bank_write(ah, &AH5416(ah)->ah_ini_bank6, priv->Bank6Data, reg_writes);
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}
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/*
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* Take the MHz channel value and set the Channel value
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*
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* ASSUMES: Writes enabled to analog bus
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*/
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static HAL_BOOL
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ar2133SetChannel(struct ath_hal *ah, const struct ieee80211_channel *chan)
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{
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uint32_t channelSel = 0;
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uint32_t bModeSynth = 0;
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uint32_t aModeRefSel = 0;
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uint32_t reg32 = 0;
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uint16_t freq;
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CHAN_CENTERS centers;
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OS_MARK(ah, AH_MARK_SETCHANNEL, chan->ic_freq);
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ar5416GetChannelCenters(ah, chan, ¢ers);
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freq = centers.synth_center;
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if (freq < 4800) {
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uint32_t txctl;
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if (((freq - 2192) % 5) == 0) {
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channelSel = ((freq - 672) * 2 - 3040)/10;
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bModeSynth = 0;
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} else if (((freq - 2224) % 5) == 0) {
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channelSel = ((freq - 704) * 2 - 3040) / 10;
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bModeSynth = 1;
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} else {
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HALDEBUG(ah, HAL_DEBUG_ANY,
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"%s: invalid channel %u MHz\n", __func__, freq);
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return AH_FALSE;
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}
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channelSel = (channelSel << 2) & 0xff;
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channelSel = ath_hal_reverseBits(channelSel, 8);
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txctl = OS_REG_READ(ah, AR_PHY_CCK_TX_CTRL);
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if (freq == 2484) {
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/* Enable channel spreading for channel 14 */
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OS_REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
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txctl | AR_PHY_CCK_TX_CTRL_JAPAN);
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} else {
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OS_REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
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txctl &~ AR_PHY_CCK_TX_CTRL_JAPAN);
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}
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/*
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* Handle programming the RF synth for odd frequencies in the
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* 4.9->5GHz range. This matches the programming from the
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* later model 802.11abg RF synths.
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*
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* This interoperates on the quarter rate channels with the
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* AR5112 and later RF synths. Please note that the synthesiser
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* isn't able to completely accurately represent these frequencies
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* (as the resolution in this reference is 2.5MHz) and thus it will
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* be slightly "off centre." This matches the same slightly
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* incorrect * centre frequency behaviour that the AR5112 and later
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* channel selection code has.
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*
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* This is disabled because it hasn't been tested for regulatory
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* compliance and neither have the NICs which would use it.
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* So if you enable this code, you must first ensure that you've
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* re-certified the NICs in question beforehand or you will be
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* violating your local regulatory rules and breaking the law.
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*/
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#if 0
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} else if (((freq % 5) == 2) && (freq <= 5435)) {
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freq = freq - 2;
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channelSel = ath_hal_reverseBits(
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(uint32_t) (((freq - 4800) * 10) / 25 + 1), 8);
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/* XXX what about for Howl/Sowl? */
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aModeRefSel = ath_hal_reverseBits(0, 2);
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#endif
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} else if ((freq % 20) == 0 && freq >= 5120) {
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channelSel = ath_hal_reverseBits(((freq - 4800) / 20 << 2), 8);
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if (AR_SREV_HOWL(ah) || AR_SREV_SOWL_10_OR_LATER(ah))
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aModeRefSel = ath_hal_reverseBits(3, 2);
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else
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aModeRefSel = ath_hal_reverseBits(1, 2);
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} else if ((freq % 10) == 0) {
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channelSel = ath_hal_reverseBits(((freq - 4800) / 10 << 1), 8);
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if (AR_SREV_HOWL(ah) || AR_SREV_SOWL_10_OR_LATER(ah))
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aModeRefSel = ath_hal_reverseBits(2, 2);
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else
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aModeRefSel = ath_hal_reverseBits(1, 2);
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} else if ((freq % 5) == 0) {
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channelSel = ath_hal_reverseBits((freq - 4800) / 5, 8);
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aModeRefSel = ath_hal_reverseBits(1, 2);
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} else {
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HALDEBUG(ah, HAL_DEBUG_UNMASKABLE,
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"%s: invalid channel %u MHz\n",
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__func__, freq);
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return AH_FALSE;
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}
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/* Workaround for hw bug - AR5416 specific */
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if (AR_SREV_OWL(ah) && ah->ah_config.ah_ar5416_biasadj)
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ar2133ForceBias(ah, freq);
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reg32 = (channelSel << 8) | (aModeRefSel << 2) | (bModeSynth << 1) |
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(1 << 5) | 0x1;
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OS_REG_WRITE(ah, AR_PHY(0x37), reg32);
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AH_PRIVATE(ah)->ah_curchan = chan;
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return AH_TRUE;
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}
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/*
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* Return a reference to the requested RF Bank.
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*/
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static uint32_t *
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ar2133GetRfBank(struct ath_hal *ah, int bank)
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{
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struct ar2133State *priv = AR2133(ah);
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HALASSERT(priv != AH_NULL);
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switch (bank) {
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case 1: return priv->Bank1Data;
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case 2: return priv->Bank2Data;
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case 3: return priv->Bank3Data;
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case 6: return priv->Bank6Data;
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case 7: return priv->Bank7Data;
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}
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HALDEBUG(ah, HAL_DEBUG_ANY, "%s: unknown RF Bank %d requested\n",
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__func__, bank);
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return AH_NULL;
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}
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/*
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* Reads EEPROM header info from device structure and programs
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* all rf registers
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*
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* REQUIRES: Access to the analog rf device
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*/
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static HAL_BOOL
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ar2133SetRfRegs(struct ath_hal *ah, const struct ieee80211_channel *chan,
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uint16_t modesIndex, uint16_t *rfXpdGain)
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{
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struct ar2133State *priv = AR2133(ah);
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int writes;
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HALASSERT(priv);
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/* Setup Bank 0 Write */
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ath_hal_ini_bank_setup(priv->Bank0Data, &AH5416(ah)->ah_ini_bank0, 1);
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/* Setup Bank 1 Write */
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ath_hal_ini_bank_setup(priv->Bank1Data, &AH5416(ah)->ah_ini_bank1, 1);
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/* Setup Bank 2 Write */
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ath_hal_ini_bank_setup(priv->Bank2Data, &AH5416(ah)->ah_ini_bank2, 1);
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/* Setup Bank 3 Write */
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ath_hal_ini_bank_setup(priv->Bank3Data, &AH5416(ah)->ah_ini_bank3, modesIndex);
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/* Setup Bank 6 Write */
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ath_hal_ini_bank_setup(priv->Bank6Data, &AH5416(ah)->ah_ini_bank6, modesIndex);
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/* Only the 5 or 2 GHz OB/DB need to be set for a mode */
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if (IEEE80211_IS_CHAN_2GHZ(chan)) {
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HALDEBUG(ah, HAL_DEBUG_EEPROM, "%s: 2ghz: OB_2:%d, DB_2:%d\n",
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__func__,
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ath_hal_eepromGet(ah, AR_EEP_OB_2, AH_NULL),
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ath_hal_eepromGet(ah, AR_EEP_DB_2, AH_NULL));
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ar5416ModifyRfBuffer(priv->Bank6Data,
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ath_hal_eepromGet(ah, AR_EEP_OB_2, AH_NULL), 3, 197, 0);
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ar5416ModifyRfBuffer(priv->Bank6Data,
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ath_hal_eepromGet(ah, AR_EEP_DB_2, AH_NULL), 3, 194, 0);
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} else {
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HALDEBUG(ah, HAL_DEBUG_EEPROM, "%s: 5ghz: OB_5:%d, DB_5:%d\n",
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__func__,
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ath_hal_eepromGet(ah, AR_EEP_OB_5, AH_NULL),
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ath_hal_eepromGet(ah, AR_EEP_DB_5, AH_NULL));
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ar5416ModifyRfBuffer(priv->Bank6Data,
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ath_hal_eepromGet(ah, AR_EEP_OB_5, AH_NULL), 3, 203, 0);
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ar5416ModifyRfBuffer(priv->Bank6Data,
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ath_hal_eepromGet(ah, AR_EEP_DB_5, AH_NULL), 3, 200, 0);
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}
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/* Setup Bank 7 Setup */
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ath_hal_ini_bank_setup(priv->Bank7Data, &AH5416(ah)->ah_ini_bank7, 1);
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/* Write Analog registers */
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writes = ath_hal_ini_bank_write(ah, &AH5416(ah)->ah_ini_bank0,
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priv->Bank0Data, 0);
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writes = ath_hal_ini_bank_write(ah, &AH5416(ah)->ah_ini_bank1,
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priv->Bank1Data, writes);
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writes = ath_hal_ini_bank_write(ah, &AH5416(ah)->ah_ini_bank2,
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priv->Bank2Data, writes);
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writes = ath_hal_ini_bank_write(ah, &AH5416(ah)->ah_ini_bank3,
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priv->Bank3Data, writes);
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writes = ath_hal_ini_bank_write(ah, &AH5416(ah)->ah_ini_bank6,
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priv->Bank6Data, writes);
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(void) ath_hal_ini_bank_write(ah, &AH5416(ah)->ah_ini_bank7,
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priv->Bank7Data, writes);
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return AH_TRUE;
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#undef RF_BANK_SETUP
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}
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/*
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* Read the transmit power levels from the structures taken from EEPROM
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* Interpolate read transmit power values for this channel
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* Organize the transmit power values into a table for writing into the hardware
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*/
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static HAL_BOOL
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ar2133SetPowerTable(struct ath_hal *ah, int16_t *pPowerMin, int16_t *pPowerMax,
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const struct ieee80211_channel *chan, uint16_t *rfXpdGain)
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{
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return AH_TRUE;
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}
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#if 0
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static int16_t
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ar2133GetMinPower(struct ath_hal *ah, EXPN_DATA_PER_CHANNEL_5112 *data)
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{
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int i, minIndex;
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int16_t minGain,minPwr,minPcdac,retVal;
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/* Assume NUM_POINTS_XPD0 > 0 */
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minGain = data->pDataPerXPD[0].xpd_gain;
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for (minIndex=0,i=1; i<NUM_XPD_PER_CHANNEL; i++) {
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if (data->pDataPerXPD[i].xpd_gain < minGain) {
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minIndex = i;
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minGain = data->pDataPerXPD[i].xpd_gain;
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}
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}
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minPwr = data->pDataPerXPD[minIndex].pwr_t4[0];
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minPcdac = data->pDataPerXPD[minIndex].pcdac[0];
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for (i=1; i<NUM_POINTS_XPD0; i++) {
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if (data->pDataPerXPD[minIndex].pwr_t4[i] < minPwr) {
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minPwr = data->pDataPerXPD[minIndex].pwr_t4[i];
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minPcdac = data->pDataPerXPD[minIndex].pcdac[i];
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}
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}
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retVal = minPwr - (minPcdac*2);
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return(retVal);
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}
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#endif
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static HAL_BOOL
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ar2133GetChannelMaxMinPower(struct ath_hal *ah,
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const struct ieee80211_channel *chan,
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int16_t *maxPow, int16_t *minPow)
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{
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#if 0
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struct ath_hal_5212 *ahp = AH5212(ah);
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int numChannels=0,i,last;
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int totalD, totalF,totalMin;
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EXPN_DATA_PER_CHANNEL_5112 *data=AH_NULL;
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EEPROM_POWER_EXPN_5112 *powerArray=AH_NULL;
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*maxPow = 0;
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if (IS_CHAN_A(chan)) {
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powerArray = ahp->ah_modePowerArray5112;
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data = powerArray[headerInfo11A].pDataPerChannel;
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numChannels = powerArray[headerInfo11A].numChannels;
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} else if (IS_CHAN_G(chan) || IS_CHAN_108G(chan)) {
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/* XXX - is this correct? Should we also use the same power for turbo G? */
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powerArray = ahp->ah_modePowerArray5112;
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data = powerArray[headerInfo11G].pDataPerChannel;
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numChannels = powerArray[headerInfo11G].numChannels;
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} else if (IS_CHAN_B(chan)) {
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powerArray = ahp->ah_modePowerArray5112;
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data = powerArray[headerInfo11B].pDataPerChannel;
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numChannels = powerArray[headerInfo11B].numChannels;
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} else {
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return (AH_TRUE);
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}
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/* Make sure the channel is in the range of the TP values
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* (freq piers)
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*/
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if ((numChannels < 1) ||
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(chan->channel < data[0].channelValue) ||
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(chan->channel > data[numChannels-1].channelValue))
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return(AH_FALSE);
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/* Linearly interpolate the power value now */
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for (last=0,i=0;
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(i<numChannels) && (chan->channel > data[i].channelValue);
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last=i++);
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totalD = data[i].channelValue - data[last].channelValue;
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if (totalD > 0) {
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totalF = data[i].maxPower_t4 - data[last].maxPower_t4;
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*maxPow = (int8_t) ((totalF*(chan->channel-data[last].channelValue) + data[last].maxPower_t4*totalD)/totalD);
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totalMin = ar2133GetMinPower(ah,&data[i]) - ar2133GetMinPower(ah, &data[last]);
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*minPow = (int8_t) ((totalMin*(chan->channel-data[last].channelValue) + ar2133GetMinPower(ah, &data[last])*totalD)/totalD);
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return (AH_TRUE);
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} else {
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if (chan->channel == data[i].channelValue) {
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*maxPow = data[i].maxPower_t4;
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*minPow = ar2133GetMinPower(ah, &data[i]);
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return(AH_TRUE);
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} else
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return(AH_FALSE);
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}
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#else
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*maxPow = *minPow = 0;
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return AH_FALSE;
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#endif
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}
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/*
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* The ordering of nfarray is thus:
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*
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* nfarray[0]: Chain 0 ctl
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* nfarray[1]: Chain 1 ctl
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* nfarray[2]: Chain 2 ctl
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* nfarray[3]: Chain 0 ext
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* nfarray[4]: Chain 1 ext
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* nfarray[5]: Chain 2 ext
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*/
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static void
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ar2133GetNoiseFloor(struct ath_hal *ah, int16_t nfarray[])
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{
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struct ath_hal_5416 *ahp = AH5416(ah);
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int16_t nf;
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/*
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* Blank nf array - some chips may only
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* have one or two RX chainmasks enabled.
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*/
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nfarray[0] = nfarray[1] = nfarray[2] = 0;
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nfarray[3] = nfarray[4] = nfarray[5] = 0;
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switch (ahp->ah_rx_chainmask) {
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case 0x7:
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nf = MS(OS_REG_READ(ah, AR_PHY_CH2_CCA), AR_PHY_CH2_MINCCA_PWR);
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if (nf & 0x100)
|
|
nf = 0 - ((nf ^ 0x1ff) + 1);
|
|
HALDEBUG(ah, HAL_DEBUG_NFCAL,
|
|
"NF calibrated [ctl] [chain 2] is %d\n", nf);
|
|
nfarray[2] = nf;
|
|
|
|
nf = MS(OS_REG_READ(ah, AR_PHY_CH2_EXT_CCA), AR_PHY_CH2_EXT_MINCCA_PWR);
|
|
if (nf & 0x100)
|
|
nf = 0 - ((nf ^ 0x1ff) + 1);
|
|
HALDEBUG(ah, HAL_DEBUG_NFCAL,
|
|
"NF calibrated [ext] [chain 2] is %d\n", nf);
|
|
nfarray[5] = nf;
|
|
/* fall thru... */
|
|
case 0x3:
|
|
case 0x5:
|
|
nf = MS(OS_REG_READ(ah, AR_PHY_CH1_CCA), AR_PHY_CH1_MINCCA_PWR);
|
|
if (nf & 0x100)
|
|
nf = 0 - ((nf ^ 0x1ff) + 1);
|
|
HALDEBUG(ah, HAL_DEBUG_NFCAL,
|
|
"NF calibrated [ctl] [chain 1] is %d\n", nf);
|
|
nfarray[1] = nf;
|
|
|
|
|
|
nf = MS(OS_REG_READ(ah, AR_PHY_CH1_EXT_CCA), AR_PHY_CH1_EXT_MINCCA_PWR);
|
|
if (nf & 0x100)
|
|
nf = 0 - ((nf ^ 0x1ff) + 1);
|
|
HALDEBUG(ah, HAL_DEBUG_NFCAL,
|
|
"NF calibrated [ext] [chain 1] is %d\n", nf);
|
|
nfarray[4] = nf;
|
|
/* fall thru... */
|
|
case 0x1:
|
|
nf = MS(OS_REG_READ(ah, AR_PHY_CCA), AR_PHY_MINCCA_PWR);
|
|
if (nf & 0x100)
|
|
nf = 0 - ((nf ^ 0x1ff) + 1);
|
|
HALDEBUG(ah, HAL_DEBUG_NFCAL,
|
|
"NF calibrated [ctl] [chain 0] is %d\n", nf);
|
|
nfarray[0] = nf;
|
|
|
|
nf = MS(OS_REG_READ(ah, AR_PHY_EXT_CCA), AR_PHY_EXT_MINCCA_PWR);
|
|
if (nf & 0x100)
|
|
nf = 0 - ((nf ^ 0x1ff) + 1);
|
|
HALDEBUG(ah, HAL_DEBUG_NFCAL,
|
|
"NF calibrated [ext] [chain 0] is %d\n", nf);
|
|
nfarray[3] = nf;
|
|
|
|
break;
|
|
}
|
|
}
|
|
|
|
/*
|
|
* Adjust NF based on statistical values for 5GHz frequencies.
|
|
* Stubbed:Not used by Fowl
|
|
*/
|
|
static int16_t
|
|
ar2133GetNfAdjust(struct ath_hal *ah, const HAL_CHANNEL_INTERNAL *c)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* Free memory for analog bank scratch buffers
|
|
*/
|
|
static void
|
|
ar2133RfDetach(struct ath_hal *ah)
|
|
{
|
|
struct ath_hal_5212 *ahp = AH5212(ah);
|
|
|
|
HALASSERT(ahp->ah_rfHal != AH_NULL);
|
|
ath_hal_free(ahp->ah_rfHal);
|
|
ahp->ah_rfHal = AH_NULL;
|
|
}
|
|
|
|
/*
|
|
* Allocate memory for analog bank scratch buffers
|
|
* Scratch Buffer will be reinitialized every reset so no need to zero now
|
|
*/
|
|
HAL_BOOL
|
|
ar2133RfAttach(struct ath_hal *ah, HAL_STATUS *status)
|
|
{
|
|
struct ath_hal_5212 *ahp = AH5212(ah);
|
|
struct ar2133State *priv;
|
|
uint32_t *bankData;
|
|
|
|
HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: attach AR2133 radio\n", __func__);
|
|
|
|
HALASSERT(ahp->ah_rfHal == AH_NULL);
|
|
priv = ath_hal_malloc(sizeof(struct ar2133State)
|
|
+ AH5416(ah)->ah_ini_bank0.rows * sizeof(uint32_t)
|
|
+ AH5416(ah)->ah_ini_bank1.rows * sizeof(uint32_t)
|
|
+ AH5416(ah)->ah_ini_bank2.rows * sizeof(uint32_t)
|
|
+ AH5416(ah)->ah_ini_bank3.rows * sizeof(uint32_t)
|
|
+ AH5416(ah)->ah_ini_bank6.rows * sizeof(uint32_t)
|
|
+ AH5416(ah)->ah_ini_bank7.rows * sizeof(uint32_t)
|
|
);
|
|
if (priv == AH_NULL) {
|
|
HALDEBUG(ah, HAL_DEBUG_ANY,
|
|
"%s: cannot allocate private state\n", __func__);
|
|
*status = HAL_ENOMEM; /* XXX */
|
|
return AH_FALSE;
|
|
}
|
|
priv->base.rfDetach = ar2133RfDetach;
|
|
priv->base.writeRegs = ar2133WriteRegs;
|
|
priv->base.getRfBank = ar2133GetRfBank;
|
|
priv->base.setChannel = ar2133SetChannel;
|
|
priv->base.setRfRegs = ar2133SetRfRegs;
|
|
priv->base.setPowerTable = ar2133SetPowerTable;
|
|
priv->base.getChannelMaxMinPower = ar2133GetChannelMaxMinPower;
|
|
priv->base.getNfAdjust = ar2133GetNfAdjust;
|
|
|
|
bankData = (uint32_t *) &priv[1];
|
|
priv->Bank0Data = bankData, bankData += AH5416(ah)->ah_ini_bank0.rows;
|
|
priv->Bank1Data = bankData, bankData += AH5416(ah)->ah_ini_bank1.rows;
|
|
priv->Bank2Data = bankData, bankData += AH5416(ah)->ah_ini_bank2.rows;
|
|
priv->Bank3Data = bankData, bankData += AH5416(ah)->ah_ini_bank3.rows;
|
|
priv->Bank6Data = bankData, bankData += AH5416(ah)->ah_ini_bank6.rows;
|
|
priv->Bank7Data = bankData, bankData += AH5416(ah)->ah_ini_bank7.rows;
|
|
|
|
ahp->ah_pcdacTable = priv->pcdacTable;
|
|
ahp->ah_pcdacTableSize = sizeof(priv->pcdacTable);
|
|
ahp->ah_rfHal = &priv->base;
|
|
/*
|
|
* Set noise floor adjust method; we arrange a
|
|
* direct call instead of thunking.
|
|
*/
|
|
AH_PRIVATE(ah)->ah_getNfAdjust = priv->base.getNfAdjust;
|
|
AH_PRIVATE(ah)->ah_getNoiseFloor = ar2133GetNoiseFloor;
|
|
|
|
return AH_TRUE;
|
|
}
|
|
|
|
static HAL_BOOL
|
|
ar2133Probe(struct ath_hal *ah)
|
|
{
|
|
return (AR_SREV_OWL(ah) || AR_SREV_HOWL(ah) || AR_SREV_SOWL(ah));
|
|
}
|
|
|
|
AH_RF(RF2133, ar2133Probe, ar2133RfAttach);
|