Mitchell Horne 2192efc03b RISC-V boot1.efi and loader.efi support ... This implementation doesn't have any major deviations from the other EFI ports. I've copied the boilerplate from arm and arm64. I've tested this with the following boot flows: OpenSBI (M-mode) -> u-boot (S-mode) -> loader.efi -> FreeBSD OpenSBI (M-mode) -> u-boot (S-mode) -> boot1.efi -> loader.efi -> FreeBSD Due to the way that u-boot handles secondary CPUs, OpenSBI >= v0.7 is required, as the HSM extension is needed to bring them up explicitly. Because of this, using BBL as the SBI implementation will not be possible. Additionally, there are a few recent u-boot changes that are required as well, all of which will be present in the upcoming v2020.07 release. Looks good: emaste Differential Revision: https://reviews.freebsd.org/D25135		2020-07-06 18:19:42 +00:00
..
_align.h
_bus.h
_inttypes.h
_limits.h
_stdint.h
_types.h
asm.h
atomic.h
bus_dma_impl.h
bus_dma.h
bus.h
clock.h
counter.h
cpu.h
cpufunc.h
db_machdep.h
dump.h
efi.h
elf.h
encoding.h
endian.h
exec.h
float.h
floatingpoint.h
fpe.h
frame.h
ieeefp.h
in_cksum.h
intr.h
kdb.h
machdep.h	Handle load from loader(8)	2020-06-24 15:20:00 +00:00
md_var.h
memdev.h
metadata.h	RISC-V boot1.efi and loader.efi support	2020-07-06 18:19:42 +00:00
minidump.h
ofw_machdep.h
param.h
pcb.h
pcpu_aux.h
pcpu.h
pmap.h
pmc_mdep.h
proc.h
procctl.h
profile.h
psl.h
pte.h	riscv pmap: zero reserved pte bits in ppn	2020-07-01 19:15:43 +00:00
ptrace.h
reg.h
reloc.h
resource.h
riscvreg.h
runq.h
sbi.h	Add support for HSM SBI extension	2020-05-01 21:55:51 +00:00
setjmp.h
sf_buf.h
sigframe.h
signal.h
smp.h
stack.h
stdarg.h
sysarch.h
trap.h
ucontext.h
vdso.h
vm.h
vmparam.h	Add macros simplifying the fake preload setup	2020-05-28 14:56:11 +00:00