Nathan Whitehorn ff6f4d01f1 Partially revert r208162 while waiting for review on a more comprehensive ... fix. On Apple OpenPICs, the low/high bit of the interrupt sense is only respected for interrupt 0. We currently erroneously program all OpenPIC interrupts level high instead of level low by default, which only matters for some G5 systems where the SATA controllers use IRQ 0. This change is a quick fix that will be reverted once the effect of changing the default interrupt sense on embedded systems is known. MFC after: 3 days		2010-06-05 16:25:25 +00:00
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ata-acard.c
ata-acerlabs.c	Fix use after free on error.	2010-06-05 08:44:40 +00:00
ata-adaptec.c
ata-ahci.c
ata-amd.c
ata-ati.c
ata-cenatek.c
ata-cypress.c
ata-cyrix.c
ata-highpoint.c
ata-intel.c	Fix PCH chipset IDs. They are 0x3bxx, not 0x3axx.	2010-06-04 07:35:59 +00:00
ata-ite.c
ata-jmicron.c
ata-marvell.c
ata-micron.c
ata-national.c
ata-netcell.c	NetCell is a PCI hardware RAID without cable and mode setting.	2010-02-01 15:22:22 +00:00
ata-nvidia.c
ata-promise.c
ata-serverworks.c	Partially revert r208162 while waiting for review on a more comprehensive	2010-06-05 16:25:25 +00:00
ata-siliconimage.c	Report SATA300 chips also as SATA.	2010-02-05 14:41:18 +00:00
ata-sis.c
ata-via.c