d/freebsd-nq
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
14bf23ce31
freebsd-nq/sys/mips/atheros/uart_dev_ar933x.c

755 lines
17 KiB
C
Raw Normal View History

Bring over the initial, CPU-only UART support for the AR933x SoC. This implements the kernel glue needed (getc, putc, rxready). This isn't a 16550 UART, even if the datasheet overview claims so. The Linux ar933x support was used as a reference, however the uart code is a reimplementation. Attentive viewers will note that the uart code is based off of the ns8250 code and the UART bus code is a stubbed-out version of this. I'll be replacing it with non-stubbed versions soon, making this a fully featured driver. Tested: * AP121 reference board (AR933x), booting through the mountroot> prompt; then doing some basic interactive tests in ddb.
2013-03-28 19:27:06 +00:00
/*-
* Copyright (c) 2013 Adrian Chadd <adrian@FreeBSD.org>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/bus.h>
#include <sys/conf.h>
#include <machine/bus.h>
#include <dev/uart/uart.h>
#include <dev/uart/uart_cpu.h>
#include <dev/uart/uart_bus.h>
#include <mips/atheros/ar933x_uart.h>
#include "uart_if.h"
AR933x UART updates: * Default clock is 25MHz; * Remove the UART register macro here - it's not needed as we don't need to "adjust" the register offset / spacing at all; * Remove unused fields in the softc. Tested: * AP121
2013-03-30 04:13:47 +00:00
/*
* Default system clock is 25MHz; see ar933x_chip.c for how
* the startup process determines whether it's 25MHz or 40MHz.
*/
#define DEFAULT_RCLK (25 * 1000 * 1000)
Bring over the initial, CPU-only UART support for the AR933x SoC. This implements the kernel glue needed (getc, putc, rxready). This isn't a 16550 UART, even if the datasheet overview claims so. The Linux ar933x support was used as a reference, however the uart code is a reimplementation. Attentive viewers will note that the uart code is based off of the ns8250 code and the UART bus code is a stubbed-out version of this. I'll be replacing it with non-stubbed versions soon, making this a fully featured driver. Tested: * AP121 reference board (AR933x), booting through the mountroot> prompt; then doing some basic interactive tests in ddb.
2013-03-28 19:27:06 +00:00
#define ar933x_getreg(bas, reg) \
AR933x UART updates: * Default clock is 25MHz; * Remove the UART register macro here - it's not needed as we don't need to "adjust" the register offset / spacing at all; * Remove unused fields in the softc. Tested: * AP121
2013-03-30 04:13:47 +00:00
bus_space_read_4((bas)->bst, (bas)->bsh, reg)
Bring over the initial, CPU-only UART support for the AR933x SoC. This implements the kernel glue needed (getc, putc, rxready). This isn't a 16550 UART, even if the datasheet overview claims so. The Linux ar933x support was used as a reference, however the uart code is a reimplementation. Attentive viewers will note that the uart code is based off of the ns8250 code and the UART bus code is a stubbed-out version of this. I'll be replacing it with non-stubbed versions soon, making this a fully featured driver. Tested: * AP121 reference board (AR933x), booting through the mountroot> prompt; then doing some basic interactive tests in ddb.
2013-03-28 19:27:06 +00:00
#define ar933x_setreg(bas, reg, value) \
AR933x UART updates: * Default clock is 25MHz; * Remove the UART register macro here - it's not needed as we don't need to "adjust" the register offset / spacing at all; * Remove unused fields in the softc. Tested: * AP121
2013-03-30 04:13:47 +00:00
bus_space_write_4((bas)->bst, (bas)->bsh, reg, value)
Bring over the initial, CPU-only UART support for the AR933x SoC. This implements the kernel glue needed (getc, putc, rxready). This isn't a 16550 UART, even if the datasheet overview claims so. The Linux ar933x support was used as a reference, however the uart code is a reimplementation. Attentive viewers will note that the uart code is based off of the ns8250 code and the UART bus code is a stubbed-out version of this. I'll be replacing it with non-stubbed versions soon, making this a fully featured driver. Tested: * AP121 reference board (AR933x), booting through the mountroot> prompt; then doing some basic interactive tests in ddb.
2013-03-28 19:27:06 +00:00
static int
ar933x_drain(struct uart_bas *bas, int what)
{
Implement AR933x polled IO uart bus code. This implements the bus transmit/receive/sigchg/ipend methods with a polled interrupt handler (ipend) rather than enabling hardware interrupts. The FIFO is faked at 16 bytes deep for now, just so the transmit IO side doesn't suck too bad (the callout frequency limits how quickly IO is flushed to the sender, rather than scheduling the callout more frequently whilst there's active TX. But I digress.) Tested: * Atheros AP121 (AR9330) reference board, booting to multi-user interactive mode.
2013-04-04 10:46:33 +00:00
int limit;
Bring over the initial, CPU-only UART support for the AR933x SoC. This implements the kernel glue needed (getc, putc, rxready). This isn't a 16550 UART, even if the datasheet overview claims so. The Linux ar933x support was used as a reference, however the uart code is a reimplementation. Attentive viewers will note that the uart code is based off of the ns8250 code and the UART bus code is a stubbed-out version of this. I'll be replacing it with non-stubbed versions soon, making this a fully featured driver. Tested: * AP121 reference board (AR933x), booting through the mountroot> prompt; then doing some basic interactive tests in ddb.
2013-03-28 19:27:06 +00:00
if (what & UART_DRAIN_TRANSMITTER) {
limit = 10*1024;
Implement AR933x polled IO uart bus code. This implements the bus transmit/receive/sigchg/ipend methods with a polled interrupt handler (ipend) rather than enabling hardware interrupts. The FIFO is faked at 16 bytes deep for now, just so the transmit IO side doesn't suck too bad (the callout frequency limits how quickly IO is flushed to the sender, rather than scheduling the callout more frequently whilst there's active TX. But I digress.) Tested: * Atheros AP121 (AR9330) reference board, booting to multi-user interactive mode.
2013-04-04 10:46:33 +00:00
/* Loop over until the TX FIFO shows entirely clear */
while (--limit) {
if ((ar933x_getreg(bas, AR933X_UART_CS_REG)
& AR933X_UART_CS_TX_BUSY) == 0)
break;
}
Bring over the initial, CPU-only UART support for the AR933x SoC. This implements the kernel glue needed (getc, putc, rxready). This isn't a 16550 UART, even if the datasheet overview claims so. The Linux ar933x support was used as a reference, however the uart code is a reimplementation. Attentive viewers will note that the uart code is based off of the ns8250 code and the UART bus code is a stubbed-out version of this. I'll be replacing it with non-stubbed versions soon, making this a fully featured driver. Tested: * AP121 reference board (AR933x), booting through the mountroot> prompt; then doing some basic interactive tests in ddb.
2013-03-28 19:27:06 +00:00
if (limit == 0) {
return (EIO);
}
}
if (what & UART_DRAIN_RECEIVER) {
limit=10*4096;
Implement AR933x polled IO uart bus code. This implements the bus transmit/receive/sigchg/ipend methods with a polled interrupt handler (ipend) rather than enabling hardware interrupts. The FIFO is faked at 16 bytes deep for now, just so the transmit IO side doesn't suck too bad (the callout frequency limits how quickly IO is flushed to the sender, rather than scheduling the callout more frequently whilst there's active TX. But I digress.) Tested: * Atheros AP121 (AR9330) reference board, booting to multi-user interactive mode.
2013-04-04 10:46:33 +00:00
while (--limit) {
/* XXX duplicated from ar933x_getc() */
/* XXX TODO: refactor! */
/* If there's nothing to read, stop! */
if ((ar933x_getreg(bas, AR933X_UART_DATA_REG) &
AR933X_UART_DATA_RX_CSR) == 0) {
break;
}
/* Read the top of the RX FIFO */
(void) ar933x_getreg(bas, AR933X_UART_DATA_REG);
/* Remove that entry from said RX FIFO */
ar933x_setreg(bas, AR933X_UART_DATA_REG,
AR933X_UART_DATA_RX_CSR);
Bring over the initial, CPU-only UART support for the AR933x SoC. This implements the kernel glue needed (getc, putc, rxready). This isn't a 16550 UART, even if the datasheet overview claims so. The Linux ar933x support was used as a reference, however the uart code is a reimplementation. Attentive viewers will note that the uart code is based off of the ns8250 code and the UART bus code is a stubbed-out version of this. I'll be replacing it with non-stubbed versions soon, making this a fully featured driver. Tested: * AP121 reference board (AR933x), booting through the mountroot> prompt; then doing some basic interactive tests in ddb.
2013-03-28 19:27:06 +00:00
uart_barrier(bas);
Implement AR933x polled IO uart bus code. This implements the bus transmit/receive/sigchg/ipend methods with a polled interrupt handler (ipend) rather than enabling hardware interrupts. The FIFO is faked at 16 bytes deep for now, just so the transmit IO side doesn't suck too bad (the callout frequency limits how quickly IO is flushed to the sender, rather than scheduling the callout more frequently whilst there's active TX. But I digress.) Tested: * Atheros AP121 (AR9330) reference board, booting to multi-user interactive mode.
2013-04-04 10:46:33 +00:00
DELAY(2);
Bring over the initial, CPU-only UART support for the AR933x SoC. This implements the kernel glue needed (getc, putc, rxready). This isn't a 16550 UART, even if the datasheet overview claims so. The Linux ar933x support was used as a reference, however the uart code is a reimplementation. Attentive viewers will note that the uart code is based off of the ns8250 code and the UART bus code is a stubbed-out version of this. I'll be replacing it with non-stubbed versions soon, making this a fully featured driver. Tested: * AP121 reference board (AR933x), booting through the mountroot> prompt; then doing some basic interactive tests in ddb.
2013-03-28 19:27:06 +00:00
}
if (limit == 0) {
return (EIO);
}
}
return (0);
}
AR933x CPU device improvements: * Add baud rate and divisor programming code. See below for more information. * Flesh out ar933x_init() to disable interrupts and program the initial console setup. * Remove #if 0'ed code from ar933x_term(). * Explain what these functions do. Now, the baud rate and divisor code comes from Linux, as a submission to the OpenWRT project and Linux kernel from Gabor Juhos <juhosg@openwrt.org>. The original ticket for this code is https://dev.openwrt.org/ticket/12031 . I've contacted Gabor and asked for his permission to also licence the patch in question (which covers this code) to BSD lience and he's agreed. Hence why I'm including it here in FreeBSD. Tested: * AP121 (AR9330)
2013-03-30 04:31:29 +00:00
/*
* Calculate the baud from the given chip configuration parameters.
*/
static unsigned long
ar933x_uart_get_baud(unsigned int clk, unsigned int scale,
unsigned int step)
{
uint64_t t;
uint32_t div;
div = (2 << 16) * (scale + 1);
t = clk;
t *= step;
t += (div / 2);
t = t / div;
return (t);
}
/*
* Calculate the scale/step with the lowest possible deviation from
* the target baudrate.
*/
static void
ar933x_uart_get_scale_step(struct uart_bas *bas, unsigned int baud,
unsigned int *scale, unsigned int *step)
{
unsigned int tscale;
uint32_t clk;
long min_diff;
clk = bas->rclk;
*scale = 0;
*step = 0;
min_diff = baud;
for (tscale = 0; tscale < AR933X_UART_MAX_SCALE; tscale++) {
uint64_t tstep;
int diff;
tstep = baud * (tscale + 1);
tstep *= (2 << 16);
tstep = tstep / clk;
if (tstep > AR933X_UART_MAX_STEP)
break;
diff = abs(ar933x_uart_get_baud(clk, tscale, tstep) - baud);
if (diff < min_diff) {
min_diff = diff;
*scale = tscale;
*step = tstep;
}
}
}
Bring over the initial, CPU-only UART support for the AR933x SoC. This implements the kernel glue needed (getc, putc, rxready). This isn't a 16550 UART, even if the datasheet overview claims so. The Linux ar933x support was used as a reference, however the uart code is a reimplementation. Attentive viewers will note that the uart code is based off of the ns8250 code and the UART bus code is a stubbed-out version of this. I'll be replacing it with non-stubbed versions soon, making this a fully featured driver. Tested: * AP121 reference board (AR933x), booting through the mountroot> prompt; then doing some basic interactive tests in ddb.
2013-03-28 19:27:06 +00:00
static int
ar933x_param(struct uart_bas *bas, int baudrate, int databits, int stopbits,
int parity)
{
AR933x CPU device improvements: * Add baud rate and divisor programming code. See below for more information. * Flesh out ar933x_init() to disable interrupts and program the initial console setup. * Remove #if 0'ed code from ar933x_term(). * Explain what these functions do. Now, the baud rate and divisor code comes from Linux, as a submission to the OpenWRT project and Linux kernel from Gabor Juhos <juhosg@openwrt.org>. The original ticket for this code is https://dev.openwrt.org/ticket/12031 . I've contacted Gabor and asked for his permission to also licence the patch in question (which covers this code) to BSD lience and he's agreed. Hence why I'm including it here in FreeBSD. Tested: * AP121 (AR9330)
2013-03-30 04:31:29 +00:00
/* UART always 8 bits */
/* UART always 1 stop bit */
/* UART parity is controllable by bits 0:1, ignore for now */
/* Set baudrate if required. */
Bring over the initial, CPU-only UART support for the AR933x SoC. This implements the kernel glue needed (getc, putc, rxready). This isn't a 16550 UART, even if the datasheet overview claims so. The Linux ar933x support was used as a reference, however the uart code is a reimplementation. Attentive viewers will note that the uart code is based off of the ns8250 code and the UART bus code is a stubbed-out version of this. I'll be replacing it with non-stubbed versions soon, making this a fully featured driver. Tested: * AP121 reference board (AR933x), booting through the mountroot> prompt; then doing some basic interactive tests in ddb.
2013-03-28 19:27:06 +00:00
if (baudrate > 0) {
AR933x CPU device improvements: * Add baud rate and divisor programming code. See below for more information. * Flesh out ar933x_init() to disable interrupts and program the initial console setup. * Remove #if 0'ed code from ar933x_term(). * Explain what these functions do. Now, the baud rate and divisor code comes from Linux, as a submission to the OpenWRT project and Linux kernel from Gabor Juhos <juhosg@openwrt.org>. The original ticket for this code is https://dev.openwrt.org/ticket/12031 . I've contacted Gabor and asked for his permission to also licence the patch in question (which covers this code) to BSD lience and he's agreed. Hence why I'm including it here in FreeBSD. Tested: * AP121 (AR9330)
2013-03-30 04:31:29 +00:00
uint32_t clock_scale, clock_step;
/* Find the best fit for the given baud rate */
ar933x_uart_get_scale_step(bas, baudrate, &clock_scale,
&clock_step);
/*
* Program the clock register in its entirety - no need
* for Read-Modify-Write.
*/
ar933x_setreg(bas, AR933X_UART_CLOCK_REG,
((clock_scale & AR933X_UART_CLOCK_SCALE_M)
<< AR933X_UART_CLOCK_SCALE_S) |
(clock_step & AR933X_UART_CLOCK_STEP_M));
Bring over the initial, CPU-only UART support for the AR933x SoC. This implements the kernel glue needed (getc, putc, rxready). This isn't a 16550 UART, even if the datasheet overview claims so. The Linux ar933x support was used as a reference, however the uart code is a reimplementation. Attentive viewers will note that the uart code is based off of the ns8250 code and the UART bus code is a stubbed-out version of this. I'll be replacing it with non-stubbed versions soon, making this a fully featured driver. Tested: * AP121 reference board (AR933x), booting through the mountroot> prompt; then doing some basic interactive tests in ddb.
2013-03-28 19:27:06 +00:00
}
uart_barrier(bas);
return (0);
}
AR933x CPU device improvements: * Add baud rate and divisor programming code. See below for more information. * Flesh out ar933x_init() to disable interrupts and program the initial console setup. * Remove #if 0'ed code from ar933x_term(). * Explain what these functions do. Now, the baud rate and divisor code comes from Linux, as a submission to the OpenWRT project and Linux kernel from Gabor Juhos <juhosg@openwrt.org>. The original ticket for this code is https://dev.openwrt.org/ticket/12031 . I've contacted Gabor and asked for his permission to also licence the patch in question (which covers this code) to BSD lience and he's agreed. Hence why I'm including it here in FreeBSD. Tested: * AP121 (AR9330)
2013-03-30 04:31:29 +00:00
Bring over the initial, CPU-only UART support for the AR933x SoC. This implements the kernel glue needed (getc, putc, rxready). This isn't a 16550 UART, even if the datasheet overview claims so. The Linux ar933x support was used as a reference, however the uart code is a reimplementation. Attentive viewers will note that the uart code is based off of the ns8250 code and the UART bus code is a stubbed-out version of this. I'll be replacing it with non-stubbed versions soon, making this a fully featured driver. Tested: * AP121 reference board (AR933x), booting through the mountroot> prompt; then doing some basic interactive tests in ddb.
2013-03-28 19:27:06 +00:00
/*
* Low-level UART interface.
*/
static int ar933x_probe(struct uart_bas *bas);
static void ar933x_init(struct uart_bas *bas, int, int, int, int);
static void ar933x_term(struct uart_bas *bas);
static void ar933x_putc(struct uart_bas *bas, int);
static int ar933x_rxready(struct uart_bas *bas);
static int ar933x_getc(struct uart_bas *bas, struct mtx *);
static struct uart_ops uart_ar933x_ops = {
.probe = ar933x_probe,
.init = ar933x_init,
.term = ar933x_term,
.putc = ar933x_putc,
.rxready = ar933x_rxready,
.getc = ar933x_getc,
};
static int
ar933x_probe(struct uart_bas *bas)
{
AR933x CPU device improvements: * Add baud rate and divisor programming code. See below for more information. * Flesh out ar933x_init() to disable interrupts and program the initial console setup. * Remove #if 0'ed code from ar933x_term(). * Explain what these functions do. Now, the baud rate and divisor code comes from Linux, as a submission to the OpenWRT project and Linux kernel from Gabor Juhos <juhosg@openwrt.org>. The original ticket for this code is https://dev.openwrt.org/ticket/12031 . I've contacted Gabor and asked for his permission to also licence the patch in question (which covers this code) to BSD lience and he's agreed. Hence why I'm including it here in FreeBSD. Tested: * AP121 (AR9330)
2013-03-30 04:31:29 +00:00
/* We always know this will be here */
Bring over the initial, CPU-only UART support for the AR933x SoC. This implements the kernel glue needed (getc, putc, rxready). This isn't a 16550 UART, even if the datasheet overview claims so. The Linux ar933x support was used as a reference, however the uart code is a reimplementation. Attentive viewers will note that the uart code is based off of the ns8250 code and the UART bus code is a stubbed-out version of this. I'll be replacing it with non-stubbed versions soon, making this a fully featured driver. Tested: * AP121 reference board (AR933x), booting through the mountroot> prompt; then doing some basic interactive tests in ddb.
2013-03-28 19:27:06 +00:00
return (0);
}
static void
ar933x_init(struct uart_bas *bas, int baudrate, int databits, int stopbits,
int parity)
{
AR933x CPU device improvements: * Add baud rate and divisor programming code. See below for more information. * Flesh out ar933x_init() to disable interrupts and program the initial console setup. * Remove #if 0'ed code from ar933x_term(). * Explain what these functions do. Now, the baud rate and divisor code comes from Linux, as a submission to the OpenWRT project and Linux kernel from Gabor Juhos <juhosg@openwrt.org>. The original ticket for this code is https://dev.openwrt.org/ticket/12031 . I've contacted Gabor and asked for his permission to also licence the patch in question (which covers this code) to BSD lience and he's agreed. Hence why I'm including it here in FreeBSD. Tested: * AP121 (AR9330)
2013-03-30 04:31:29 +00:00
uint32_t reg;
Bring over the initial, CPU-only UART support for the AR933x SoC. This implements the kernel glue needed (getc, putc, rxready). This isn't a 16550 UART, even if the datasheet overview claims so. The Linux ar933x support was used as a reference, however the uart code is a reimplementation. Attentive viewers will note that the uart code is based off of the ns8250 code and the UART bus code is a stubbed-out version of this. I'll be replacing it with non-stubbed versions soon, making this a fully featured driver. Tested: * AP121 reference board (AR933x), booting through the mountroot> prompt; then doing some basic interactive tests in ddb.
2013-03-28 19:27:06 +00:00
AR933x CPU device improvements: * Add baud rate and divisor programming code. See below for more information. * Flesh out ar933x_init() to disable interrupts and program the initial console setup. * Remove #if 0'ed code from ar933x_term(). * Explain what these functions do. Now, the baud rate and divisor code comes from Linux, as a submission to the OpenWRT project and Linux kernel from Gabor Juhos <juhosg@openwrt.org>. The original ticket for this code is https://dev.openwrt.org/ticket/12031 . I've contacted Gabor and asked for his permission to also licence the patch in question (which covers this code) to BSD lience and he's agreed. Hence why I'm including it here in FreeBSD. Tested: * AP121 (AR9330)
2013-03-30 04:31:29 +00:00
/* Setup default parameters */
Bring over the initial, CPU-only UART support for the AR933x SoC. This implements the kernel glue needed (getc, putc, rxready). This isn't a 16550 UART, even if the datasheet overview claims so. The Linux ar933x support was used as a reference, however the uart code is a reimplementation. Attentive viewers will note that the uart code is based off of the ns8250 code and the UART bus code is a stubbed-out version of this. I'll be replacing it with non-stubbed versions soon, making this a fully featured driver. Tested: * AP121 reference board (AR933x), booting through the mountroot> prompt; then doing some basic interactive tests in ddb.
2013-03-28 19:27:06 +00:00
ar933x_param(bas, baudrate, databits, stopbits, parity);
AR933x CPU device improvements: * Add baud rate and divisor programming code. See below for more information. * Flesh out ar933x_init() to disable interrupts and program the initial console setup. * Remove #if 0'ed code from ar933x_term(). * Explain what these functions do. Now, the baud rate and divisor code comes from Linux, as a submission to the OpenWRT project and Linux kernel from Gabor Juhos <juhosg@openwrt.org>. The original ticket for this code is https://dev.openwrt.org/ticket/12031 . I've contacted Gabor and asked for his permission to also licence the patch in question (which covers this code) to BSD lience and he's agreed. Hence why I'm including it here in FreeBSD. Tested: * AP121 (AR9330)
2013-03-30 04:31:29 +00:00
/* XXX Force enable UART in case it was disabled */
Bring over the initial, CPU-only UART support for the AR933x SoC. This implements the kernel glue needed (getc, putc, rxready). This isn't a 16550 UART, even if the datasheet overview claims so. The Linux ar933x support was used as a reference, however the uart code is a reimplementation. Attentive viewers will note that the uart code is based off of the ns8250 code and the UART bus code is a stubbed-out version of this. I'll be replacing it with non-stubbed versions soon, making this a fully featured driver. Tested: * AP121 reference board (AR933x), booting through the mountroot> prompt; then doing some basic interactive tests in ddb.
2013-03-28 19:27:06 +00:00
AR933x CPU device improvements: * Add baud rate and divisor programming code. See below for more information. * Flesh out ar933x_init() to disable interrupts and program the initial console setup. * Remove #if 0'ed code from ar933x_term(). * Explain what these functions do. Now, the baud rate and divisor code comes from Linux, as a submission to the OpenWRT project and Linux kernel from Gabor Juhos <juhosg@openwrt.org>. The original ticket for this code is https://dev.openwrt.org/ticket/12031 . I've contacted Gabor and asked for his permission to also licence the patch in question (which covers this code) to BSD lience and he's agreed. Hence why I'm including it here in FreeBSD. Tested: * AP121 (AR9330)
2013-03-30 04:31:29 +00:00
/* Disable all interrupts */
ar933x_setreg(bas, AR933X_UART_INT_EN_REG, 0x00000000);
/* Disable the host interrupt */
reg = ar933x_getreg(bas, AR933X_UART_CS_REG);
reg &= ~AR933X_UART_CS_HOST_INT_EN;
ar933x_setreg(bas, AR933X_UART_CS_REG, reg);
Bring over the initial, CPU-only UART support for the AR933x SoC. This implements the kernel glue needed (getc, putc, rxready). This isn't a 16550 UART, even if the datasheet overview claims so. The Linux ar933x support was used as a reference, however the uart code is a reimplementation. Attentive viewers will note that the uart code is based off of the ns8250 code and the UART bus code is a stubbed-out version of this. I'll be replacing it with non-stubbed versions soon, making this a fully featured driver. Tested: * AP121 reference board (AR933x), booting through the mountroot> prompt; then doing some basic interactive tests in ddb.
2013-03-28 19:27:06 +00:00
uart_barrier(bas);
AR933x CPU device improvements: * Add baud rate and divisor programming code. See below for more information. * Flesh out ar933x_init() to disable interrupts and program the initial console setup. * Remove #if 0'ed code from ar933x_term(). * Explain what these functions do. Now, the baud rate and divisor code comes from Linux, as a submission to the OpenWRT project and Linux kernel from Gabor Juhos <juhosg@openwrt.org>. The original ticket for this code is https://dev.openwrt.org/ticket/12031 . I've contacted Gabor and asked for his permission to also licence the patch in question (which covers this code) to BSD lience and he's agreed. Hence why I'm including it here in FreeBSD. Tested: * AP121 (AR9330)
2013-03-30 04:31:29 +00:00
/* XXX Set RTS/DTR? */
Bring over the initial, CPU-only UART support for the AR933x SoC. This implements the kernel glue needed (getc, putc, rxready). This isn't a 16550 UART, even if the datasheet overview claims so. The Linux ar933x support was used as a reference, however the uart code is a reimplementation. Attentive viewers will note that the uart code is based off of the ns8250 code and the UART bus code is a stubbed-out version of this. I'll be replacing it with non-stubbed versions soon, making this a fully featured driver. Tested: * AP121 reference board (AR933x), booting through the mountroot> prompt; then doing some basic interactive tests in ddb.
2013-03-28 19:27:06 +00:00
}
AR933x CPU device improvements: * Add baud rate and divisor programming code. See below for more information. * Flesh out ar933x_init() to disable interrupts and program the initial console setup. * Remove #if 0'ed code from ar933x_term(). * Explain what these functions do. Now, the baud rate and divisor code comes from Linux, as a submission to the OpenWRT project and Linux kernel from Gabor Juhos <juhosg@openwrt.org>. The original ticket for this code is https://dev.openwrt.org/ticket/12031 . I've contacted Gabor and asked for his permission to also licence the patch in question (which covers this code) to BSD lience and he's agreed. Hence why I'm including it here in FreeBSD. Tested: * AP121 (AR9330)
2013-03-30 04:31:29 +00:00
/*
* Detach from console.
*/
Bring over the initial, CPU-only UART support for the AR933x SoC. This implements the kernel glue needed (getc, putc, rxready). This isn't a 16550 UART, even if the datasheet overview claims so. The Linux ar933x support was used as a reference, however the uart code is a reimplementation. Attentive viewers will note that the uart code is based off of the ns8250 code and the UART bus code is a stubbed-out version of this. I'll be replacing it with non-stubbed versions soon, making this a fully featured driver. Tested: * AP121 reference board (AR933x), booting through the mountroot> prompt; then doing some basic interactive tests in ddb.
2013-03-28 19:27:06 +00:00
static void
ar933x_term(struct uart_bas *bas)
{
AR933x CPU device improvements: * Add baud rate and divisor programming code. See below for more information. * Flesh out ar933x_init() to disable interrupts and program the initial console setup. * Remove #if 0'ed code from ar933x_term(). * Explain what these functions do. Now, the baud rate and divisor code comes from Linux, as a submission to the OpenWRT project and Linux kernel from Gabor Juhos <juhosg@openwrt.org>. The original ticket for this code is https://dev.openwrt.org/ticket/12031 . I've contacted Gabor and asked for his permission to also licence the patch in question (which covers this code) to BSD lience and he's agreed. Hence why I'm including it here in FreeBSD. Tested: * AP121 (AR9330)
2013-03-30 04:31:29 +00:00
/* XXX TODO */
Bring over the initial, CPU-only UART support for the AR933x SoC. This implements the kernel glue needed (getc, putc, rxready). This isn't a 16550 UART, even if the datasheet overview claims so. The Linux ar933x support was used as a reference, however the uart code is a reimplementation. Attentive viewers will note that the uart code is based off of the ns8250 code and the UART bus code is a stubbed-out version of this. I'll be replacing it with non-stubbed versions soon, making this a fully featured driver. Tested: * AP121 reference board (AR933x), booting through the mountroot> prompt; then doing some basic interactive tests in ddb.
2013-03-28 19:27:06 +00:00
}
static void
ar933x_putc(struct uart_bas *bas, int c)
{
int limit;
limit = 250000;
/* Wait for space in the TX FIFO */
while ( ((ar933x_getreg(bas, AR933X_UART_DATA_REG) &
AR933X_UART_DATA_TX_CSR) == 0) && --limit)
DELAY(4);
/* Write the actual byte */
ar933x_setreg(bas, AR933X_UART_DATA_REG,
(c & 0xff) | AR933X_UART_DATA_TX_CSR);
}
static int
ar933x_rxready(struct uart_bas *bas)
{
/* Wait for a character to come ready */
return (!!(ar933x_getreg(bas, AR933X_UART_DATA_REG)
& AR933X_UART_DATA_RX_CSR));
}
static int
ar933x_getc(struct uart_bas *bas, struct mtx *hwmtx)
{
int c;
uart_lock(hwmtx);
/* Wait for a character to come ready */
while ((ar933x_getreg(bas, AR933X_UART_DATA_REG) &
AR933X_UART_DATA_RX_CSR) == 0) {
uart_unlock(hwmtx);
DELAY(4);
uart_lock(hwmtx);
}
/* Read the top of the RX FIFO */
c = ar933x_getreg(bas, AR933X_UART_DATA_REG) & 0xff;
/* Remove that entry from said RX FIFO */
ar933x_setreg(bas, AR933X_UART_DATA_REG, AR933X_UART_DATA_RX_CSR);
uart_unlock(hwmtx);
return (c);
}
/*
* High-level UART interface.
*/
struct ar933x_softc {
struct uart_softc base;
AR933x UART updates: * Default clock is 25MHz; * Remove the UART register macro here - it's not needed as we don't need to "adjust" the register offset / spacing at all; * Remove unused fields in the softc. Tested: * AP121
2013-03-30 04:13:47 +00:00
Bring over the initial, CPU-only UART support for the AR933x SoC. This implements the kernel glue needed (getc, putc, rxready). This isn't a 16550 UART, even if the datasheet overview claims so. The Linux ar933x support was used as a reference, however the uart code is a reimplementation. Attentive viewers will note that the uart code is based off of the ns8250 code and the UART bus code is a stubbed-out version of this. I'll be replacing it with non-stubbed versions soon, making this a fully featured driver. Tested: * AP121 reference board (AR933x), booting through the mountroot> prompt; then doing some basic interactive tests in ddb.
2013-03-28 19:27:06 +00:00
uint32_t u_ier;
};
static int ar933x_bus_attach(struct uart_softc *);
static int ar933x_bus_detach(struct uart_softc *);
static int ar933x_bus_flush(struct uart_softc *, int);
static int ar933x_bus_getsig(struct uart_softc *);
static int ar933x_bus_ioctl(struct uart_softc *, int, intptr_t);
static int ar933x_bus_ipend(struct uart_softc *);
static int ar933x_bus_param(struct uart_softc *, int, int, int, int);
static int ar933x_bus_probe(struct uart_softc *);
static int ar933x_bus_receive(struct uart_softc *);
static int ar933x_bus_setsig(struct uart_softc *, int);
static int ar933x_bus_transmit(struct uart_softc *);
static kobj_method_t ar933x_methods[] = {
KOBJMETHOD(uart_attach, ar933x_bus_attach),
KOBJMETHOD(uart_detach, ar933x_bus_detach),
KOBJMETHOD(uart_flush, ar933x_bus_flush),
KOBJMETHOD(uart_getsig, ar933x_bus_getsig),
KOBJMETHOD(uart_ioctl, ar933x_bus_ioctl),
KOBJMETHOD(uart_ipend, ar933x_bus_ipend),
KOBJMETHOD(uart_param, ar933x_bus_param),
KOBJMETHOD(uart_probe, ar933x_bus_probe),
KOBJMETHOD(uart_receive, ar933x_bus_receive),
KOBJMETHOD(uart_setsig, ar933x_bus_setsig),
KOBJMETHOD(uart_transmit, ar933x_bus_transmit),
{ 0, 0 }
};
struct uart_class uart_ar933x_class = {
"ar933x",
ar933x_methods,
sizeof(struct ar933x_softc),
.uc_ops = &uart_ar933x_ops,
.uc_range = 8,
.uc_rclk = DEFAULT_RCLK
};
#define SIGCHG(c, i, s, d) \
if (c) { \
i |= (i & s) ? s : s | d; \
} else { \
i = (i & s) ? (i & ~s) | d : i; \
}
static int
ar933x_bus_attach(struct uart_softc *sc)
{
Implement the AR933x interrupt driven UART code. * Enable RX and host interrupts during bus probe/attach * Disable all interrupts (+ host ISR) during bus detach * Enable TX DONE interrupt only when we start transmitting; clear it when we're done. * The RX/TX FIFO depth is still conjecture on my part. I'll fix this shortly. * The TX FIFO interrupt isn't an "empty" interrupt, it's an "almost empty" interrupt. Sigh. So.. * .. in ar933x_bus_transmit(), wait for the FIFO to drain before continuing. I dislike having to wait for the FIFO to drain, alas. Tested: * Atheros AP121 board, AR9331 SoC. TODO: * RX/TX overflow, RX error, BREAK support, etc. * Figure out the true RX/TX FIFO depth.
2013-04-05 00:26:06 +00:00
struct ar933x_softc *u = (struct ar933x_softc *)sc;
struct uart_bas *bas = &sc->sc_bas;
uint32_t reg;
Implement AR933x polled IO uart bus code. This implements the bus transmit/receive/sigchg/ipend methods with a polled interrupt handler (ipend) rather than enabling hardware interrupts. The FIFO is faked at 16 bytes deep for now, just so the transmit IO side doesn't suck too bad (the callout frequency limits how quickly IO is flushed to the sender, rather than scheduling the callout more frequently whilst there's active TX. But I digress.) Tested: * Atheros AP121 (AR9330) reference board, booting to multi-user interactive mode.
2013-04-04 10:46:33 +00:00
/* XXX TODO: flush transmitter */
Bring over the initial, CPU-only UART support for the AR933x SoC. This implements the kernel glue needed (getc, putc, rxready). This isn't a 16550 UART, even if the datasheet overview claims so. The Linux ar933x support was used as a reference, however the uart code is a reimplementation. Attentive viewers will note that the uart code is based off of the ns8250 code and the UART bus code is a stubbed-out version of this. I'll be replacing it with non-stubbed versions soon, making this a fully featured driver. Tested: * AP121 reference board (AR933x), booting through the mountroot> prompt; then doing some basic interactive tests in ddb.
2013-03-28 19:27:06 +00:00
Implement the AR933x interrupt driven UART code. * Enable RX and host interrupts during bus probe/attach * Disable all interrupts (+ host ISR) during bus detach * Enable TX DONE interrupt only when we start transmitting; clear it when we're done. * The RX/TX FIFO depth is still conjecture on my part. I'll fix this shortly. * The TX FIFO interrupt isn't an "empty" interrupt, it's an "almost empty" interrupt. Sigh. So.. * .. in ar933x_bus_transmit(), wait for the FIFO to drain before continuing. I dislike having to wait for the FIFO to drain, alas. Tested: * Atheros AP121 board, AR9331 SoC. TODO: * RX/TX overflow, RX error, BREAK support, etc. * Figure out the true RX/TX FIFO depth.
2013-04-05 00:26:06 +00:00
/*
* Setup initial interrupt notifications.
*
* XXX for now, just RX FIFO valid.
* Later on (when they're handled), also handle
* RX errors/overflow.
*/
u->u_ier = AR933X_UART_INT_RX_VALID;
/* Enable RX interrupts to kick-start things */
ar933x_setreg(bas, AR933X_UART_INT_EN_REG, u->u_ier);
Bring over the initial, CPU-only UART support for the AR933x SoC. This implements the kernel glue needed (getc, putc, rxready). This isn't a 16550 UART, even if the datasheet overview claims so. The Linux ar933x support was used as a reference, however the uart code is a reimplementation. Attentive viewers will note that the uart code is based off of the ns8250 code and the UART bus code is a stubbed-out version of this. I'll be replacing it with non-stubbed versions soon, making this a fully featured driver. Tested: * AP121 reference board (AR933x), booting through the mountroot> prompt; then doing some basic interactive tests in ddb.
2013-03-28 19:27:06 +00:00
Implement the AR933x interrupt driven UART code. * Enable RX and host interrupts during bus probe/attach * Disable all interrupts (+ host ISR) during bus detach * Enable TX DONE interrupt only when we start transmitting; clear it when we're done. * The RX/TX FIFO depth is still conjecture on my part. I'll fix this shortly. * The TX FIFO interrupt isn't an "empty" interrupt, it's an "almost empty" interrupt. Sigh. So.. * .. in ar933x_bus_transmit(), wait for the FIFO to drain before continuing. I dislike having to wait for the FIFO to drain, alas. Tested: * Atheros AP121 board, AR9331 SoC. TODO: * RX/TX overflow, RX error, BREAK support, etc. * Figure out the true RX/TX FIFO depth.
2013-04-05 00:26:06 +00:00
/* Enable the host interrupt now */
reg = ar933x_getreg(bas, AR933X_UART_CS_REG);
reg |= AR933X_UART_CS_HOST_INT_EN;
ar933x_setreg(bas, AR933X_UART_CS_REG, reg);
Bring over the initial, CPU-only UART support for the AR933x SoC. This implements the kernel glue needed (getc, putc, rxready). This isn't a 16550 UART, even if the datasheet overview claims so. The Linux ar933x support was used as a reference, however the uart code is a reimplementation. Attentive viewers will note that the uart code is based off of the ns8250 code and the UART bus code is a stubbed-out version of this. I'll be replacing it with non-stubbed versions soon, making this a fully featured driver. Tested: * AP121 reference board (AR933x), booting through the mountroot> prompt; then doing some basic interactive tests in ddb.
2013-03-28 19:27:06 +00:00
return (0);
}
static int
ar933x_bus_detach(struct uart_softc *sc)
{
Implement the AR933x interrupt driven UART code. * Enable RX and host interrupts during bus probe/attach * Disable all interrupts (+ host ISR) during bus detach * Enable TX DONE interrupt only when we start transmitting; clear it when we're done. * The RX/TX FIFO depth is still conjecture on my part. I'll fix this shortly. * The TX FIFO interrupt isn't an "empty" interrupt, it's an "almost empty" interrupt. Sigh. So.. * .. in ar933x_bus_transmit(), wait for the FIFO to drain before continuing. I dislike having to wait for the FIFO to drain, alas. Tested: * Atheros AP121 board, AR9331 SoC. TODO: * RX/TX overflow, RX error, BREAK support, etc. * Figure out the true RX/TX FIFO depth.
2013-04-05 00:26:06 +00:00
struct uart_bas *bas = &sc->sc_bas;
uint32_t reg;
Bring over the initial, CPU-only UART support for the AR933x SoC. This implements the kernel glue needed (getc, putc, rxready). This isn't a 16550 UART, even if the datasheet overview claims so. The Linux ar933x support was used as a reference, however the uart code is a reimplementation. Attentive viewers will note that the uart code is based off of the ns8250 code and the UART bus code is a stubbed-out version of this. I'll be replacing it with non-stubbed versions soon, making this a fully featured driver. Tested: * AP121 reference board (AR933x), booting through the mountroot> prompt; then doing some basic interactive tests in ddb.
2013-03-28 19:27:06 +00:00
Implement the AR933x interrupt driven UART code. * Enable RX and host interrupts during bus probe/attach * Disable all interrupts (+ host ISR) during bus detach * Enable TX DONE interrupt only when we start transmitting; clear it when we're done. * The RX/TX FIFO depth is still conjecture on my part. I'll fix this shortly. * The TX FIFO interrupt isn't an "empty" interrupt, it's an "almost empty" interrupt. Sigh. So.. * .. in ar933x_bus_transmit(), wait for the FIFO to drain before continuing. I dislike having to wait for the FIFO to drain, alas. Tested: * Atheros AP121 board, AR9331 SoC. TODO: * RX/TX overflow, RX error, BREAK support, etc. * Figure out the true RX/TX FIFO depth.
2013-04-05 00:26:06 +00:00
/* Disable all interrupts */
ar933x_setreg(bas, AR933X_UART_INT_EN_REG, 0x00000000);
Implement AR933x polled IO uart bus code. This implements the bus transmit/receive/sigchg/ipend methods with a polled interrupt handler (ipend) rather than enabling hardware interrupts. The FIFO is faked at 16 bytes deep for now, just so the transmit IO side doesn't suck too bad (the callout frequency limits how quickly IO is flushed to the sender, rather than scheduling the callout more frequently whilst there's active TX. But I digress.) Tested: * Atheros AP121 (AR9330) reference board, booting to multi-user interactive mode.
2013-04-04 10:46:33 +00:00
Implement the AR933x interrupt driven UART code. * Enable RX and host interrupts during bus probe/attach * Disable all interrupts (+ host ISR) during bus detach * Enable TX DONE interrupt only when we start transmitting; clear it when we're done. * The RX/TX FIFO depth is still conjecture on my part. I'll fix this shortly. * The TX FIFO interrupt isn't an "empty" interrupt, it's an "almost empty" interrupt. Sigh. So.. * .. in ar933x_bus_transmit(), wait for the FIFO to drain before continuing. I dislike having to wait for the FIFO to drain, alas. Tested: * Atheros AP121 board, AR9331 SoC. TODO: * RX/TX overflow, RX error, BREAK support, etc. * Figure out the true RX/TX FIFO depth.
2013-04-05 00:26:06 +00:00
/* Disable the host interrupt */
reg = ar933x_getreg(bas, AR933X_UART_CS_REG);
reg &= ~AR933X_UART_CS_HOST_INT_EN;
ar933x_setreg(bas, AR933X_UART_CS_REG, reg);
uart_barrier(bas);
Implement AR933x polled IO uart bus code. This implements the bus transmit/receive/sigchg/ipend methods with a polled interrupt handler (ipend) rather than enabling hardware interrupts. The FIFO is faked at 16 bytes deep for now, just so the transmit IO side doesn't suck too bad (the callout frequency limits how quickly IO is flushed to the sender, rather than scheduling the callout more frequently whilst there's active TX. But I digress.) Tested: * Atheros AP121 (AR9330) reference board, booting to multi-user interactive mode.
2013-04-04 10:46:33 +00:00
Bring over the initial, CPU-only UART support for the AR933x SoC. This implements the kernel glue needed (getc, putc, rxready). This isn't a 16550 UART, even if the datasheet overview claims so. The Linux ar933x support was used as a reference, however the uart code is a reimplementation. Attentive viewers will note that the uart code is based off of the ns8250 code and the UART bus code is a stubbed-out version of this. I'll be replacing it with non-stubbed versions soon, making this a fully featured driver. Tested: * AP121 reference board (AR933x), booting through the mountroot> prompt; then doing some basic interactive tests in ddb.
2013-03-28 19:27:06 +00:00
return (0);
}
static int
ar933x_bus_flush(struct uart_softc *sc, int what)
{
struct uart_bas *bas;
bas = &sc->sc_bas;
uart_lock(sc->sc_hwmtx);
Implement AR933x polled IO uart bus code. This implements the bus transmit/receive/sigchg/ipend methods with a polled interrupt handler (ipend) rather than enabling hardware interrupts. The FIFO is faked at 16 bytes deep for now, just so the transmit IO side doesn't suck too bad (the callout frequency limits how quickly IO is flushed to the sender, rather than scheduling the callout more frequently whilst there's active TX. But I digress.) Tested: * Atheros AP121 (AR9330) reference board, booting to multi-user interactive mode.
2013-04-04 10:46:33 +00:00
ar933x_drain(bas, what);
Bring over the initial, CPU-only UART support for the AR933x SoC. This implements the kernel glue needed (getc, putc, rxready). This isn't a 16550 UART, even if the datasheet overview claims so. The Linux ar933x support was used as a reference, however the uart code is a reimplementation. Attentive viewers will note that the uart code is based off of the ns8250 code and the UART bus code is a stubbed-out version of this. I'll be replacing it with non-stubbed versions soon, making this a fully featured driver. Tested: * AP121 reference board (AR933x), booting through the mountroot> prompt; then doing some basic interactive tests in ddb.
2013-03-28 19:27:06 +00:00
uart_unlock(sc->sc_hwmtx);
Implement AR933x polled IO uart bus code. This implements the bus transmit/receive/sigchg/ipend methods with a polled interrupt handler (ipend) rather than enabling hardware interrupts. The FIFO is faked at 16 bytes deep for now, just so the transmit IO side doesn't suck too bad (the callout frequency limits how quickly IO is flushed to the sender, rather than scheduling the callout more frequently whilst there's active TX. But I digress.) Tested: * Atheros AP121 (AR9330) reference board, booting to multi-user interactive mode.
2013-04-04 10:46:33 +00:00
return (0);
Bring over the initial, CPU-only UART support for the AR933x SoC. This implements the kernel glue needed (getc, putc, rxready). This isn't a 16550 UART, even if the datasheet overview claims so. The Linux ar933x support was used as a reference, however the uart code is a reimplementation. Attentive viewers will note that the uart code is based off of the ns8250 code and the UART bus code is a stubbed-out version of this. I'll be replacing it with non-stubbed versions soon, making this a fully featured driver. Tested: * AP121 reference board (AR933x), booting through the mountroot> prompt; then doing some basic interactive tests in ddb.
2013-03-28 19:27:06 +00:00
}
static int
ar933x_bus_getsig(struct uart_softc *sc)
{
Implement AR933x polled IO uart bus code. This implements the bus transmit/receive/sigchg/ipend methods with a polled interrupt handler (ipend) rather than enabling hardware interrupts. The FIFO is faked at 16 bytes deep for now, just so the transmit IO side doesn't suck too bad (the callout frequency limits how quickly IO is flushed to the sender, rather than scheduling the callout more frequently whilst there's active TX. But I digress.) Tested: * Atheros AP121 (AR9330) reference board, booting to multi-user interactive mode.
2013-04-04 10:46:33 +00:00
uint32_t sig = sc->sc_hwsig;
/*
* For now, let's just return that DSR/DCD/CTS is asserted.
*
* XXX TODO: actually verify whether this is correct!
*/
SIGCHG(1, sig, SER_DSR, SER_DDSR);
SIGCHG(1, sig, SER_CTS, SER_DCTS);
SIGCHG(1, sig, SER_DCD, SER_DDCD);
SIGCHG(1, sig, SER_RI, SER_DRI);
sc->sc_hwsig = sig & ~SER_MASK_DELTA;
Bring over the initial, CPU-only UART support for the AR933x SoC. This implements the kernel glue needed (getc, putc, rxready). This isn't a 16550 UART, even if the datasheet overview claims so. The Linux ar933x support was used as a reference, however the uart code is a reimplementation. Attentive viewers will note that the uart code is based off of the ns8250 code and the UART bus code is a stubbed-out version of this. I'll be replacing it with non-stubbed versions soon, making this a fully featured driver. Tested: * AP121 reference board (AR933x), booting through the mountroot> prompt; then doing some basic interactive tests in ddb.
2013-03-28 19:27:06 +00:00
return (sig);
}
static int
ar933x_bus_ioctl(struct uart_softc *sc, int request, intptr_t data)
{
#if 0
struct uart_bas *bas;
int baudrate, divisor, error;
uint8_t efr, lcr;
bas = &sc->sc_bas;
error = 0;
uart_lock(sc->sc_hwmtx);
switch (request) {
case UART_IOCTL_BREAK:
lcr = uart_getreg(bas, REG_LCR);
if (data)
lcr |= LCR_SBREAK;
else
lcr &= ~LCR_SBREAK;
uart_setreg(bas, REG_LCR, lcr);
uart_barrier(bas);
break;
case UART_IOCTL_IFLOW:
lcr = uart_getreg(bas, REG_LCR);
uart_barrier(bas);
uart_setreg(bas, REG_LCR, 0xbf);
uart_barrier(bas);
efr = uart_getreg(bas, REG_EFR);
if (data)
efr |= EFR_RTS;
else
efr &= ~EFR_RTS;
uart_setreg(bas, REG_EFR, efr);
uart_barrier(bas);
uart_setreg(bas, REG_LCR, lcr);
uart_barrier(bas);
break;
case UART_IOCTL_OFLOW:
lcr = uart_getreg(bas, REG_LCR);
uart_barrier(bas);
uart_setreg(bas, REG_LCR, 0xbf);
uart_barrier(bas);
efr = uart_getreg(bas, REG_EFR);
if (data)
efr |= EFR_CTS;
else
efr &= ~EFR_CTS;
uart_setreg(bas, REG_EFR, efr);
uart_barrier(bas);
uart_setreg(bas, REG_LCR, lcr);
uart_barrier(bas);
break;
case UART_IOCTL_BAUD:
lcr = uart_getreg(bas, REG_LCR);
uart_setreg(bas, REG_LCR, lcr | LCR_DLAB);
uart_barrier(bas);
divisor = uart_getreg(bas, REG_DLL) |
(uart_getreg(bas, REG_DLH) << 8);
uart_barrier(bas);
uart_setreg(bas, REG_LCR, lcr);
uart_barrier(bas);
baudrate = (divisor > 0) ? bas->rclk / divisor / 16 : 0;
if (baudrate > 0)
*(int*)data = baudrate;
else
error = ENXIO;
break;
default:
error = EINVAL;
break;
}
uart_unlock(sc->sc_hwmtx);
return (error);
#endif
return (ENXIO);
}
Implement AR933x polled IO uart bus code. This implements the bus transmit/receive/sigchg/ipend methods with a polled interrupt handler (ipend) rather than enabling hardware interrupts. The FIFO is faked at 16 bytes deep for now, just so the transmit IO side doesn't suck too bad (the callout frequency limits how quickly IO is flushed to the sender, rather than scheduling the callout more frequently whilst there's active TX. But I digress.) Tested: * Atheros AP121 (AR9330) reference board, booting to multi-user interactive mode.
2013-04-04 10:46:33 +00:00
/*
* Bus interrupt handler.
*
* For now, system interrupts are disabled.
* So this is just called from a callout in uart_core.c
* to poll various state.
*/
Bring over the initial, CPU-only UART support for the AR933x SoC. This implements the kernel glue needed (getc, putc, rxready). This isn't a 16550 UART, even if the datasheet overview claims so. The Linux ar933x support was used as a reference, however the uart code is a reimplementation. Attentive viewers will note that the uart code is based off of the ns8250 code and the UART bus code is a stubbed-out version of this. I'll be replacing it with non-stubbed versions soon, making this a fully featured driver. Tested: * AP121 reference board (AR933x), booting through the mountroot> prompt; then doing some basic interactive tests in ddb.
2013-03-28 19:27:06 +00:00
static int
ar933x_bus_ipend(struct uart_softc *sc)
{
Implement the AR933x interrupt driven UART code. * Enable RX and host interrupts during bus probe/attach * Disable all interrupts (+ host ISR) during bus detach * Enable TX DONE interrupt only when we start transmitting; clear it when we're done. * The RX/TX FIFO depth is still conjecture on my part. I'll fix this shortly. * The TX FIFO interrupt isn't an "empty" interrupt, it's an "almost empty" interrupt. Sigh. So.. * .. in ar933x_bus_transmit(), wait for the FIFO to drain before continuing. I dislike having to wait for the FIFO to drain, alas. Tested: * Atheros AP121 board, AR9331 SoC. TODO: * RX/TX overflow, RX error, BREAK support, etc. * Figure out the true RX/TX FIFO depth.
2013-04-05 00:26:06 +00:00
struct ar933x_softc *u = (struct ar933x_softc *)sc;
Implement AR933x polled IO uart bus code. This implements the bus transmit/receive/sigchg/ipend methods with a polled interrupt handler (ipend) rather than enabling hardware interrupts. The FIFO is faked at 16 bytes deep for now, just so the transmit IO side doesn't suck too bad (the callout frequency limits how quickly IO is flushed to the sender, rather than scheduling the callout more frequently whilst there's active TX. But I digress.) Tested: * Atheros AP121 (AR9330) reference board, booting to multi-user interactive mode.
2013-04-04 10:46:33 +00:00
struct uart_bas *bas = &sc->sc_bas;
int ipend = 0;
Implement the AR933x interrupt driven UART code. * Enable RX and host interrupts during bus probe/attach * Disable all interrupts (+ host ISR) during bus detach * Enable TX DONE interrupt only when we start transmitting; clear it when we're done. * The RX/TX FIFO depth is still conjecture on my part. I'll fix this shortly. * The TX FIFO interrupt isn't an "empty" interrupt, it's an "almost empty" interrupt. Sigh. So.. * .. in ar933x_bus_transmit(), wait for the FIFO to drain before continuing. I dislike having to wait for the FIFO to drain, alas. Tested: * Atheros AP121 board, AR9331 SoC. TODO: * RX/TX overflow, RX error, BREAK support, etc. * Figure out the true RX/TX FIFO depth.
2013-04-05 00:26:06 +00:00
uint32_t isr;
Bring over the initial, CPU-only UART support for the AR933x SoC. This implements the kernel glue needed (getc, putc, rxready). This isn't a 16550 UART, even if the datasheet overview claims so. The Linux ar933x support was used as a reference, however the uart code is a reimplementation. Attentive viewers will note that the uart code is based off of the ns8250 code and the UART bus code is a stubbed-out version of this. I'll be replacing it with non-stubbed versions soon, making this a fully featured driver. Tested: * AP121 reference board (AR933x), booting through the mountroot> prompt; then doing some basic interactive tests in ddb.
2013-03-28 19:27:06 +00:00
uart_lock(sc->sc_hwmtx);
Implement AR933x polled IO uart bus code. This implements the bus transmit/receive/sigchg/ipend methods with a polled interrupt handler (ipend) rather than enabling hardware interrupts. The FIFO is faked at 16 bytes deep for now, just so the transmit IO side doesn't suck too bad (the callout frequency limits how quickly IO is flushed to the sender, rather than scheduling the callout more frequently whilst there's active TX. But I digress.) Tested: * Atheros AP121 (AR9330) reference board, booting to multi-user interactive mode.
2013-04-04 10:46:33 +00:00
/*
Implement the AR933x interrupt driven UART code. * Enable RX and host interrupts during bus probe/attach * Disable all interrupts (+ host ISR) during bus detach * Enable TX DONE interrupt only when we start transmitting; clear it when we're done. * The RX/TX FIFO depth is still conjecture on my part. I'll fix this shortly. * The TX FIFO interrupt isn't an "empty" interrupt, it's an "almost empty" interrupt. Sigh. So.. * .. in ar933x_bus_transmit(), wait for the FIFO to drain before continuing. I dislike having to wait for the FIFO to drain, alas. Tested: * Atheros AP121 board, AR9331 SoC. TODO: * RX/TX overflow, RX error, BREAK support, etc. * Figure out the true RX/TX FIFO depth.
2013-04-05 00:26:06 +00:00
* Fetch/ACK the ISR status.
*/
isr = ar933x_getreg(bas, AR933X_UART_INT_REG);
ar933x_setreg(bas, AR933X_UART_INT_REG, isr);
uart_barrier(bas);
/*
* RX ready - notify upper layer.
Implement AR933x polled IO uart bus code. This implements the bus transmit/receive/sigchg/ipend methods with a polled interrupt handler (ipend) rather than enabling hardware interrupts. The FIFO is faked at 16 bytes deep for now, just so the transmit IO side doesn't suck too bad (the callout frequency limits how quickly IO is flushed to the sender, rather than scheduling the callout more frequently whilst there's active TX. But I digress.) Tested: * Atheros AP121 (AR9330) reference board, booting to multi-user interactive mode.
2013-04-04 10:46:33 +00:00
*/
Implement the AR933x interrupt driven UART code. * Enable RX and host interrupts during bus probe/attach * Disable all interrupts (+ host ISR) during bus detach * Enable TX DONE interrupt only when we start transmitting; clear it when we're done. * The RX/TX FIFO depth is still conjecture on my part. I'll fix this shortly. * The TX FIFO interrupt isn't an "empty" interrupt, it's an "almost empty" interrupt. Sigh. So.. * .. in ar933x_bus_transmit(), wait for the FIFO to drain before continuing. I dislike having to wait for the FIFO to drain, alas. Tested: * Atheros AP121 board, AR9331 SoC. TODO: * RX/TX overflow, RX error, BREAK support, etc. * Figure out the true RX/TX FIFO depth.
2013-04-05 00:26:06 +00:00
if (isr & AR933X_UART_INT_RX_VALID) {
Implement AR933x polled IO uart bus code. This implements the bus transmit/receive/sigchg/ipend methods with a polled interrupt handler (ipend) rather than enabling hardware interrupts. The FIFO is faked at 16 bytes deep for now, just so the transmit IO side doesn't suck too bad (the callout frequency limits how quickly IO is flushed to the sender, rather than scheduling the callout more frequently whilst there's active TX. But I digress.) Tested: * Atheros AP121 (AR9330) reference board, booting to multi-user interactive mode.
2013-04-04 10:46:33 +00:00
ipend |= SER_INT_RXREADY;
Bring over the initial, CPU-only UART support for the AR933x SoC. This implements the kernel glue needed (getc, putc, rxready). This isn't a 16550 UART, even if the datasheet overview claims so. The Linux ar933x support was used as a reference, however the uart code is a reimplementation. Attentive viewers will note that the uart code is based off of the ns8250 code and the UART bus code is a stubbed-out version of this. I'll be replacing it with non-stubbed versions soon, making this a fully featured driver. Tested: * AP121 reference board (AR933x), booting through the mountroot> prompt; then doing some basic interactive tests in ddb.
2013-03-28 19:27:06 +00:00
}
Implement the AR933x interrupt driven UART code. * Enable RX and host interrupts during bus probe/attach * Disable all interrupts (+ host ISR) during bus detach * Enable TX DONE interrupt only when we start transmitting; clear it when we're done. * The RX/TX FIFO depth is still conjecture on my part. I'll fix this shortly. * The TX FIFO interrupt isn't an "empty" interrupt, it's an "almost empty" interrupt. Sigh. So.. * .. in ar933x_bus_transmit(), wait for the FIFO to drain before continuing. I dislike having to wait for the FIFO to drain, alas. Tested: * Atheros AP121 board, AR9331 SoC. TODO: * RX/TX overflow, RX error, BREAK support, etc. * Figure out the true RX/TX FIFO depth.
2013-04-05 00:26:06 +00:00
/*
* If we get this interrupt, we should disable
* it from the interrupt mask and inform the uart
* driver appropriately.
*
* We can't keep setting SER_INT_TXIDLE or SER_INT_SIGCHG
* all the time or IO stops working. So we will always
* clear this interrupt if we get it, then we only signal
* the upper layer if we were doing active TX in the
* first place.
*
* Also, the name is misleading. This actually means
* "the FIFO is almost empty." So if we just write some
* more data to the FIFO without checking whether it can
* take said data, we'll overflow the thing.
*
* Unfortunately the FreeBSD uart device has no concept of
* partial UART writes - it expects that the whole buffer
* is written to the hardware. Thus for now, ar933x_bus_transmit()
* will wait for the FIFO to finish draining before it pushes
* more frames into it.
*/
if (isr & AR933X_UART_INT_TX_EMPTY) {
/*
* Update u_ier to disable TX notifications; update hardware
*/
u->u_ier &= ~AR933X_UART_INT_TX_EMPTY;
ar933x_setreg(bas, AR933X_UART_INT_EN_REG, u->u_ier);
uart_barrier(bas);
}
Implement AR933x polled IO uart bus code. This implements the bus transmit/receive/sigchg/ipend methods with a polled interrupt handler (ipend) rather than enabling hardware interrupts. The FIFO is faked at 16 bytes deep for now, just so the transmit IO side doesn't suck too bad (the callout frequency limits how quickly IO is flushed to the sender, rather than scheduling the callout more frequently whilst there's active TX. But I digress.) Tested: * Atheros AP121 (AR9330) reference board, booting to multi-user interactive mode.
2013-04-04 10:46:33 +00:00
/*
* Only signal TX idle if we're not busy transmitting.
*/
if (sc->sc_txbusy) {
Implement the AR933x interrupt driven UART code. * Enable RX and host interrupts during bus probe/attach * Disable all interrupts (+ host ISR) during bus detach * Enable TX DONE interrupt only when we start transmitting; clear it when we're done. * The RX/TX FIFO depth is still conjecture on my part. I'll fix this shortly. * The TX FIFO interrupt isn't an "empty" interrupt, it's an "almost empty" interrupt. Sigh. So.. * .. in ar933x_bus_transmit(), wait for the FIFO to drain before continuing. I dislike having to wait for the FIFO to drain, alas. Tested: * Atheros AP121 board, AR9331 SoC. TODO: * RX/TX overflow, RX error, BREAK support, etc. * Figure out the true RX/TX FIFO depth.
2013-04-05 00:26:06 +00:00
if (isr & AR933X_UART_INT_TX_EMPTY) {
Bring over the initial, CPU-only UART support for the AR933x SoC. This implements the kernel glue needed (getc, putc, rxready). This isn't a 16550 UART, even if the datasheet overview claims so. The Linux ar933x support was used as a reference, however the uart code is a reimplementation. Attentive viewers will note that the uart code is based off of the ns8250 code and the UART bus code is a stubbed-out version of this. I'll be replacing it with non-stubbed versions soon, making this a fully featured driver. Tested: * AP121 reference board (AR933x), booting through the mountroot> prompt; then doing some basic interactive tests in ddb.
2013-03-28 19:27:06 +00:00
ipend |= SER_INT_TXIDLE;
Implement AR933x polled IO uart bus code. This implements the bus transmit/receive/sigchg/ipend methods with a polled interrupt handler (ipend) rather than enabling hardware interrupts. The FIFO is faked at 16 bytes deep for now, just so the transmit IO side doesn't suck too bad (the callout frequency limits how quickly IO is flushed to the sender, rather than scheduling the callout more frequently whilst there's active TX. But I digress.) Tested: * Atheros AP121 (AR9330) reference board, booting to multi-user interactive mode.
2013-04-04 10:46:33 +00:00
} else {
Bring over the initial, CPU-only UART support for the AR933x SoC. This implements the kernel glue needed (getc, putc, rxready). This isn't a 16550 UART, even if the datasheet overview claims so. The Linux ar933x support was used as a reference, however the uart code is a reimplementation. Attentive viewers will note that the uart code is based off of the ns8250 code and the UART bus code is a stubbed-out version of this. I'll be replacing it with non-stubbed versions soon, making this a fully featured driver. Tested: * AP121 reference board (AR933x), booting through the mountroot> prompt; then doing some basic interactive tests in ddb.
2013-03-28 19:27:06 +00:00
ipend |= SER_INT_SIGCHG;
Implement AR933x polled IO uart bus code. This implements the bus transmit/receive/sigchg/ipend methods with a polled interrupt handler (ipend) rather than enabling hardware interrupts. The FIFO is faked at 16 bytes deep for now, just so the transmit IO side doesn't suck too bad (the callout frequency limits how quickly IO is flushed to the sender, rather than scheduling the callout more frequently whilst there's active TX. But I digress.) Tested: * Atheros AP121 (AR9330) reference board, booting to multi-user interactive mode.
2013-04-04 10:46:33 +00:00
}
Bring over the initial, CPU-only UART support for the AR933x SoC. This implements the kernel glue needed (getc, putc, rxready). This isn't a 16550 UART, even if the datasheet overview claims so. The Linux ar933x support was used as a reference, however the uart code is a reimplementation. Attentive viewers will note that the uart code is based off of the ns8250 code and the UART bus code is a stubbed-out version of this. I'll be replacing it with non-stubbed versions soon, making this a fully featured driver. Tested: * AP121 reference board (AR933x), booting through the mountroot> prompt; then doing some basic interactive tests in ddb.
2013-03-28 19:27:06 +00:00
}
Implement AR933x polled IO uart bus code. This implements the bus transmit/receive/sigchg/ipend methods with a polled interrupt handler (ipend) rather than enabling hardware interrupts. The FIFO is faked at 16 bytes deep for now, just so the transmit IO side doesn't suck too bad (the callout frequency limits how quickly IO is flushed to the sender, rather than scheduling the callout more frequently whilst there's active TX. But I digress.) Tested: * Atheros AP121 (AR9330) reference board, booting to multi-user interactive mode.
2013-04-04 10:46:33 +00:00
Bring over the initial, CPU-only UART support for the AR933x SoC. This implements the kernel glue needed (getc, putc, rxready). This isn't a 16550 UART, even if the datasheet overview claims so. The Linux ar933x support was used as a reference, however the uart code is a reimplementation. Attentive viewers will note that the uart code is based off of the ns8250 code and the UART bus code is a stubbed-out version of this. I'll be replacing it with non-stubbed versions soon, making this a fully featured driver. Tested: * AP121 reference board (AR933x), booting through the mountroot> prompt; then doing some basic interactive tests in ddb.
2013-03-28 19:27:06 +00:00
uart_unlock(sc->sc_hwmtx);
return (ipend);
}
static int
ar933x_bus_param(struct uart_softc *sc, int baudrate, int databits,
int stopbits, int parity)
{
struct uart_bas *bas;
int error;
bas = &sc->sc_bas;
uart_lock(sc->sc_hwmtx);
error = ar933x_param(bas, baudrate, databits, stopbits, parity);
uart_unlock(sc->sc_hwmtx);
return (error);
}
static int
ar933x_bus_probe(struct uart_softc *sc)
{
struct uart_bas *bas;
Implement AR933x polled IO uart bus code. This implements the bus transmit/receive/sigchg/ipend methods with a polled interrupt handler (ipend) rather than enabling hardware interrupts. The FIFO is faked at 16 bytes deep for now, just so the transmit IO side doesn't suck too bad (the callout frequency limits how quickly IO is flushed to the sender, rather than scheduling the callout more frequently whilst there's active TX. But I digress.) Tested: * Atheros AP121 (AR9330) reference board, booting to multi-user interactive mode.
2013-04-04 10:46:33 +00:00
int error;
Bring over the initial, CPU-only UART support for the AR933x SoC. This implements the kernel glue needed (getc, putc, rxready). This isn't a 16550 UART, even if the datasheet overview claims so. The Linux ar933x support was used as a reference, however the uart code is a reimplementation. Attentive viewers will note that the uart code is based off of the ns8250 code and the UART bus code is a stubbed-out version of this. I'll be replacing it with non-stubbed versions soon, making this a fully featured driver. Tested: * AP121 reference board (AR933x), booting through the mountroot> prompt; then doing some basic interactive tests in ddb.
2013-03-28 19:27:06 +00:00
bas = &sc->sc_bas;
error = ar933x_probe(bas);
if (error)
return (error);
/* Reset FIFOs. */
Implement AR933x polled IO uart bus code. This implements the bus transmit/receive/sigchg/ipend methods with a polled interrupt handler (ipend) rather than enabling hardware interrupts. The FIFO is faked at 16 bytes deep for now, just so the transmit IO side doesn't suck too bad (the callout frequency limits how quickly IO is flushed to the sender, rather than scheduling the callout more frequently whilst there's active TX. But I digress.) Tested: * Atheros AP121 (AR9330) reference board, booting to multi-user interactive mode.
2013-04-04 10:46:33 +00:00
ar933x_drain(bas, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER);
Bring over the initial, CPU-only UART support for the AR933x SoC. This implements the kernel glue needed (getc, putc, rxready). This isn't a 16550 UART, even if the datasheet overview claims so. The Linux ar933x support was used as a reference, however the uart code is a reimplementation. Attentive viewers will note that the uart code is based off of the ns8250 code and the UART bus code is a stubbed-out version of this. I'll be replacing it with non-stubbed versions soon, making this a fully featured driver. Tested: * AP121 reference board (AR933x), booting through the mountroot> prompt; then doing some basic interactive tests in ddb.
2013-03-28 19:27:06 +00:00
Implement AR933x polled IO uart bus code. This implements the bus transmit/receive/sigchg/ipend methods with a polled interrupt handler (ipend) rather than enabling hardware interrupts. The FIFO is faked at 16 bytes deep for now, just so the transmit IO side doesn't suck too bad (the callout frequency limits how quickly IO is flushed to the sender, rather than scheduling the callout more frequently whilst there's active TX. But I digress.) Tested: * Atheros AP121 (AR9330) reference board, booting to multi-user interactive mode.
2013-04-04 10:46:33 +00:00
/* XXX TODO: actually find out what the FIFO depth is! */
sc->sc_rxfifosz = 16;
Bring over the initial, CPU-only UART support for the AR933x SoC. This implements the kernel glue needed (getc, putc, rxready). This isn't a 16550 UART, even if the datasheet overview claims so. The Linux ar933x support was used as a reference, however the uart code is a reimplementation. Attentive viewers will note that the uart code is based off of the ns8250 code and the UART bus code is a stubbed-out version of this. I'll be replacing it with non-stubbed versions soon, making this a fully featured driver. Tested: * AP121 reference board (AR933x), booting through the mountroot> prompt; then doing some basic interactive tests in ddb.
2013-03-28 19:27:06 +00:00
sc->sc_txfifosz = 16;
return (0);
}
static int
ar933x_bus_receive(struct uart_softc *sc)
{
Implement AR933x polled IO uart bus code. This implements the bus transmit/receive/sigchg/ipend methods with a polled interrupt handler (ipend) rather than enabling hardware interrupts. The FIFO is faked at 16 bytes deep for now, just so the transmit IO side doesn't suck too bad (the callout frequency limits how quickly IO is flushed to the sender, rather than scheduling the callout more frequently whilst there's active TX. But I digress.) Tested: * Atheros AP121 (AR9330) reference board, booting to multi-user interactive mode.
2013-04-04 10:46:33 +00:00
struct uart_bas *bas = &sc->sc_bas;
Bring over the initial, CPU-only UART support for the AR933x SoC. This implements the kernel glue needed (getc, putc, rxready). This isn't a 16550 UART, even if the datasheet overview claims so. The Linux ar933x support was used as a reference, however the uart code is a reimplementation. Attentive viewers will note that the uart code is based off of the ns8250 code and the UART bus code is a stubbed-out version of this. I'll be replacing it with non-stubbed versions soon, making this a fully featured driver. Tested: * AP121 reference board (AR933x), booting through the mountroot> prompt; then doing some basic interactive tests in ddb.
2013-03-28 19:27:06 +00:00
int xc;
uart_lock(sc->sc_hwmtx);
Implement AR933x polled IO uart bus code. This implements the bus transmit/receive/sigchg/ipend methods with a polled interrupt handler (ipend) rather than enabling hardware interrupts. The FIFO is faked at 16 bytes deep for now, just so the transmit IO side doesn't suck too bad (the callout frequency limits how quickly IO is flushed to the sender, rather than scheduling the callout more frequently whilst there's active TX. But I digress.) Tested: * Atheros AP121 (AR9330) reference board, booting to multi-user interactive mode.
2013-04-04 10:46:33 +00:00
/* Loop over until we are full, or no data is available */
while (ar933x_rxready(bas)) {
Bring over the initial, CPU-only UART support for the AR933x SoC. This implements the kernel glue needed (getc, putc, rxready). This isn't a 16550 UART, even if the datasheet overview claims so. The Linux ar933x support was used as a reference, however the uart code is a reimplementation. Attentive viewers will note that the uart code is based off of the ns8250 code and the UART bus code is a stubbed-out version of this. I'll be replacing it with non-stubbed versions soon, making this a fully featured driver. Tested: * AP121 reference board (AR933x), booting through the mountroot> prompt; then doing some basic interactive tests in ddb.
2013-03-28 19:27:06 +00:00
if (uart_rx_full(sc)) {
sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN;
break;
}
Implement AR933x polled IO uart bus code. This implements the bus transmit/receive/sigchg/ipend methods with a polled interrupt handler (ipend) rather than enabling hardware interrupts. The FIFO is faked at 16 bytes deep for now, just so the transmit IO side doesn't suck too bad (the callout frequency limits how quickly IO is flushed to the sender, rather than scheduling the callout more frequently whilst there's active TX. But I digress.) Tested: * Atheros AP121 (AR9330) reference board, booting to multi-user interactive mode.
2013-04-04 10:46:33 +00:00
/* Read the top of the RX FIFO */
xc = ar933x_getreg(bas, AR933X_UART_DATA_REG) & 0xff;
/* Remove that entry from said RX FIFO */
ar933x_setreg(bas, AR933X_UART_DATA_REG,
AR933X_UART_DATA_RX_CSR);
Implement the AR933x interrupt driven UART code. * Enable RX and host interrupts during bus probe/attach * Disable all interrupts (+ host ISR) during bus detach * Enable TX DONE interrupt only when we start transmitting; clear it when we're done. * The RX/TX FIFO depth is still conjecture on my part. I'll fix this shortly. * The TX FIFO interrupt isn't an "empty" interrupt, it's an "almost empty" interrupt. Sigh. So.. * .. in ar933x_bus_transmit(), wait for the FIFO to drain before continuing. I dislike having to wait for the FIFO to drain, alas. Tested: * Atheros AP121 board, AR9331 SoC. TODO: * RX/TX overflow, RX error, BREAK support, etc. * Figure out the true RX/TX FIFO depth.
2013-04-05 00:26:06 +00:00
uart_barrier(bas);
Implement AR933x polled IO uart bus code. This implements the bus transmit/receive/sigchg/ipend methods with a polled interrupt handler (ipend) rather than enabling hardware interrupts. The FIFO is faked at 16 bytes deep for now, just so the transmit IO side doesn't suck too bad (the callout frequency limits how quickly IO is flushed to the sender, rather than scheduling the callout more frequently whilst there's active TX. But I digress.) Tested: * Atheros AP121 (AR9330) reference board, booting to multi-user interactive mode.
2013-04-04 10:46:33 +00:00
/* XXX frame, parity error */
Bring over the initial, CPU-only UART support for the AR933x SoC. This implements the kernel glue needed (getc, putc, rxready). This isn't a 16550 UART, even if the datasheet overview claims so. The Linux ar933x support was used as a reference, however the uart code is a reimplementation. Attentive viewers will note that the uart code is based off of the ns8250 code and the UART bus code is a stubbed-out version of this. I'll be replacing it with non-stubbed versions soon, making this a fully featured driver. Tested: * AP121 reference board (AR933x), booting through the mountroot> prompt; then doing some basic interactive tests in ddb.
2013-03-28 19:27:06 +00:00
uart_rx_put(sc, xc);
}
Implement AR933x polled IO uart bus code. This implements the bus transmit/receive/sigchg/ipend methods with a polled interrupt handler (ipend) rather than enabling hardware interrupts. The FIFO is faked at 16 bytes deep for now, just so the transmit IO side doesn't suck too bad (the callout frequency limits how quickly IO is flushed to the sender, rather than scheduling the callout more frequently whilst there's active TX. But I digress.) Tested: * Atheros AP121 (AR9330) reference board, booting to multi-user interactive mode.
2013-04-04 10:46:33 +00:00
/*
* XXX TODO: Discard everything left in the Rx FIFO?
* XXX only if we've hit an overrun condition?
*/
Bring over the initial, CPU-only UART support for the AR933x SoC. This implements the kernel glue needed (getc, putc, rxready). This isn't a 16550 UART, even if the datasheet overview claims so. The Linux ar933x support was used as a reference, however the uart code is a reimplementation. Attentive viewers will note that the uart code is based off of the ns8250 code and the UART bus code is a stubbed-out version of this. I'll be replacing it with non-stubbed versions soon, making this a fully featured driver. Tested: * AP121 reference board (AR933x), booting through the mountroot> prompt; then doing some basic interactive tests in ddb.
2013-03-28 19:27:06 +00:00
uart_unlock(sc->sc_hwmtx);
Implement AR933x polled IO uart bus code. This implements the bus transmit/receive/sigchg/ipend methods with a polled interrupt handler (ipend) rather than enabling hardware interrupts. The FIFO is faked at 16 bytes deep for now, just so the transmit IO side doesn't suck too bad (the callout frequency limits how quickly IO is flushed to the sender, rather than scheduling the callout more frequently whilst there's active TX. But I digress.) Tested: * Atheros AP121 (AR9330) reference board, booting to multi-user interactive mode.
2013-04-04 10:46:33 +00:00
Bring over the initial, CPU-only UART support for the AR933x SoC. This implements the kernel glue needed (getc, putc, rxready). This isn't a 16550 UART, even if the datasheet overview claims so. The Linux ar933x support was used as a reference, however the uart code is a reimplementation. Attentive viewers will note that the uart code is based off of the ns8250 code and the UART bus code is a stubbed-out version of this. I'll be replacing it with non-stubbed versions soon, making this a fully featured driver. Tested: * AP121 reference board (AR933x), booting through the mountroot> prompt; then doing some basic interactive tests in ddb.
2013-03-28 19:27:06 +00:00
return (0);
}
static int
ar933x_bus_setsig(struct uart_softc *sc, int sig)
{
#if 0
struct ar933x_softc *ns8250 = (struct ar933x_softc*)sc;
struct uart_bas *bas;
uint32_t new, old;
bas = &sc->sc_bas;
do {
old = sc->sc_hwsig;
new = old;
if (sig & SER_DDTR) {
SIGCHG(sig & SER_DTR, new, SER_DTR,
SER_DDTR);
}
if (sig & SER_DRTS) {
SIGCHG(sig & SER_RTS, new, SER_RTS,
SER_DRTS);
}
} while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
uart_lock(sc->sc_hwmtx);
ns8250->mcr &= ~(MCR_DTR|MCR_RTS);
if (new & SER_DTR)
ns8250->mcr |= MCR_DTR;
if (new & SER_RTS)
ns8250->mcr |= MCR_RTS;
uart_setreg(bas, REG_MCR, ns8250->mcr);
uart_barrier(bas);
uart_unlock(sc->sc_hwmtx);
#endif
return (0);
}
Implement the AR933x interrupt driven UART code. * Enable RX and host interrupts during bus probe/attach * Disable all interrupts (+ host ISR) during bus detach * Enable TX DONE interrupt only when we start transmitting; clear it when we're done. * The RX/TX FIFO depth is still conjecture on my part. I'll fix this shortly. * The TX FIFO interrupt isn't an "empty" interrupt, it's an "almost empty" interrupt. Sigh. So.. * .. in ar933x_bus_transmit(), wait for the FIFO to drain before continuing. I dislike having to wait for the FIFO to drain, alas. Tested: * Atheros AP121 board, AR9331 SoC. TODO: * RX/TX overflow, RX error, BREAK support, etc. * Figure out the true RX/TX FIFO depth.
2013-04-05 00:26:06 +00:00
/*
* Write the current transmit buffer to the TX FIFO.
*
* Unfortunately the FreeBSD uart device has no concept of
* partial UART writes - it expects that the whole buffer
* is written to the hardware. Thus for now, this will wait for
* the FIFO to finish draining before it pushes more frames into it.
*
* If non-blocking operation is truely needed here, either
* the FreeBSD uart device will need to handle partial writes
* in xxx_bus_transmit(), or we'll need to do TX FIFO buffering
* of our own here.
*/
Bring over the initial, CPU-only UART support for the AR933x SoC. This implements the kernel glue needed (getc, putc, rxready). This isn't a 16550 UART, even if the datasheet overview claims so. The Linux ar933x support was used as a reference, however the uart code is a reimplementation. Attentive viewers will note that the uart code is based off of the ns8250 code and the UART bus code is a stubbed-out version of this. I'll be replacing it with non-stubbed versions soon, making this a fully featured driver. Tested: * AP121 reference board (AR933x), booting through the mountroot> prompt; then doing some basic interactive tests in ddb.
2013-03-28 19:27:06 +00:00
static int
ar933x_bus_transmit(struct uart_softc *sc)
{
Implement AR933x polled IO uart bus code. This implements the bus transmit/receive/sigchg/ipend methods with a polled interrupt handler (ipend) rather than enabling hardware interrupts. The FIFO is faked at 16 bytes deep for now, just so the transmit IO side doesn't suck too bad (the callout frequency limits how quickly IO is flushed to the sender, rather than scheduling the callout more frequently whilst there's active TX. But I digress.) Tested: * Atheros AP121 (AR9330) reference board, booting to multi-user interactive mode.
2013-04-04 10:46:33 +00:00
struct uart_bas *bas = &sc->sc_bas;
Implement the AR933x interrupt driven UART code. * Enable RX and host interrupts during bus probe/attach * Disable all interrupts (+ host ISR) during bus detach * Enable TX DONE interrupt only when we start transmitting; clear it when we're done. * The RX/TX FIFO depth is still conjecture on my part. I'll fix this shortly. * The TX FIFO interrupt isn't an "empty" interrupt, it's an "almost empty" interrupt. Sigh. So.. * .. in ar933x_bus_transmit(), wait for the FIFO to drain before continuing. I dislike having to wait for the FIFO to drain, alas. Tested: * Atheros AP121 board, AR9331 SoC. TODO: * RX/TX overflow, RX error, BREAK support, etc. * Figure out the true RX/TX FIFO depth.
2013-04-05 00:26:06 +00:00
struct ar933x_softc *u = (struct ar933x_softc *)sc;
Bring over the initial, CPU-only UART support for the AR933x SoC. This implements the kernel glue needed (getc, putc, rxready). This isn't a 16550 UART, even if the datasheet overview claims so. The Linux ar933x support was used as a reference, however the uart code is a reimplementation. Attentive viewers will note that the uart code is based off of the ns8250 code and the UART bus code is a stubbed-out version of this. I'll be replacing it with non-stubbed versions soon, making this a fully featured driver. Tested: * AP121 reference board (AR933x), booting through the mountroot> prompt; then doing some basic interactive tests in ddb.
2013-03-28 19:27:06 +00:00
int i;
uart_lock(sc->sc_hwmtx);
Implement AR933x polled IO uart bus code. This implements the bus transmit/receive/sigchg/ipend methods with a polled interrupt handler (ipend) rather than enabling hardware interrupts. The FIFO is faked at 16 bytes deep for now, just so the transmit IO side doesn't suck too bad (the callout frequency limits how quickly IO is flushed to the sender, rather than scheduling the callout more frequently whilst there's active TX. But I digress.) Tested: * Atheros AP121 (AR9330) reference board, booting to multi-user interactive mode.
2013-04-04 10:46:33 +00:00
Implement the AR933x interrupt driven UART code. * Enable RX and host interrupts during bus probe/attach * Disable all interrupts (+ host ISR) during bus detach * Enable TX DONE interrupt only when we start transmitting; clear it when we're done. * The RX/TX FIFO depth is still conjecture on my part. I'll fix this shortly. * The TX FIFO interrupt isn't an "empty" interrupt, it's an "almost empty" interrupt. Sigh. So.. * .. in ar933x_bus_transmit(), wait for the FIFO to drain before continuing. I dislike having to wait for the FIFO to drain, alas. Tested: * Atheros AP121 board, AR9331 SoC. TODO: * RX/TX overflow, RX error, BREAK support, etc. * Figure out the true RX/TX FIFO depth.
2013-04-05 00:26:06 +00:00
/* Wait for the FIFO to be clear - see above */
while (ar933x_getreg(bas, AR933X_UART_CS_REG) &
AR933X_UART_CS_TX_BUSY)
;
Implement AR933x polled IO uart bus code. This implements the bus transmit/receive/sigchg/ipend methods with a polled interrupt handler (ipend) rather than enabling hardware interrupts. The FIFO is faked at 16 bytes deep for now, just so the transmit IO side doesn't suck too bad (the callout frequency limits how quickly IO is flushed to the sender, rather than scheduling the callout more frequently whilst there's active TX. But I digress.) Tested: * Atheros AP121 (AR9330) reference board, booting to multi-user interactive mode.
2013-04-04 10:46:33 +00:00
Implement the AR933x interrupt driven UART code. * Enable RX and host interrupts during bus probe/attach * Disable all interrupts (+ host ISR) during bus detach * Enable TX DONE interrupt only when we start transmitting; clear it when we're done. * The RX/TX FIFO depth is still conjecture on my part. I'll fix this shortly. * The TX FIFO interrupt isn't an "empty" interrupt, it's an "almost empty" interrupt. Sigh. So.. * .. in ar933x_bus_transmit(), wait for the FIFO to drain before continuing. I dislike having to wait for the FIFO to drain, alas. Tested: * Atheros AP121 board, AR9331 SoC. TODO: * RX/TX overflow, RX error, BREAK support, etc. * Figure out the true RX/TX FIFO depth.
2013-04-05 00:26:06 +00:00
/*
* Write some data!
*/
Bring over the initial, CPU-only UART support for the AR933x SoC. This implements the kernel glue needed (getc, putc, rxready). This isn't a 16550 UART, even if the datasheet overview claims so. The Linux ar933x support was used as a reference, however the uart code is a reimplementation. Attentive viewers will note that the uart code is based off of the ns8250 code and the UART bus code is a stubbed-out version of this. I'll be replacing it with non-stubbed versions soon, making this a fully featured driver. Tested: * AP121 reference board (AR933x), booting through the mountroot> prompt; then doing some basic interactive tests in ddb.
2013-03-28 19:27:06 +00:00
for (i = 0; i < sc->sc_txdatasz; i++) {
Implement AR933x polled IO uart bus code. This implements the bus transmit/receive/sigchg/ipend methods with a polled interrupt handler (ipend) rather than enabling hardware interrupts. The FIFO is faked at 16 bytes deep for now, just so the transmit IO side doesn't suck too bad (the callout frequency limits how quickly IO is flushed to the sender, rather than scheduling the callout more frequently whilst there's active TX. But I digress.) Tested: * Atheros AP121 (AR9330) reference board, booting to multi-user interactive mode.
2013-04-04 10:46:33 +00:00
/* Write the TX data */
ar933x_setreg(bas, AR933X_UART_DATA_REG,
(sc->sc_txbuf[i] & 0xff) | AR933X_UART_DATA_TX_CSR);
Implement the AR933x interrupt driven UART code. * Enable RX and host interrupts during bus probe/attach * Disable all interrupts (+ host ISR) during bus detach * Enable TX DONE interrupt only when we start transmitting; clear it when we're done. * The RX/TX FIFO depth is still conjecture on my part. I'll fix this shortly. * The TX FIFO interrupt isn't an "empty" interrupt, it's an "almost empty" interrupt. Sigh. So.. * .. in ar933x_bus_transmit(), wait for the FIFO to drain before continuing. I dislike having to wait for the FIFO to drain, alas. Tested: * Atheros AP121 board, AR9331 SoC. TODO: * RX/TX overflow, RX error, BREAK support, etc. * Figure out the true RX/TX FIFO depth.
2013-04-05 00:26:06 +00:00
uart_barrier(bas);
Bring over the initial, CPU-only UART support for the AR933x SoC. This implements the kernel glue needed (getc, putc, rxready). This isn't a 16550 UART, even if the datasheet overview claims so. The Linux ar933x support was used as a reference, however the uart code is a reimplementation. Attentive viewers will note that the uart code is based off of the ns8250 code and the UART bus code is a stubbed-out version of this. I'll be replacing it with non-stubbed versions soon, making this a fully featured driver. Tested: * AP121 reference board (AR933x), booting through the mountroot> prompt; then doing some basic interactive tests in ddb.
2013-03-28 19:27:06 +00:00
}
Implement AR933x polled IO uart bus code. This implements the bus transmit/receive/sigchg/ipend methods with a polled interrupt handler (ipend) rather than enabling hardware interrupts. The FIFO is faked at 16 bytes deep for now, just so the transmit IO side doesn't suck too bad (the callout frequency limits how quickly IO is flushed to the sender, rather than scheduling the callout more frequently whilst there's active TX. But I digress.) Tested: * Atheros AP121 (AR9330) reference board, booting to multi-user interactive mode.
2013-04-04 10:46:33 +00:00
Implement the AR933x interrupt driven UART code. * Enable RX and host interrupts during bus probe/attach * Disable all interrupts (+ host ISR) during bus detach * Enable TX DONE interrupt only when we start transmitting; clear it when we're done. * The RX/TX FIFO depth is still conjecture on my part. I'll fix this shortly. * The TX FIFO interrupt isn't an "empty" interrupt, it's an "almost empty" interrupt. Sigh. So.. * .. in ar933x_bus_transmit(), wait for the FIFO to drain before continuing. I dislike having to wait for the FIFO to drain, alas. Tested: * Atheros AP121 board, AR9331 SoC. TODO: * RX/TX overflow, RX error, BREAK support, etc. * Figure out the true RX/TX FIFO depth.
2013-04-05 00:26:06 +00:00
/*
* Now that we're transmitting, get interrupt notification
* when the FIFO is (almost) empty - see above.
*/
u->u_ier |= AR933X_UART_INT_TX_EMPTY;
ar933x_setreg(bas, AR933X_UART_INT_EN_REG, u->u_ier);
uart_barrier(bas);
Implement AR933x polled IO uart bus code. This implements the bus transmit/receive/sigchg/ipend methods with a polled interrupt handler (ipend) rather than enabling hardware interrupts. The FIFO is faked at 16 bytes deep for now, just so the transmit IO side doesn't suck too bad (the callout frequency limits how quickly IO is flushed to the sender, rather than scheduling the callout more frequently whilst there's active TX. But I digress.) Tested: * Atheros AP121 (AR9330) reference board, booting to multi-user interactive mode.
2013-04-04 10:46:33 +00:00
/*
* Inform the upper layer that we are presently transmitting
* data to the hardware; this will be cleared when the
* TXIDLE interrupt occurs.
*/
Bring over the initial, CPU-only UART support for the AR933x SoC. This implements the kernel glue needed (getc, putc, rxready). This isn't a 16550 UART, even if the datasheet overview claims so. The Linux ar933x support was used as a reference, however the uart code is a reimplementation. Attentive viewers will note that the uart code is based off of the ns8250 code and the UART bus code is a stubbed-out version of this. I'll be replacing it with non-stubbed versions soon, making this a fully featured driver. Tested: * AP121 reference board (AR933x), booting through the mountroot> prompt; then doing some basic interactive tests in ddb.
2013-03-28 19:27:06 +00:00
sc->sc_txbusy = 1;
uart_unlock(sc->sc_hwmtx);
Implement AR933x polled IO uart bus code. This implements the bus transmit/receive/sigchg/ipend methods with a polled interrupt handler (ipend) rather than enabling hardware interrupts. The FIFO is faked at 16 bytes deep for now, just so the transmit IO side doesn't suck too bad (the callout frequency limits how quickly IO is flushed to the sender, rather than scheduling the callout more frequently whilst there's active TX. But I digress.) Tested: * Atheros AP121 (AR9330) reference board, booting to multi-user interactive mode.
2013-04-04 10:46:33 +00:00
Bring over the initial, CPU-only UART support for the AR933x SoC. This implements the kernel glue needed (getc, putc, rxready). This isn't a 16550 UART, even if the datasheet overview claims so. The Linux ar933x support was used as a reference, however the uart code is a reimplementation. Attentive viewers will note that the uart code is based off of the ns8250 code and the UART bus code is a stubbed-out version of this. I'll be replacing it with non-stubbed versions soon, making this a fully featured driver. Tested: * AP121 reference board (AR933x), booting through the mountroot> prompt; then doing some basic interactive tests in ddb.
2013-03-28 19:27:06 +00:00
return (0);
}
Reference in New Issue Copy Permalink