freebsd-nq/sys/sparc64/include/bus.h

855 lines
22 KiB
C
Raw Normal View History

/*-
* Copyright (c) 1996, 1997, 1998, 2001 The NetBSD Foundation, Inc.
* All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
* by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
* NASA Ames Research Center.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*
* Copyright (c) 1997-1999 Eduardo E. Horvath. All rights reserved.
* Copyright (c) 1996 Charles M. Hannum. All rights reserved.
* Copyright (c) 1996 Christopher G. Demetriou. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Christopher G. Demetriou
* for the NetBSD Project.
* 4. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* from: NetBSD: bus.h,v 1.58 2008/04/28 20:23:36 martin Exp
* and
* from: FreeBSD: src/sys/alpha/include/bus.h,v 1.9 2001/01/09
*
* $FreeBSD$
*/
#ifndef _MACHINE_BUS_H_
#define _MACHINE_BUS_H_
#ifdef BUS_SPACE_DEBUG
#include <sys/ktr.h>
#endif
#include <machine/_bus.h>
#include <machine/cpufunc.h>
/*
* Nexus and SBus spaces are non-cached and big endian
* (except for RAM and PROM)
*
* PCI spaces are non-cached and little endian
*/
#define NEXUS_BUS_SPACE 0
#define SBUS_BUS_SPACE 1
#define PCI_CONFIG_BUS_SPACE 2
#define PCI_IO_BUS_SPACE 3
#define PCI_MEMORY_BUS_SPACE 4
#define LAST_BUS_SPACE 5
extern const int bus_type_asi[];
extern const int bus_stream_asi[];
#define __BUS_SPACE_HAS_STREAM_METHODS 1
#define BUS_SPACE_MAXSIZE_24BIT 0xFFFFFF
#define BUS_SPACE_MAXSIZE_32BIT 0xFFFFFFFF
#define BUS_SPACE_MAXSIZE 0xFFFFFFFFFFFFFFFF
#define BUS_SPACE_MAXADDR_24BIT 0xFFFFFF
#define BUS_SPACE_MAXADDR_32BIT 0xFFFFFFFF
#define BUS_SPACE_MAXADDR 0xFFFFFFFF
#define BUS_SPACE_UNRESTRICTED (~0)
struct bus_space_tag {
void *bst_cookie;
bus_space_tag_t bst_parent;
int bst_type;
void (*bst_bus_barrier)(bus_space_tag_t, bus_space_handle_t,
bus_size_t, bus_size_t, int);
};
/*
* Bus space function prototypes.
*/
static void bus_space_barrier(bus_space_tag_t, bus_space_handle_t, bus_size_t,
bus_size_t, int);
2003-01-08 04:29:00 +00:00
static int bus_space_subregion(bus_space_tag_t, bus_space_handle_t,
bus_size_t, bus_size_t, bus_space_handle_t *);
/*
* Map a region of device bus space into CPU virtual address space.
*/
Make sparc64 compatible with NEW_PCIB and enable it: - Implement bus_adjust_resource() methods as far as necessary and in non-PCI bridge drivers as far as feasible without rototilling them. - As NEW_PCIB does a layering violation by activating resources at layers above pci(4) without previously bubbling up their allocation there, move the assignment of bus tags and handles from the bus_alloc_resource() to the bus_activate_resource() methods like at least the other NEW_PCIB enabled architectures do. This is somewhat unfortunate as previously sparc64 (ab)used resource activation to indicate whether SYS_RES_MEMORY resources should be mapped into KVA, which is only necessary if their going to be accessed via the pointer returned from rman_get_virtual() but not for bus_space(9) as the later always uses physical access on sparc64. Besides wasting KVA if we always map in SYS_RES_MEMORY resources, a driver also may deliberately not map them in if the firmware already has done so, possibly in a special way. So in order to still allow a driver to decide whether a SYS_RES_MEMORY resource should be mapped into KVA we let it indicate that by calling bus_space_map(9) with BUS_SPACE_MAP_LINEAR as actually documented in the bus_space(9) page. This is implemented by allocating a separate bus tag per SYS_RES_MEMORY resource and passing the resource via the previously unused bus tag cookie so we later on can call rman_set_virtual() in sparc64_bus_mem_map(). As a side effect this now also allows to actually indicate that a SYS_RES_MEMORY resource should be mapped in as cacheable and/or read-only via BUS_SPACE_MAP_CACHEABLE and BUS_SPACE_MAP_READONLY respectively. - Do some minor cleanup like taking advantage of rman_init_from_resource(), factor out the common part of bus tag allocation into a newly added sparc64_alloc_bus_tag(), hook up some missing newbus methods and replace some homegrown versions with the generic counterparts etc. - While at it, let apb_attach() (which can't use the generic NEW_PCIB code as APB bridges just don't have the base and limit registers implemented) regarding the config space registers cached in pcib_softc and the SYSCTL reporting nodes set up.
2011-10-02 23:22:38 +00:00
int bus_space_map(bus_space_tag_t tag, bus_addr_t address, bus_size_t size,
int flags, bus_space_handle_t *handlep);
/*
* Unmap a region of device bus space.
*/
Make sparc64 compatible with NEW_PCIB and enable it: - Implement bus_adjust_resource() methods as far as necessary and in non-PCI bridge drivers as far as feasible without rototilling them. - As NEW_PCIB does a layering violation by activating resources at layers above pci(4) without previously bubbling up their allocation there, move the assignment of bus tags and handles from the bus_alloc_resource() to the bus_activate_resource() methods like at least the other NEW_PCIB enabled architectures do. This is somewhat unfortunate as previously sparc64 (ab)used resource activation to indicate whether SYS_RES_MEMORY resources should be mapped into KVA, which is only necessary if their going to be accessed via the pointer returned from rman_get_virtual() but not for bus_space(9) as the later always uses physical access on sparc64. Besides wasting KVA if we always map in SYS_RES_MEMORY resources, a driver also may deliberately not map them in if the firmware already has done so, possibly in a special way. So in order to still allow a driver to decide whether a SYS_RES_MEMORY resource should be mapped into KVA we let it indicate that by calling bus_space_map(9) with BUS_SPACE_MAP_LINEAR as actually documented in the bus_space(9) page. This is implemented by allocating a separate bus tag per SYS_RES_MEMORY resource and passing the resource via the previously unused bus tag cookie so we later on can call rman_set_virtual() in sparc64_bus_mem_map(). As a side effect this now also allows to actually indicate that a SYS_RES_MEMORY resource should be mapped in as cacheable and/or read-only via BUS_SPACE_MAP_CACHEABLE and BUS_SPACE_MAP_READONLY respectively. - Do some minor cleanup like taking advantage of rman_init_from_resource(), factor out the common part of bus tag allocation into a newly added sparc64_alloc_bus_tag(), hook up some missing newbus methods and replace some homegrown versions with the generic counterparts etc. - While at it, let apb_attach() (which can't use the generic NEW_PCIB code as APB bridges just don't have the base and limit registers implemented) regarding the config space registers cached in pcib_softc and the SYSCTL reporting nodes set up.
2011-10-02 23:22:38 +00:00
void bus_space_unmap(bus_space_tag_t tag, bus_space_handle_t handle,
bus_size_t size);
/* This macro finds the first "upstream" implementation of method `f' */
#define _BS_CALL(t,f) \
while (t->f == NULL) \
t = t->bst_parent; \
return (*(t)->f)
static __inline void
bus_space_barrier(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o,
bus_size_t s, int f)
{
_BS_CALL(t, bst_bus_barrier)(t, h, o, s, f);
}
2003-01-08 04:29:00 +00:00
static __inline int
bus_space_subregion(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o,
bus_size_t s, bus_space_handle_t *hp)
{
2003-01-08 04:29:00 +00:00
*hp = h + o;
return (0);
}
/* flags for bus space map functions */
#define BUS_SPACE_MAP_CACHEABLE 0x0001
#define BUS_SPACE_MAP_LINEAR 0x0002
#define BUS_SPACE_MAP_READONLY 0x0004
#define BUS_SPACE_MAP_PREFETCHABLE 0x0008
/* placeholders for bus functions... */
#define BUS_SPACE_MAP_BUS1 0x0100
#define BUS_SPACE_MAP_BUS2 0x0200
#define BUS_SPACE_MAP_BUS3 0x0400
#define BUS_SPACE_MAP_BUS4 0x0800
/* flags for bus_space_barrier() */
#define BUS_SPACE_BARRIER_READ 0x01 /* force read barrier */
#define BUS_SPACE_BARRIER_WRITE 0x02 /* force write barrier */
#ifdef BUS_SPACE_DEBUG
#define KTR_BUS KTR_SPARE2
#define __BUS_DEBUG_ACCESS(h, o, desc, sz) do { \
CTR4(KTR_BUS, "bus space: %s %d: handle %#lx, offset %#lx", \
(desc), (sz), (h), (o)); \
} while (0)
#else
#define __BUS_DEBUG_ACCESS(h, o, desc, sz)
#endif
static __inline uint8_t
bus_space_read_1(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o)
{
__BUS_DEBUG_ACCESS(h, o, "read", 1);
return (lduba_nc((caddr_t)(h + o), bus_type_asi[t->bst_type]));
}
static __inline uint16_t
bus_space_read_2(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o)
{
__BUS_DEBUG_ACCESS(h, o, "read", 2);
return (lduha_nc((caddr_t)(h + o), bus_type_asi[t->bst_type]));
}
static __inline uint32_t
bus_space_read_4(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o)
{
__BUS_DEBUG_ACCESS(h, o, "read", 4);
return (lduwa_nc((caddr_t)(h + o), bus_type_asi[t->bst_type]));
}
static __inline uint64_t
bus_space_read_8(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o)
{
__BUS_DEBUG_ACCESS(h, o, "read", 8);
return (ldxa_nc((caddr_t)(h + o), bus_type_asi[t->bst_type]));
}
static __inline void
bus_space_read_multi_1(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o,
uint8_t *a, size_t c)
{
while (c-- > 0)
*a++ = bus_space_read_1(t, h, o);
}
static __inline void
bus_space_read_multi_2(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o,
uint16_t *a, size_t c)
{
while (c-- > 0)
*a++ = bus_space_read_2(t, h, o);
}
static __inline void
bus_space_read_multi_4(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o,
uint32_t *a, size_t c)
{
while (c-- > 0)
*a++ = bus_space_read_4(t, h, o);
}
static __inline void
bus_space_read_multi_8(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o,
uint64_t *a, size_t c)
{
while (c-- > 0)
*a++ = bus_space_read_8(t, h, o);
}
static __inline void
bus_space_write_1(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o,
uint8_t v)
{
__BUS_DEBUG_ACCESS(h, o, "write", 1);
stba_nc((caddr_t)(h + o), bus_type_asi[t->bst_type], v);
}
static __inline void
bus_space_write_2(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o,
uint16_t v)
{
__BUS_DEBUG_ACCESS(h, o, "write", 2);
stha_nc((caddr_t)(h + o), bus_type_asi[t->bst_type], v);
}
static __inline void
bus_space_write_4(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o,
uint32_t v)
{
__BUS_DEBUG_ACCESS(h, o, "write", 4);
stwa_nc((caddr_t)(h + o), bus_type_asi[t->bst_type], v);
}
static __inline void
bus_space_write_8(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o,
uint64_t v)
{
__BUS_DEBUG_ACCESS(h, o, "write", 8);
stxa_nc((caddr_t)(h + o), bus_type_asi[t->bst_type], v);
}
static __inline void
bus_space_write_multi_1(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o,
const uint8_t *a, size_t c)
{
while (c-- > 0)
bus_space_write_1(t, h, o, *a++);
}
static __inline void
bus_space_write_multi_2(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o,
const uint16_t *a, size_t c)
{
while (c-- > 0)
bus_space_write_2(t, h, o, *a++);
}
static __inline void
bus_space_write_multi_4(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o,
const uint32_t *a, size_t c)
{
while (c-- > 0)
bus_space_write_4(t, h, o, *a++);
}
static __inline void
bus_space_write_multi_8(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o,
const uint64_t *a, size_t c)
{
while (c-- > 0)
bus_space_write_8(t, h, o, *a++);
}
static __inline void
bus_space_set_multi_1(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o,
uint8_t v, size_t c)
{
while (c-- > 0)
bus_space_write_1(t, h, o, v);
}
static __inline void
bus_space_set_multi_2(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o,
uint16_t v, size_t c)
{
while (c-- > 0)
bus_space_write_2(t, h, o, v);
}
static __inline void
bus_space_set_multi_4(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o,
uint32_t v, size_t c)
{
while (c-- > 0)
bus_space_write_4(t, h, o, v);
}
static __inline void
bus_space_set_multi_8(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o,
uint64_t v, size_t c)
{
while (c-- > 0)
bus_space_write_8(t, h, o, v);
}
static __inline void
bus_space_read_region_1(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o,
uint8_t *a, bus_size_t c)
{
for (; c; a++, c--, o++)
*a = bus_space_read_1(t, h, o);
}
static __inline void
bus_space_read_region_2(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o,
uint16_t *a, bus_size_t c)
{
for (; c; a++, c--, o += 2)
*a = bus_space_read_2(t, h, o);
}
static __inline void
bus_space_read_region_4(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o,
uint32_t *a, bus_size_t c)
{
for (; c; a++, c--, o += 4)
*a = bus_space_read_4(t, h, o);
}
static __inline void
bus_space_read_region_8(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o,
uint64_t *a, bus_size_t c)
{
for (; c; a++, c--, o += 8)
*a = bus_space_read_8(t, h, o);
}
static __inline void
bus_space_write_region_1(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o,
const uint8_t *a, bus_size_t c)
{
for (; c; a++, c--, o++)
bus_space_write_1(t, h, o, *a);
}
static __inline void
bus_space_write_region_2(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o,
const uint16_t *a, bus_size_t c)
{
for (; c; a++, c--, o += 2)
bus_space_write_2(t, h, o, *a);
}
static __inline void
bus_space_write_region_4(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o,
const uint32_t *a, bus_size_t c)
{
for (; c; a++, c--, o += 4)
bus_space_write_4(t, h, o, *a);
}
static __inline void
bus_space_write_region_8(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o,
const uint64_t *a, bus_size_t c)
{
for (; c; a++, c--, o += 8)
bus_space_write_8(t, h, o, *a);
}
static __inline void
bus_space_set_region_1(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o,
const uint8_t v, bus_size_t c)
{
for (; c; c--, o++)
bus_space_write_1(t, h, o, v);
}
static __inline void
bus_space_set_region_2(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o,
const uint16_t v, bus_size_t c)
{
for (; c; c--, o += 2)
bus_space_write_2(t, h, o, v);
}
static __inline void
bus_space_set_region_4(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o,
const uint32_t v, bus_size_t c)
{
for (; c; c--, o += 4)
bus_space_write_4(t, h, o, v);
}
static __inline void
bus_space_set_region_8(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o,
const uint64_t v, bus_size_t c)
{
for (; c; c--, o += 8)
bus_space_write_8(t, h, o, v);
}
static __inline void
bus_space_copy_region_1(bus_space_tag_t t, bus_space_handle_t h1,
bus_size_t o1, bus_space_handle_t h2, bus_size_t o2, bus_size_t c)
{
for (; c; c--, o1++, o2++)
bus_space_write_1(t, h1, o1, bus_space_read_1(t, h2, o2));
}
static __inline void
bus_space_copy_region_2(bus_space_tag_t t, bus_space_handle_t h1,
bus_size_t o1, bus_space_handle_t h2, bus_size_t o2, bus_size_t c)
{
for (; c; c--, o1 += 2, o2 += 2)
bus_space_write_2(t, h1, o1, bus_space_read_2(t, h2, o2));
}
static __inline void
bus_space_copy_region_4(bus_space_tag_t t, bus_space_handle_t h1,
bus_size_t o1, bus_space_handle_t h2, bus_size_t o2, bus_size_t c)
{
for (; c; c--, o1 += 4, o2 += 4)
bus_space_write_4(t, h1, o1, bus_space_read_4(t, h2, o2));
}
static __inline void
bus_space_copy_region_8(bus_space_tag_t t, bus_space_handle_t h1,
bus_size_t o1, bus_space_handle_t h2, bus_size_t o2, bus_size_t c)
{
for (; c; c--, o1 += 8, o2 += 8)
bus_space_write_8(t, h1, o1, bus_space_read_8(t, h2, o2));
}
static __inline uint8_t
bus_space_read_stream_1(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o)
{
__BUS_DEBUG_ACCESS(h, o, "read stream", 1);
return (lduba_nc((caddr_t)(h + o), bus_stream_asi[t->bst_type]));
}
static __inline uint16_t
bus_space_read_stream_2(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o)
{
__BUS_DEBUG_ACCESS(h, o, "read stream", 2);
return (lduha_nc((caddr_t)(h + o), bus_stream_asi[t->bst_type]));
}
static __inline uint32_t
bus_space_read_stream_4(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o)
{
__BUS_DEBUG_ACCESS(h, o, "read stream", 4);
return (lduwa_nc((caddr_t)(h + o), bus_stream_asi[t->bst_type]));
}
static __inline uint64_t
bus_space_read_stream_8(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o)
{
__BUS_DEBUG_ACCESS(h, o, "read stream", 8);
return (ldxa_nc((caddr_t)(h + o), bus_stream_asi[t->bst_type]));
}
static __inline void
bus_space_read_multi_stream_1(bus_space_tag_t t, bus_space_handle_t h,
bus_size_t o, uint8_t *a, size_t c)
{
while (c-- > 0)
*a++ = bus_space_read_stream_1(t, h, o);
}
static __inline void
bus_space_read_multi_stream_2(bus_space_tag_t t, bus_space_handle_t h,
bus_size_t o, uint16_t *a, size_t c)
{
while (c-- > 0)
*a++ = bus_space_read_stream_2(t, h, o);
}
static __inline void
bus_space_read_multi_stream_4(bus_space_tag_t t, bus_space_handle_t h,
bus_size_t o, uint32_t *a, size_t c)
{
while (c-- > 0)
*a++ = bus_space_read_stream_4(t, h, o);
}
static __inline void
bus_space_read_multi_stream_8(bus_space_tag_t t, bus_space_handle_t h,
bus_size_t o, uint64_t *a, size_t c)
{
while (c-- > 0)
*a++ = bus_space_read_stream_8(t, h, o);
}
static __inline void
bus_space_write_stream_1(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o,
uint8_t v)
{
__BUS_DEBUG_ACCESS(h, o, "write stream", 1);
stba_nc((caddr_t)(h + o), bus_stream_asi[t->bst_type], v);
}
static __inline void
bus_space_write_stream_2(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o,
uint16_t v)
{
__BUS_DEBUG_ACCESS(h, o, "write stream", 2);
stha_nc((caddr_t)(h + o), bus_stream_asi[t->bst_type], v);
}
static __inline void
bus_space_write_stream_4(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o,
uint32_t v)
{
__BUS_DEBUG_ACCESS(h, o, "write stream", 4);
stwa_nc((caddr_t)(h + o), bus_stream_asi[t->bst_type], v);
}
static __inline void
bus_space_write_stream_8(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o,
uint64_t v)
{
__BUS_DEBUG_ACCESS(h, o, "write stream", 8);
stxa_nc((caddr_t)(h + o), bus_stream_asi[t->bst_type], v);
}
static __inline void
bus_space_write_multi_stream_1(bus_space_tag_t t, bus_space_handle_t h,
bus_size_t o, const uint8_t *a, size_t c)
{
while (c-- > 0)
bus_space_write_stream_1(t, h, o, *a++);
}
static __inline void
bus_space_write_multi_stream_2(bus_space_tag_t t, bus_space_handle_t h,
bus_size_t o, const uint16_t *a, size_t c)
{
while (c-- > 0)
bus_space_write_stream_2(t, h, o, *a++);
}
static __inline void
bus_space_write_multi_stream_4(bus_space_tag_t t, bus_space_handle_t h,
bus_size_t o, const uint32_t *a, size_t c)
{
while (c-- > 0)
bus_space_write_stream_4(t, h, o, *a++);
}
static __inline void
bus_space_write_multi_stream_8(bus_space_tag_t t, bus_space_handle_t h,
bus_size_t o, const uint64_t *a, size_t c)
{
while (c-- > 0)
bus_space_write_stream_8(t, h, o, *a++);
}
static __inline void
bus_space_set_multi_stream_1(bus_space_tag_t t, bus_space_handle_t h,
bus_size_t o, uint8_t v, size_t c)
{
while (c-- > 0)
bus_space_write_stream_1(t, h, o, v);
}
static __inline void
bus_space_set_multi_stream_2(bus_space_tag_t t, bus_space_handle_t h,
bus_size_t o, uint16_t v, size_t c)
{
while (c-- > 0)
bus_space_write_stream_2(t, h, o, v);
}
static __inline void
bus_space_set_multi_stream_4(bus_space_tag_t t, bus_space_handle_t h,
bus_size_t o, uint32_t v, size_t c)
{
while (c-- > 0)
bus_space_write_stream_4(t, h, o, v);
}
static __inline void
bus_space_set_multi_stream_8(bus_space_tag_t t, bus_space_handle_t h,
bus_size_t o, uint64_t v, size_t c)
{
while (c-- > 0)
bus_space_write_stream_8(t, h, o, v);
}
static __inline void
bus_space_read_region_stream_1(bus_space_tag_t t, bus_space_handle_t h,
bus_size_t o, uint8_t *a, bus_size_t c)
{
for (; c; a++, c--, o++)
*a = bus_space_read_stream_1(t, h, o);
}
static __inline void
bus_space_read_region_stream_2(bus_space_tag_t t, bus_space_handle_t h,
bus_size_t o, uint16_t *a, bus_size_t c)
{
for (; c; a++, c--, o += 2)
*a = bus_space_read_stream_2(t, h, o);
}
static __inline void
bus_space_read_region_stream_4(bus_space_tag_t t, bus_space_handle_t h,
bus_size_t o, uint32_t *a, bus_size_t c)
{
for (; c; a++, c--, o += 4)
*a = bus_space_read_stream_4(t, h, o);
}
static __inline void
bus_space_read_region_stream_8(bus_space_tag_t t, bus_space_handle_t h,
bus_size_t o, uint64_t *a, bus_size_t c)
{
for (; c; a++, c--, o += 8)
*a = bus_space_read_stream_8(t, h, o);
}
static __inline void
bus_space_write_region_stream_1(bus_space_tag_t t, bus_space_handle_t h,
bus_size_t o, const uint8_t *a, bus_size_t c)
{
for (; c; a++, c--, o++)
bus_space_write_stream_1(t, h, o, *a);
}
static __inline void
bus_space_write_region_stream_2(bus_space_tag_t t, bus_space_handle_t h,
bus_size_t o, const uint16_t *a, bus_size_t c)
{
for (; c; a++, c--, o += 2)
bus_space_write_stream_2(t, h, o, *a);
}
static __inline void
bus_space_write_region_stream_4(bus_space_tag_t t, bus_space_handle_t h,
bus_size_t o, const uint32_t *a, bus_size_t c)
{
for (; c; a++, c--, o += 4)
bus_space_write_stream_4(t, h, o, *a);
}
static __inline void
bus_space_write_region_stream_8(bus_space_tag_t t, bus_space_handle_t h,
bus_size_t o, const uint64_t *a, bus_size_t c)
{
for (; c; a++, c--, o += 8)
bus_space_write_stream_8(t, h, o, *a);
}
static __inline void
bus_space_set_region_stream_1(bus_space_tag_t t, bus_space_handle_t h,
bus_size_t o, const uint8_t v, bus_size_t c)
{
for (; c; c--, o++)
bus_space_write_stream_1(t, h, o, v);
}
static __inline void
bus_space_set_region_stream_2(bus_space_tag_t t, bus_space_handle_t h,
bus_size_t o, const uint16_t v, bus_size_t c)
{
for (; c; c--, o += 2)
bus_space_write_stream_2(t, h, o, v);
}
static __inline void
bus_space_set_region_stream_4(bus_space_tag_t t, bus_space_handle_t h,
bus_size_t o, const uint32_t v, bus_size_t c)
{
for (; c; c--, o += 4)
bus_space_write_stream_4(t, h, o, v);
}
static __inline void
bus_space_set_region_stream_8(bus_space_tag_t t, bus_space_handle_t h,
bus_size_t o, const uint64_t v, bus_size_t c)
{
for (; c; c--, o += 8)
bus_space_write_stream_8(t, h, o, v);
}
static __inline void
bus_space_copy_region_stream_1(bus_space_tag_t t, bus_space_handle_t h1,
bus_size_t o1, bus_space_handle_t h2, bus_size_t o2, bus_size_t c)
{
for (; c; c--, o1++, o2++)
bus_space_write_stream_1(t, h1, o1, bus_space_read_stream_1(t, h2,
o2));
}
static __inline void
bus_space_copy_region_stream_2(bus_space_tag_t t, bus_space_handle_t h1,
bus_size_t o1, bus_space_handle_t h2, bus_size_t o2, bus_size_t c)
{
for (; c; c--, o1 += 2, o2 += 2)
bus_space_write_stream_2(t, h1, o1, bus_space_read_stream_2(t, h2,
o2));
}
static __inline void
bus_space_copy_region_stream_4(bus_space_tag_t t, bus_space_handle_t h1,
bus_size_t o1, bus_space_handle_t h2, bus_size_t o2, bus_size_t c)
{
for (; c; c--, o1 += 4, o2 += 4)
bus_space_write_stream_4(t, h1, o1, bus_space_read_stream_4(t, h2,
o2));
}
static __inline void
bus_space_copy_region_stream_8(bus_space_tag_t t, bus_space_handle_t h1,
bus_size_t o1, bus_space_handle_t h2, bus_size_t o2, bus_size_t c)
{
for (; c; c--, o1 += 8, o2 += 8)
bus_space_write_stream_8(t, h1, o1, bus_space_read_8(t, h2, o2));
}
static __inline int
bus_space_peek_1(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o,
uint8_t *a)
{
__BUS_DEBUG_ACCESS(h, o, "peek", 1);
return (fasword8(bus_type_asi[t->bst_type], (caddr_t)(h + o), a));
}
static __inline int
bus_space_peek_2(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o,
uint16_t *a)
{
__BUS_DEBUG_ACCESS(h, o, "peek", 2);
return (fasword16(bus_type_asi[t->bst_type], (caddr_t)(h + o), a));
}
static __inline int
bus_space_peek_4(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o,
uint32_t *a)
{
__BUS_DEBUG_ACCESS(h, o, "peek", 4);
return (fasword32(bus_type_asi[t->bst_type], (caddr_t)(h + o), a));
}
#include <machine/bus_dma.h>
#endif /* !_MACHINE_BUS_H_ */