1995-05-12 15:09:29 +00:00
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/*
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* Copyright (C) 1995 by Pavel Antonov, Moscow, Russia.
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* Copyright (C) 1995 by Andrey A. Chernov, Moscow, Russia.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/*
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* Cirrus Logic CD180 registers
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*/
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/* Global registers */
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#define CD180_GIVR 0x40 /* Global Interrupt Verctor Register */
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#define CD180_GICR 0x41 /* Global Interrupting Channel Register */
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#define CD180_PILR1 0x61 /* Priority Interrupt Level Register 1 */
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#define CD180_PILR2 0x62 /* Priority Interrupt Level Register 2 */
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#define CD180_PILR3 0x63 /* Priority Interrupt Level Register 3 */
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#define CD180_CAR 0x64 /* Channel Access Register */
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#define CD180_GFRCR 0x6B /* Global Firmware Revision Code Register */
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#define CD180_PPRH 0x70 /* Prescaler Period Register MSB */
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#define CD180_PPRL 0x71 /* Prescaler Period Register LSB */
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#define CD180_RDR 0x78 /* Receiver Data Register */
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#define CD180_RCSR 0x7A /* Receiver Character Status Register */
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#define CD180_TDR 0x7B /* Transmit Data Register */
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#define CD180_EOIR 0x7F /* End of Interrupt Register */
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/* Channel Registers */
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#define CD180_CCR 0x01 /* Channel Command Register */
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#define CD180_IER 0x02 /* Interrupt Enable Register */
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#define CD180_COR1 0x03 /* Channel Option Register 1 */
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#define CD180_COR2 0x04 /* Channel Option Register 1 */
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#define CD180_COR3 0x05 /* Channel Option Register 1 */
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#define CD180_CCSR 0x06 /* Channel Control STatus Register */
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#define CD180_RDCR 0x07 /* Receive Data Count Register */
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#define CD180_SCHR1 0x09 /* Special Character Register 1 */
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#define CD180_SCHR2 0x0A /* Special Character Register 2 */
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#define CD180_SCHR3 0x0B /* Special Character Register 3 */
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#define CD180_SCHR4 0x0C /* Special Character Register 4 */
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#define CD180_MCOR1 0x10 /* Modem Change Option 1 Register */
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#define CD180_MCOR2 0x11 /* Modem Change Option 2 Register */
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#define CD180_MCR 0x12 /* Modem Change Register */
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#define CD180_RTPR 0x18 /* Receive Timeout Period Register */
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#define CD180_MSVR 0x28 /* Modem Signal Value Register */
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#define CD180_RBPRH 0x31 /* Receive Baud Rate Period Register MSB */
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#define CD180_RBPRL 0x32 /* Receive Baud Rate Period Register LSB */
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#define CD180_TBPRH 0x39 /* Transmit Baud Rate Period Register MSB */
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#define CD180_TBPRL 0x3A /* Transmit Baud Rate Period Register LSB */
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/** Register descritpions **/
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/* Global Interrupt Vector Register */
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#define GIVR_IT_MSCI 0x01 /* Modem Signal Change Interrupt */
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#define GIVR_IT_TDI 0x02 /* Transmit Data Interrupt */
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#define GIVR_IT_RGDI 0x03 /* Receive Good Data Interrupt */
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#define GIVR_IT_REI 0x07 /* Receive Exception Interrupt */
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/* Global Interrupt Channel Register */
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#define GICR_CHAN 0x1C /* Channel Number Mask */
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#define GICR_LSH 2 /* Channel Number Shift */
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/* Channel Address Register */
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#define CAR_CHAN 0x07 /* Channel Number Mask */
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#define CAR_A7 0x08 /* Addres bit 7 (unused) */
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/* Receive Character Status Register */
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#define RCSR_OE 0x01 /* Overrun Error */
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#define RCSR_FE 0x02 /* Frame Error */
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#define RCSR_PE 0x04 /* Parity Error */
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1995-06-14 19:37:02 +00:00
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#define RCSR_Break 0x08 /* Break detected */
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#define RCSR_Timeout 0x80 /* Rx Timeout */
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#define RCSR_SCMASK 0x70 /* Special Character Detected Mask */
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1995-05-12 15:09:29 +00:00
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#define RCSR_SC1 0x10 /* Special Char 1 (or 1 & 3 seq matched) */
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#define RCSR_SC2 0x20 /* Special Char 2 (or 2 & 4 seq matched) */
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#define RCSR_SC3 0x30 /* Special Char 3 */
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#define RCSR_SC4 0x40 /* Special Char 4 */
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/* Channel Command Register */
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1995-06-14 19:37:02 +00:00
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#define CCR_ResetChan 0x80 /* Reset Channel */
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1995-05-12 15:09:29 +00:00
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#define CCR_HWRESET 0x81 /* Hardware Reset (all channels) */
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#define CCR_CORCHG1 0x42 /* Channel Option Register 1 Changed */
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#define CCR_CORCHG2 0x44 /* Channel Option Register 2 Changed */
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#define CCR_CORCHG3 0x48 /* Channel Option Register 3 Changed */
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1995-06-14 19:37:02 +00:00
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#define CCR_SENDSPCH1 0x21 /* Send Special Character 1 */
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#define CCR_SENDSPCH2 0x22 /* Send Special Character 2 */
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#define CCR_SENDSPCH3 0x23 /* Send Special Character 3 */
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#define CCR_SENDSPCH4 0x24 /* Send Special Character 4 */
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#define CCR_RCVRDIS 0x11 /* Receiver Disable */
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#define CCR_RCVREN 0x12 /* Receiver Enable */
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#define CCR_XMTRDIS 0x14 /* Transmitter Disable */
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#define CCR_XMTREN 0x18 /* Transmitter Enable */
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1995-05-12 15:09:29 +00:00
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/* Interrupt Enable Register */
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#define IER_DSR 0x80 /* Enable interrupt on DSR change */
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#define IER_CD 0x40 /* Enable interrupt on CD change */
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#define IER_CTS 0x20 /* Enable interrupt on CTS change */
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1995-06-14 19:37:02 +00:00
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#define IER_RxData 0x10 /* Enable interrupt on Receive Data */
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#define IER_RxSC 0x08 /* Enable interrupt on Receive Spec. Char */
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#define IER_TxRdy 0x04 /* Enable interrupt on TX FIFO empty */
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#define IER_TxMpty 0x02 /* Enable interrupt on TX completely empty*/
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1995-05-12 15:09:29 +00:00
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#define IER_RET 0x01 /* Enable interrupt on RX Except. Timeout */
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/* Channel Option Register 1 */
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#define COR1_ODDP 0x80 /* Odd Parity */
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1995-06-14 19:37:02 +00:00
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#define COR1_ParMMASK 0x60 /* Parity Mode mask */
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1995-05-12 15:09:29 +00:00
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#define COR1_NOPAR 0x02 /* No Parity */
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#define COR1_FORCEPAR 0x20 /* Force Parity */
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#define COR1_NORMPAR 0x40 /* Normal Parity */
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1995-06-14 19:37:02 +00:00
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#define COR1_Ignore 0x10 /* Ignore Parity on RX */
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#define COR1_StopMASK 0x0C /* Stop Bits mode mask */
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1995-05-12 15:09:29 +00:00
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#define COR1_1SB 0x00 /* 1 Stop Bit */
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#define COR1_15SB 0x04 /* 1.5 Stop Bits */
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#define COR1_2SB 0x08 /* 2 Stop Bits */
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#define COR1_CHLMASK 0x03 /* Character Length mask */
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#define COR1_5BITS 0x00 /* 5 bits */
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#define COR1_6BITS 0x01 /* 6 bits */
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#define COR1_7BITS 0x02 /* 7 bits */
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#define COR1_8BITS 0x03 /* 8 bits */
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/* Channel Option Register 2 */
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#define COR2_IXM 0x80 /* Implied XON mode */
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1995-06-14 19:37:02 +00:00
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#define COR2_TxIBE 0x40 /* Enable In-Band XON/XOFF Flow Control */
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1995-05-12 15:09:29 +00:00
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#define COR2_ETC 0x20 /* Embedded Tx Commands Enable */
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#define COR2_LLM 0x10 /* Local Loopback Mode */
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#define COR2_RLM 0x08 /* Remote Loopback Mode */
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1995-06-14 19:37:02 +00:00
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#define COR2_RtsAO 0x04 /* RTS Automatic Output Enable */
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#define COR2_CtsAE 0x02 /* CTS Automatic Enable */
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#define COR2_DsrAE 0x01 /* DSR Automatic Enable */
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1995-05-12 15:09:29 +00:00
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/* Channel Option Register 3 */
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1995-06-14 19:37:02 +00:00
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#define COR3_XonCH 0x80 /* XON is a double seq (1 & 3) */
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#define COR3_XoffCH 0x40 /* XOFF is a double seq (1 & 3) */
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1995-05-12 15:09:29 +00:00
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#define COR3_FCT 0x20 /* Flow-Control Transparency Mode */
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#define COR3_SCDE 0x10 /* Special Character Detection Enable */
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1995-06-14 19:37:02 +00:00
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#define COR3_RxTHMASK 0x0F /* RX FIFO Threshold value (1-8) */
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1995-05-12 15:09:29 +00:00
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/* Channel Control Status Register */
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1995-06-14 19:37:02 +00:00
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#define CCSR_RxEn 0x80 /* Revceiver Enabled */
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#define CCSR_RxFloff 0x40 /* Receive Flow Off (XOFF sent) */
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#define CCSR_RxFlon 0x20 /* Receive Flow On (XON sent) */
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#define CCSR_TxEn 0x08 /* Transmitter Enabled */
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#define CCSR_TxFloff 0x04 /* Transmit Flow Off (got XOFF) */
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#define CCSR_TxFlon 0x02 /* Transmit Flow On (got XON) */
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1995-05-12 15:09:29 +00:00
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/* Modem Change Option Register 1 */
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1995-06-14 19:37:02 +00:00
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#define MCOR1_DSRzd 0x80 /* Detect 0->1 transition of DSR */
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#define MCOR1_CDzd 0x40 /* Detect 0->1 transition of CD */
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#define MCOR1_CTSzd 0x20 /* Detect 0->1 transition of CTS */
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#define MCOR1_DTRthMASK 0x0F /* Automatic DTR FC Threshold (1-8) chars */
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1995-05-12 15:09:29 +00:00
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/* Modem Change Option Register 2 */
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1995-06-14 19:37:02 +00:00
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#define MCOR2_DSRod 0x80 /* Detect 1->0 transition of DSR */
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#define MCOR2_CDod 0x40 /* Detect 1->0 transition of CD */
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#define MCOR2_CTSod 0x20 /* Detect 1->0 transition of CTS */
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1995-05-12 15:09:29 +00:00
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/* Modem Change Register */
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1995-06-14 19:37:02 +00:00
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#define MCR_DSRchg 0x80 /* DSR Changed */
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#define MCR_CDchg 0x40 /* CD Changed */
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#define MCR_CTSchg 0x20 /* CTS Changed */
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1995-05-12 15:09:29 +00:00
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/* Modem Signal Value Register */
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#define MSVR_DSR 0x80 /* Current state of DSR input */
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#define MSVR_CD 0x40 /* Current state of DSR input */
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#define MSVR_CTS 0x20 /* Current state of CTS input */
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#define MSVR_DTR 0x02 /* Current state of DTR output */
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#define MSVR_RTS 0x01 /* Current state of RTS output */
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/* Escape characters */
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#define CD180_C_ESC 0x00 /* Escape character */
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#define CD180_C_SBRK 0x81 /* Start sending BREAK */
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#define CD180_C_DELAY 0x82 /* Delay output */
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#define CD180_C_EBRK 0x83 /* Stop sending BREAK */
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/* Miscellaneous */
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#define CD180_NCHAN 8 /* 8 channels per chip */
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#define CD180_CTICKS 16 /* 16 ticks for character processing */
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#define CD180_NFIFO 8 /* 8 bytes in FIFO */
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