77 lines
2.8 KiB
C
77 lines
2.8 KiB
C
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/*-
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* Copyright (c) 2015 Stanislav Galabov.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef __RT305X_PCIREG_H__
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#define __RT305X_PCIREG_H__
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#define RT305X_PCI_NIRQS 1
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#define RT305X_PCI_BASESLOT 0
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#define RT305X_PCI_PCICFG 0x0000
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#define RT305X_PCI_PCIINT 0x0008
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#define RT305X_PCI_PCIENA 0x000C
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#define RT305X_PCI_CFGADDR 0x0020
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#define RT305X_PCI_CFGDATA 0x0024
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#define RT305X_PCI_MEMBASE 0x0028
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#define RT305X_PCI_IOBASE 0x002C
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#define RT305X_PCI_PHY0_CFG 0x0090
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#define RT305X_PCI_PCIE0_BAR0SETUP 0x2010
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#define RT305X_PCI_PCIE0_BAR1SETUP 0x2014
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#define RT305X_PCI_PCIE0_IMBASEBAR0 0x2018
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#define RT305X_PCI_PCIE0_ID 0x2030
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#define RT305X_PCI_PCIE0_CLASS 0x2034
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#define RT305X_PCI_PCIE0_SUBID 0x2038
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#define RT305X_PCI_PCIE0_STATUS 0x2050
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#define RT305X_PCI_PCIE0_DLECR 0x2060
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#define RT305X_PCI_PCIE0_ECRC 0x2064
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#define RT305X_PCIE0_IRQ 20
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#define RT305X_PCIE1_IRQ 21
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#define RT305X_PCIE2_IRQ 22
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#define RT305X_PCI_INTR_PIN 2
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#define PCI_MIN_IO_ALLOC 4
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#define PCI_MIN_MEM_ALLOC 16
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#define BITS_PER_UINT32 (NBBY * sizeof(uint32_t))
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#define RT_WRITE32(sc, off, val) \
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bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (off), (val))
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#define RT_WRITE16(sc, off, val) \
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bus_space_write_2((sc)->sc_bst, (sc)->sc_bsh, (off), (val))
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#define RT_WRITE8(sc, off, val) \
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bus_space_write_1((sc)->sc_bst, (sc)->sc_bsh, (off), (val))
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#define RT_READ32(sc, off) \
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bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (off))
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#define RT_READ16(sc, off) \
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bus_space_read_2((sc)->sc_bst, (sc)->sc_bsh, (off))
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#define RT_READ8(sc, off) \
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bus_space_read_1((sc)->sc_bst, (sc)->sc_bsh, (off))
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#endif /* __RT305X_PCIREG_H__ */
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