1995-05-12 15:09:29 +00:00
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/*
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* Copyright (C) 1995 by Pavel Antonov, Moscow, Russia.
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* Copyright (C) 1995 by Andrey A. Chernov, Moscow, Russia.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/*
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* Cirrus Logic CD180 -based RISCom/8 board definitions
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*/
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/* Oscillator frequency - 19660.08Mhz / 2 */
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#define RC_OSCFREQ 9830400
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1995-08-02 10:17:35 +00:00
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#define RC_BRD(s) ((s) == 0 ? 0 : \
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(((RC_OSCFREQ + (s) / 2) / (s)) + CD180_CTICKS/2) / CD180_CTICKS)
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1995-05-12 15:09:29 +00:00
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#define RC_VALIDADDR(a) ( (a) == 0x220 || (a) == 0x240 || (a) == 0x250 \
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|| (a) == 0x260 || (a) == 0x2A0 || (a) == 0x2B0 \
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|| (a) == 0x300 || (a) == 0x320)
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#define RC_VALIDIRQ(i) ((i) < 16 && \
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"\0\0\0\1\1\1\0\1\0\0\1\1\1\0\0\1"[(i) & 0xF])
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1995-06-14 19:37:02 +00:00
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/* Riscom/8 board ISA I/O mapping */
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1995-05-12 15:09:29 +00:00
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#define RC_IOMAP(r) ((((r) & 07) << 1) | (((r) & ~07) << 7))
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/* I/O commands */
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#define RC_OUT(p,i,d) outb(RC_IOMAP(i) + (p), (d))
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#define RC_IN(p,i) inb (RC_IOMAP(i) + (p))
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/* Riscom on-board registers (mapping assumed) */
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1995-06-14 19:37:02 +00:00
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#define RC_RIREG 0x100 /* Ring Indicator Register (read-only) */
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#define RC_DTREG 0x100 /* DTR Register (write-only) */
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1995-05-12 15:09:29 +00:00
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#define RC_BSR 0x101 /* Board Status Register (read-only) */
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#define RC_CTOUT 0x101 /* Clear Timeout (write-only) */
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/* Board Status Register */
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#define RC_BSR_TOUT 0x08 /* Timeout */
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#define RC_BSR_RXINT 0x04 /* Receiver Interrupt */
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#define RC_BSR_TXINT 0x02 /* Transmitter Interrupt */
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#define RC_BSR_MOINT 0x01 /* Modem Control Interrupt */
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/* Interrupt groups */
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#define RC_MODEMGRP 0x01 /* Modem interrupt group */
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1995-06-14 19:37:02 +00:00
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#define RC_RXGRP 0x02 /* Receiver interrupt group */
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#define RC_TXGRP 0x04 /* Transmitter interrupt group */
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1995-05-12 15:09:29 +00:00
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/* Priority Interrupt Level definitions */
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#define RC_PILR_MODEM (0x80 | RC_MODEMGRP)
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#define RC_PILR_RX (0x80 | RC_RXGRP )
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1995-06-14 19:37:02 +00:00
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#define RC_PILR_TX (0x80 | RC_TXGRP )
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