2000-06-09 16:04:30 +00:00
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/*-
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* Copyright (c) 2000 Doug Rabson
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _PCI_AGPREG_H_
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#define _PCI_AGPREG_H_
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/*
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* Offsets for various AGP configuration registers.
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*/
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2005-12-20 22:45:24 +00:00
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#define AGP_APBASE PCIR_BAR(0)
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2000-06-09 16:04:30 +00:00
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/*
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* Offsets from the AGP Capability pointer.
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*/
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#define AGP_CAPID 0x0
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#define AGP_STATUS 0x4
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#define AGP_COMMAND 0x8
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2004-04-05 02:32:07 +00:00
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#define AGP_STATUS_AGP3 0x0008
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#define AGP_STATUS_RQ_MASK 0xff000000
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#define AGP_COMMAND_RQ_MASK 0xff000000
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#define AGP_STATUS_ARQSZ_MASK 0xe000
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#define AGP_COMMAND_ARQSZ_MASK 0xe000
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#define AGP_STATUS_CAL_MASK 0x1c00
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#define AGP_COMMAND_CAL_MASK 0x1c00
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#define AGP_STATUS_ISOCH 0x10000
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#define AGP_STATUS_SBA 0x0200
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#define AGP_STATUS_ITA_COH 0x0100
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#define AGP_STATUS_GART64 0x0080
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#define AGP_STATUS_HTRANS 0x0040
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#define AGP_STATUS_64BIT 0x0020
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#define AGP_STATUS_FW 0x0010
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#define AGP_COMMAND_RQ_MASK 0xff000000
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#define AGP_COMMAND_ARQSZ_MASK 0xe000
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#define AGP_COMMAND_CAL_MASK 0x1c00
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#define AGP_COMMAND_SBA 0x0200
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#define AGP_COMMAND_AGP 0x0100
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#define AGP_COMMAND_GART64 0x0080
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#define AGP_COMMAND_64BIT 0x0020
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#define AGP_COMMAND_FW 0x0010
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2000-06-09 16:04:30 +00:00
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/*
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* Config offsets for Intel AGP chipsets.
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*/
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#define AGP_INTEL_NBXCFG 0x50
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#define AGP_INTEL_ERRSTS 0x91
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#define AGP_INTEL_AGPCTRL 0xb0
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#define AGP_INTEL_APSIZE 0xb4
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#define AGP_INTEL_ATTBASE 0xb8
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2001-11-08 16:03:23 +00:00
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/*
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- Clean up Aperture Access Global Enable (APEN) bit access.
- Rename confusing AGP_INTEL_I845_MCHCFG to AGP_INTEL_I845_AGPM.
- Move E7205 and E7505 from i8x5 to i8x0 family. It probably worked
because the actual offset is the same.
In fact, all three families have the bit at the exact same place. Only
differences are name and width of the registers, i.e., NBXCFG (0x50, dword),
RDCR (0x51, byte), AGPM (0x51, byte), MCHCFG (0x50, word) depending on
the family of the chipsets.
2007-01-05 22:55:19 +00:00
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* Config offsets for Intel i8xx/E7xxx AGP chipsets.
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2001-11-08 16:03:23 +00:00
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*/
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#define AGP_INTEL_MCHCFG 0x50
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#define AGP_INTEL_I820_RDCR 0x51
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- Clean up Aperture Access Global Enable (APEN) bit access.
- Rename confusing AGP_INTEL_I845_MCHCFG to AGP_INTEL_I845_AGPM.
- Move E7205 and E7505 from i8x5 to i8x0 family. It probably worked
because the actual offset is the same.
In fact, all three families have the bit at the exact same place. Only
differences are name and width of the registers, i.e., NBXCFG (0x50, dword),
RDCR (0x51, byte), AGPM (0x51, byte), MCHCFG (0x50, word) depending on
the family of the chipsets.
2007-01-05 22:55:19 +00:00
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#define AGP_INTEL_I845_AGPM 0x51
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2001-11-08 16:03:23 +00:00
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#define AGP_INTEL_I8XX_ERRSTS 0xc8
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2000-06-09 16:04:30 +00:00
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/*
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2004-05-13 20:05:42 +00:00
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* Config offsets for VIA AGP 2.x chipsets.
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2000-06-09 16:04:30 +00:00
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*/
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#define AGP_VIA_GARTCTRL 0x80
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#define AGP_VIA_APSIZE 0x84
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#define AGP_VIA_ATTBASE 0x88
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2004-05-13 20:05:42 +00:00
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/*
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* Config offsets for VIA AGP 3.0 chipsets.
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*/
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#define AGP3_VIA_GARTCTRL 0x90
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#define AGP3_VIA_APSIZE 0x94
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#define AGP3_VIA_ATTBASE 0x98
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2004-08-09 21:01:49 +00:00
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#define AGP_VIA_AGPSEL 0xfd
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2004-05-13 20:05:42 +00:00
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2000-06-09 16:04:30 +00:00
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/*
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* Config offsets for SiS AGP chipsets.
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*/
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#define AGP_SIS_ATTBASE 0x90
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#define AGP_SIS_WINCTRL 0x94
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#define AGP_SIS_TLBCTRL 0x97
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#define AGP_SIS_TLBFLUSH 0x98
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/*
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* Config offsets for Ali AGP chipsets.
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*/
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#define AGP_ALI_AGPCTRL 0xb8
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#define AGP_ALI_ATTBASE 0xbc
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#define AGP_ALI_TLBCTRL 0xc0
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/*
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* Config offsets for the AMD 751 chipset.
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*/
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2001-12-07 05:41:26 +00:00
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#define AGP_AMD751_APBASE 0x10
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2000-06-09 16:04:30 +00:00
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#define AGP_AMD751_REGISTERS 0x14
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#define AGP_AMD751_APCTRL 0xac
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#define AGP_AMD751_MODECTRL 0xb0
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2000-06-10 17:44:53 +00:00
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#define AGP_AMD751_MODECTRL_SYNEN 0x80
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#define AGP_AMD751_MODECTRL2 0xb2
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#define AGP_AMD751_MODECTRL2_G1LM 0x01
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#define AGP_AMD751_MODECTRL2_GPDCE 0x02
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#define AGP_AMD751_MODECTRL2_NGSE 0x08
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2000-06-09 16:04:30 +00:00
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/*
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* Memory mapped register offsets for AMD 751 chipset.
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*/
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#define AGP_AMD751_CAPS 0x00
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#define AGP_AMD751_CAPS_EHI 0x0800
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#define AGP_AMD751_CAPS_P2P 0x0400
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#define AGP_AMD751_CAPS_MPC 0x0200
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#define AGP_AMD751_CAPS_VBE 0x0100
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#define AGP_AMD751_CAPS_REV 0x00ff
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#define AGP_AMD751_STATUS 0x02
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#define AGP_AMD751_STATUS_P2PS 0x0800
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#define AGP_AMD751_STATUS_GCS 0x0400
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#define AGP_AMD751_STATUS_MPS 0x0200
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#define AGP_AMD751_STATUS_VBES 0x0100
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#define AGP_AMD751_STATUS_P2PE 0x0008
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#define AGP_AMD751_STATUS_GCE 0x0004
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#define AGP_AMD751_STATUS_VBEE 0x0001
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#define AGP_AMD751_ATTBASE 0x04
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#define AGP_AMD751_TLBCTRL 0x0c
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2000-07-12 10:13:07 +00:00
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/*
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* Config registers for i810 device 0
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*/
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#define AGP_I810_SMRAM 0x70
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#define AGP_I810_SMRAM_GMS 0xc0
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#define AGP_I810_SMRAM_GMS_DISABLED 0x00
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#define AGP_I810_SMRAM_GMS_ENABLED_0 0x40
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#define AGP_I810_SMRAM_GMS_ENABLED_512 0x80
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#define AGP_I810_SMRAM_GMS_ENABLED_1024 0xc0
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#define AGP_I810_MISCC 0x72
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#define AGP_I810_MISCC_WINSIZE 0x0001
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#define AGP_I810_MISCC_WINSIZE_64 0x0000
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#define AGP_I810_MISCC_WINSIZE_32 0x0001
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#define AGP_I810_MISCC_PLCK 0x0008
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#define AGP_I810_MISCC_PLCK_UNLOCKED 0x0000
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#define AGP_I810_MISCC_PLCK_LOCKED 0x0008
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#define AGP_I810_MISCC_WPTC 0x0030
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#define AGP_I810_MISCC_WPTC_NOLIMIT 0x0000
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#define AGP_I810_MISCC_WPTC_62 0x0010
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#define AGP_I810_MISCC_WPTC_50 0x0020
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#define AGP_I810_MISCC_WPTC_37 0x0030
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#define AGP_I810_MISCC_RPTC 0x00c0
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#define AGP_I810_MISCC_RPTC_NOLIMIT 0x0000
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#define AGP_I810_MISCC_RPTC_62 0x0040
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#define AGP_I810_MISCC_RPTC_50 0x0080
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#define AGP_I810_MISCC_RPTC_37 0x00c0
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/*
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* Config registers for i810 device 1
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*/
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#define AGP_I810_GMADR 0x10
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#define AGP_I810_MMADR 0x14
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/*
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* Memory mapped register offsets for i810 chipset.
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*/
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#define AGP_I810_PGTBL_CTL 0x2020
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2007-07-13 16:28:12 +00:00
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/**
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* This field determines the actual size of the global GTT on the 965
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* and G33
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*/
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#define AGP_I810_PGTBL_SIZE_MASK 0x0000000e
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#define AGP_I810_PGTBL_SIZE_512KB (0 << 1)
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#define AGP_I810_PGTBL_SIZE_256KB (1 << 1)
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#define AGP_I810_PGTBL_SIZE_128KB (2 << 1)
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2000-07-12 10:13:07 +00:00
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#define AGP_I810_DRT 0x3000
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#define AGP_I810_DRT_UNPOPULATED 0x00
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#define AGP_I810_DRT_POPULATED 0x01
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#define AGP_I810_GTT 0x10000
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2007-07-13 16:28:12 +00:00
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2002-09-12 04:23:18 +00:00
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/*
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* Config registers for i830MG device 0
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*/
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#define AGP_I830_GCC1 0x52
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#define AGP_I830_GCC1_DEV2 0x08
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#define AGP_I830_GCC1_DEV2_ENABLED 0x00
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#define AGP_I830_GCC1_DEV2_DISABLED 0x08
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2007-07-13 16:28:12 +00:00
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#define AGP_I830_GCC1_GMS 0xf0 /* Top bit reserved pre-G33 */
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2002-09-12 04:23:18 +00:00
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#define AGP_I830_GCC1_GMS_STOLEN_512 0x20
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#define AGP_I830_GCC1_GMS_STOLEN_1024 0x30
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#define AGP_I830_GCC1_GMS_STOLEN_8192 0x40
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#define AGP_I830_GCC1_GMASIZE 0x01
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#define AGP_I830_GCC1_GMASIZE_64 0x01
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#define AGP_I830_GCC1_GMASIZE_128 0x00
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2000-06-09 16:04:30 +00:00
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2003-02-13 19:24:19 +00:00
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/*
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* Config registers for 852GM/855GM/865G device 0
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*/
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#define AGP_I855_GCC1 0x52
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#define AGP_I855_GCC1_DEV2 0x08
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#define AGP_I855_GCC1_DEV2_ENABLED 0x00
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#define AGP_I855_GCC1_DEV2_DISABLED 0x08
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#define AGP_I855_GCC1_GMS 0x70
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#define AGP_I855_GCC1_GMS_STOLEN_0M 0x00
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#define AGP_I855_GCC1_GMS_STOLEN_1M 0x10
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#define AGP_I855_GCC1_GMS_STOLEN_4M 0x20
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#define AGP_I855_GCC1_GMS_STOLEN_8M 0x30
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#define AGP_I855_GCC1_GMS_STOLEN_16M 0x40
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#define AGP_I855_GCC1_GMS_STOLEN_32M 0x50
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/*
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* 852GM/855GM variant identification
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*/
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#define AGP_I85X_CAPID 0x44
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#define AGP_I85X_VARIANT_MASK 0x7
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#define AGP_I85X_VARIANT_SHIFT 5
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#define AGP_I855_GME 0x0
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#define AGP_I855_GM 0x4
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#define AGP_I852_GME 0x2
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#define AGP_I852_GM 0x5
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2005-12-02 23:51:36 +00:00
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/*
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* 915G registers
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*/
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#define AGP_I915_GMADR 0x18
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#define AGP_I915_MMADR 0x10
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#define AGP_I915_GTTADR 0x1C
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#define AGP_I915_GCC1_GMS_STOLEN_48M 0x60
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#define AGP_I915_GCC1_GMS_STOLEN_64M 0x70
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#define AGP_I915_DEVEN 0x54
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#define AGP_I915_DEVEN_D2F0 0x08
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#define AGP_I915_DEVEN_D2F0_ENABLED 0x08
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#define AGP_I915_DEVEN_D2F0_DISABLED 0x00
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#define AGP_I915_MSAC 0x62
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#define AGP_I915_MSAC_GMASIZE 0x02
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#define AGP_I915_MSAC_GMASIZE_128 0x02
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#define AGP_I915_MSAC_GMASIZE_256 0x00
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2007-07-13 16:28:12 +00:00
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/*
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* G965 registers
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*/
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#define AGP_I965_GTTMMADR 0x10
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#define AGP_I965_MSAC 0x62
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#define AGP_I965_MSAC_GMASIZE_128 0x00
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#define AGP_I965_MSAC_GMASIZE_256 0x02
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#define AGP_I965_MSAC_GMASIZE_512 0x06
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/*
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* G33 registers
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*/
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#define AGP_G33_GCC1_GMS_STOLEN_128M 0x80
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#define AGP_G33_GCC1_GMS_STOLEN_256M 0x90
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2003-08-23 18:00:31 +00:00
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/*
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* NVIDIA nForce/nForce2 registers
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*/
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#define AGP_NVIDIA_0_APBASE 0x10
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#define AGP_NVIDIA_0_APSIZE 0x80
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#define AGP_NVIDIA_1_WBC 0xf0
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#define AGP_NVIDIA_2_GARTCTRL 0xd0
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#define AGP_NVIDIA_2_APBASE 0xd8
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#define AGP_NVIDIA_2_APLIMIT 0xdc
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#define AGP_NVIDIA_2_ATTBASE(i) (0xe0 + (i) * 4)
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#define AGP_NVIDIA_3_APBASE 0x50
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#define AGP_NVIDIA_3_APLIMIT 0x54
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2004-08-16 12:25:48 +00:00
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/*
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* AMD64 GART registers
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*/
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#define AGP_AMD64_APCTRL 0x90
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#define AGP_AMD64_APBASE 0x94
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#define AGP_AMD64_ATTBASE 0x98
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#define AGP_AMD64_CACHECTRL 0x9c
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#define AGP_AMD64_APCTRL_GARTEN 0x00000001
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#define AGP_AMD64_APCTRL_SIZE_MASK 0x0000000e
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#define AGP_AMD64_APCTRL_DISGARTCPU 0x00000010
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#define AGP_AMD64_APCTRL_DISGARTIO 0x00000020
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#define AGP_AMD64_APCTRL_DISWLKPRB 0x00000040
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#define AGP_AMD64_APBASE_MASK 0x00007fff
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#define AGP_AMD64_ATTBASE_MASK 0xfffffff0
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#define AGP_AMD64_CACHECTRL_INVGART 0x00000001
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#define AGP_AMD64_CACHECTRL_PTEERR 0x00000002
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2005-09-27 20:57:50 +00:00
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/*
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* NVIDIA nForce3 registers
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*/
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#define AGP_AMD64_NVIDIA_0_APBASE 0x10
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#define AGP_AMD64_NVIDIA_1_APBASE1 0x50
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#define AGP_AMD64_NVIDIA_1_APLIMIT1 0x54
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#define AGP_AMD64_NVIDIA_1_APSIZE 0xa8
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#define AGP_AMD64_NVIDIA_1_APBASE2 0xd8
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#define AGP_AMD64_NVIDIA_1_APLIMIT2 0xdc
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/*
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* ULi M1689 registers
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*/
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#define AGP_AMD64_ULI_APBASE 0x10
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#define AGP_AMD64_ULI_HTT_FEATURE 0x50
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#define AGP_AMD64_ULI_ENU_SCR 0x54
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2005-09-17 03:36:47 +00:00
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/*
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* ATI IGP registers
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*/
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#define ATI_GART_MMADDR 0x14
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#define ATI_RS100_APSIZE 0xac
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#define ATI_RS100_IG_AGPMODE 0xb0
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#define ATI_RS300_APSIZE 0xf8
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#define ATI_RS300_IG_AGPMODE 0xfc
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#define ATI_GART_FEATURE_ID 0x00
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#define ATI_GART_BASE 0x04
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#define ATI_GART_CACHE_CNTRL 0x0c
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2000-06-09 16:04:30 +00:00
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#endif /* !_PCI_AGPREG_H_ */
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