2002-08-26 15:57:08 +00:00
|
|
|
/*-
|
|
|
|
* Copyright (c) 1994,1995 Stefan Esser, Wolfgang StanglMeier
|
|
|
|
* Copyright (c) 2000 Michael Smith <msmith@freebsd.org>
|
|
|
|
* Copyright (c) 2000 BSDi
|
|
|
|
* All rights reserved.
|
|
|
|
*
|
|
|
|
* Redistribution and use in source and binary forms, with or without
|
|
|
|
* modification, are permitted provided that the following conditions
|
|
|
|
* are met:
|
|
|
|
* 1. Redistributions of source code must retain the above copyright
|
|
|
|
* notice, this list of conditions and the following disclaimer.
|
|
|
|
* 2. Redistributions in binary form must reproduce the above copyright
|
|
|
|
* notice, this list of conditions and the following disclaimer in the
|
|
|
|
* documentation and/or other materials provided with the distribution.
|
|
|
|
* 3. The name of the author may not be used to endorse or promote products
|
|
|
|
* derived from this software without specific prior written permission.
|
|
|
|
*
|
|
|
|
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
|
|
|
|
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
|
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
|
|
|
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
|
|
|
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
|
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
|
|
|
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
|
|
|
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
|
|
|
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
|
|
|
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
|
|
|
* SUCH DAMAGE.
|
|
|
|
*
|
|
|
|
* $FreeBSD$
|
|
|
|
*/
|
|
|
|
|
|
|
|
#ifndef __PCIB_PRIVATE_H__
|
|
|
|
#define __PCIB_PRIVATE_H__
|
|
|
|
|
2011-07-15 21:08:58 +00:00
|
|
|
#ifdef NEW_PCIB
|
|
|
|
/*
|
|
|
|
* Data structure and routines that Host to PCI bridge drivers can use
|
|
|
|
* to restrict allocations for child devices to ranges decoded by the
|
|
|
|
* bridge.
|
|
|
|
*/
|
|
|
|
struct pcib_host_resources {
|
|
|
|
device_t hr_pcib;
|
|
|
|
struct resource_list hr_rl;
|
|
|
|
};
|
|
|
|
|
|
|
|
int pcib_host_res_init(device_t pcib,
|
|
|
|
struct pcib_host_resources *hr);
|
|
|
|
int pcib_host_res_free(device_t pcib,
|
|
|
|
struct pcib_host_resources *hr);
|
|
|
|
int pcib_host_res_decodes(struct pcib_host_resources *hr, int type,
|
|
|
|
u_long start, u_long end, u_int flags);
|
|
|
|
struct resource *pcib_host_res_alloc(struct pcib_host_resources *hr,
|
|
|
|
device_t dev, int type, int *rid, u_long start, u_long end,
|
|
|
|
u_long count, u_int flags);
|
|
|
|
int pcib_host_res_adjust(struct pcib_host_resources *hr,
|
|
|
|
device_t dev, int type, struct resource *r, u_long start,
|
|
|
|
u_long end);
|
|
|
|
#endif
|
|
|
|
|
2002-08-26 15:57:08 +00:00
|
|
|
/*
|
|
|
|
* Export portions of generic PCI:PCI bridge support so that it can be
|
|
|
|
* used by subclasses.
|
|
|
|
*/
|
2010-08-05 16:10:12 +00:00
|
|
|
DECLARE_CLASS(pcib_driver);
|
2002-08-26 15:57:08 +00:00
|
|
|
|
2011-05-03 17:37:24 +00:00
|
|
|
#ifdef NEW_PCIB
|
|
|
|
#define WIN_IO 0x1
|
|
|
|
#define WIN_MEM 0x2
|
|
|
|
#define WIN_PMEM 0x4
|
|
|
|
|
|
|
|
struct pcib_window {
|
|
|
|
pci_addr_t base; /* base address */
|
|
|
|
pci_addr_t limit; /* topmost address */
|
|
|
|
struct rman rman;
|
2013-07-18 15:17:11 +00:00
|
|
|
struct resource **res;
|
|
|
|
int count; /* size of 'res' array */
|
2011-05-03 17:37:24 +00:00
|
|
|
int reg; /* resource id from parent */
|
|
|
|
int valid;
|
|
|
|
int mask; /* WIN_* bitmask of this window */
|
|
|
|
int step; /* log_2 of window granularity */
|
|
|
|
const char *name;
|
|
|
|
};
|
|
|
|
#endif
|
|
|
|
|
2002-08-26 15:57:08 +00:00
|
|
|
/*
|
|
|
|
* Bridge-specific data.
|
|
|
|
*/
|
|
|
|
struct pcib_softc
|
|
|
|
{
|
|
|
|
device_t dev;
|
2004-01-11 06:52:31 +00:00
|
|
|
uint32_t flags; /* flags */
|
2006-12-14 16:53:48 +00:00
|
|
|
#define PCIB_SUBTRACTIVE 0x1
|
2007-01-13 04:57:37 +00:00
|
|
|
#define PCIB_DISABLE_MSI 0x2
|
2013-07-09 23:12:26 +00:00
|
|
|
#define PCIB_DISABLE_MSIX 0x4
|
2003-08-22 03:11:53 +00:00
|
|
|
uint16_t command; /* command register */
|
Add some sysctl reporting for most pci_pci bridges. We now report
domain, pribus (the primary bus, eg the bus that this chip is on),
secbus (the secondary bus, eg the bus immediately behind this chip)
and subbus (the number of the highest bus behind this chip).
Normally, this information is reported via bootverbose parameters, but
that's hard to use for debugging in some cases.
This adds reading of pribus to make this happen. In addition, change
the narrow types to u_int to allow for easier reporting via sysctl for
domain, secbus and subbus. This should have no effect, but if it
does, please let me know.
2008-08-16 20:18:40 +00:00
|
|
|
u_int domain; /* domain number */
|
|
|
|
u_int pribus; /* primary bus number */
|
|
|
|
u_int secbus; /* secondary bus number */
|
|
|
|
u_int subbus; /* subordinate bus number */
|
2011-05-03 17:37:24 +00:00
|
|
|
#ifdef NEW_PCIB
|
|
|
|
struct pcib_window io; /* I/O port window */
|
|
|
|
struct pcib_window mem; /* memory window */
|
|
|
|
struct pcib_window pmem; /* prefetchable memory window */
|
|
|
|
#else
|
2002-08-26 15:57:08 +00:00
|
|
|
pci_addr_t pmembase; /* base address of prefetchable memory */
|
|
|
|
pci_addr_t pmemlimit; /* topmost address of prefetchable memory */
|
|
|
|
pci_addr_t membase; /* base address of memory window */
|
|
|
|
pci_addr_t memlimit; /* topmost address of memory window */
|
2003-08-22 03:11:53 +00:00
|
|
|
uint32_t iobase; /* base address of port window */
|
|
|
|
uint32_t iolimit; /* topmost address of port window */
|
2011-05-03 17:37:24 +00:00
|
|
|
#endif
|
2003-08-22 03:11:53 +00:00
|
|
|
uint16_t secstat; /* secondary bus status register */
|
|
|
|
uint16_t bridgectl; /* bridge control register */
|
|
|
|
uint8_t seclat; /* secondary bus latency timer */
|
2002-08-26 15:57:08 +00:00
|
|
|
};
|
|
|
|
|
2003-08-22 03:11:53 +00:00
|
|
|
typedef uint32_t pci_read_config_fn(int b, int s, int f, int reg, int width);
|
2002-11-22 17:50:47 +00:00
|
|
|
|
2011-07-15 21:08:58 +00:00
|
|
|
#ifdef NEW_PCIB
|
|
|
|
const char *pcib_child_name(device_t child);
|
|
|
|
#endif
|
2002-11-22 17:50:47 +00:00
|
|
|
int host_pcib_get_busno(pci_read_config_fn read_config, int bus,
|
2003-08-22 03:11:53 +00:00
|
|
|
int slot, int func, uint8_t *busnum);
|
2002-09-06 22:14:00 +00:00
|
|
|
int pcib_attach(device_t dev);
|
2002-08-26 15:57:08 +00:00
|
|
|
void pcib_attach_common(device_t dev);
|
|
|
|
int pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result);
|
|
|
|
int pcib_write_ivar(device_t dev, device_t child, int which, uintptr_t value);
|
|
|
|
struct resource *pcib_alloc_resource(device_t dev, device_t child, int type, int *rid,
|
|
|
|
u_long start, u_long end, u_long count, u_int flags);
|
2011-05-03 17:37:24 +00:00
|
|
|
#ifdef NEW_PCIB
|
|
|
|
int pcib_adjust_resource(device_t bus, device_t child, int type,
|
|
|
|
struct resource *r, u_long start, u_long end);
|
|
|
|
int pcib_release_resource(device_t dev, device_t child, int type, int rid,
|
|
|
|
struct resource *r);
|
|
|
|
#endif
|
2002-08-26 15:57:08 +00:00
|
|
|
int pcib_maxslots(device_t dev);
|
2009-03-14 14:08:53 +00:00
|
|
|
uint32_t pcib_read_config(device_t dev, u_int b, u_int s, u_int f, u_int reg, int width);
|
|
|
|
void pcib_write_config(device_t dev, u_int b, u_int s, u_int f, u_int reg, uint32_t val, int width);
|
2003-01-14 11:37:56 +00:00
|
|
|
int pcib_route_interrupt(device_t pcib, device_t dev, int pin);
|
First cut at MI support for PCI Message Signalled Interrupts (MSI):
- Add 3 new functions to the pci_if interface along with suitable wrappers
to provide the device driver visible API:
- pci_alloc_msi(dev, int *count) backed by PCI_ALLOC_MSI(). '*count'
here is an in and out parameter. The driver stores the desired number
of messages in '*count' before calling the function. On success,
'*count' holds the number of messages allocated to the device. Also on
success, the driver can access the messages as SYS_RES_IRQ resources
starting at rid 1. Note that the legacy INTx interrupt resource will
not be available when using MSI. Note that this function will allocate
either MSI or MSI-X messages depending on the devices capabilities and
the 'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables. Also note
that the driver should activate the memory resource that holds the
MSI-X table and pending bit array (PBA) before calling this function
if the device supports MSI-X.
- pci_release_msi(dev) backed by PCI_RELEASE_MSI(). This function
releases the messages allocated for this device. All of the
SYS_RES_IRQ resources need to be released for this function to succeed.
- pci_msi_count(dev) backed by PCI_MSI_COUNT(). This function returns
the maximum number of MSI or MSI-X messages supported by this device.
MSI-X is preferred if present, but this function will honor the
'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables. This function
should return the largest value that pci_alloc_msi() can return
(assuming the MD code is able to allocate sufficient backing resources
for all of the messages).
- Add default implementations for these 3 methods to the pci_driver generic
PCI bus driver. (The various other PCI bus drivers such as for ACPI and
OFW will inherit these default implementations.) This default
implementation depends on 4 new pcib_if methods that bubble up through
the PCI bridges to the MD code to allocate IRQ values and perform any
needed MD setup code needed:
- PCIB_ALLOC_MSI() attempts to allocate a group of MSI messages.
- PCIB_RELEASE_MSI() releases a group of MSI messages.
- PCIB_ALLOC_MSIX() attempts to allocate a single MSI-X message.
- PCIB_RELEASE_MSIX() releases a single MSI-X message.
- Add default implementations for these 4 methods that just pass the
request up to the parent bus's parent bridge driver and use the
default implementation in the various MI PCI bridge drivers.
- Add MI functions for use by MD code when managing MSI and MSI-X
interrupts:
- pci_enable_msi(dev, address, data) programs the MSI capability address
and data registers for a group of MSI messages
- pci_enable_msix(dev, index, address, data) initializes a single MSI-X
message in the MSI-X table
- pci_mask_msix(dev, index) masks a single MSI-X message
- pci_unmask_msix(dev, index) unmasks a single MSI-X message
- pci_pending_msix(dev, index) returns true if the specified MSI-X
message is currently pending
- Save the MSI capability address and data registers in the pci_cfgreg
block in a PCI devices ivars and restore the values when a device is
resumed. Note that the MSI-X table is not currently restored during
resume.
- Add constants for MSI-X register offsets and fields.
- Record interesting data about any MSI-X capability blocks we come
across in the pci_cfgreg block in the ivars for PCI devices.
Tested on: em (i386, MSI), bce (amd64/i386, MSI), mpt (amd64, MSI-X)
Reviewed by: scottl, grehan, jfv
MFC after: 2 months
2006-11-13 21:47:30 +00:00
|
|
|
int pcib_alloc_msi(device_t pcib, device_t dev, int count, int maxcount, int *irqs);
|
|
|
|
int pcib_release_msi(device_t pcib, device_t dev, int count, int *irqs);
|
2007-05-02 17:50:36 +00:00
|
|
|
int pcib_alloc_msix(device_t pcib, device_t dev, int *irq);
|
First cut at MI support for PCI Message Signalled Interrupts (MSI):
- Add 3 new functions to the pci_if interface along with suitable wrappers
to provide the device driver visible API:
- pci_alloc_msi(dev, int *count) backed by PCI_ALLOC_MSI(). '*count'
here is an in and out parameter. The driver stores the desired number
of messages in '*count' before calling the function. On success,
'*count' holds the number of messages allocated to the device. Also on
success, the driver can access the messages as SYS_RES_IRQ resources
starting at rid 1. Note that the legacy INTx interrupt resource will
not be available when using MSI. Note that this function will allocate
either MSI or MSI-X messages depending on the devices capabilities and
the 'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables. Also note
that the driver should activate the memory resource that holds the
MSI-X table and pending bit array (PBA) before calling this function
if the device supports MSI-X.
- pci_release_msi(dev) backed by PCI_RELEASE_MSI(). This function
releases the messages allocated for this device. All of the
SYS_RES_IRQ resources need to be released for this function to succeed.
- pci_msi_count(dev) backed by PCI_MSI_COUNT(). This function returns
the maximum number of MSI or MSI-X messages supported by this device.
MSI-X is preferred if present, but this function will honor the
'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables. This function
should return the largest value that pci_alloc_msi() can return
(assuming the MD code is able to allocate sufficient backing resources
for all of the messages).
- Add default implementations for these 3 methods to the pci_driver generic
PCI bus driver. (The various other PCI bus drivers such as for ACPI and
OFW will inherit these default implementations.) This default
implementation depends on 4 new pcib_if methods that bubble up through
the PCI bridges to the MD code to allocate IRQ values and perform any
needed MD setup code needed:
- PCIB_ALLOC_MSI() attempts to allocate a group of MSI messages.
- PCIB_RELEASE_MSI() releases a group of MSI messages.
- PCIB_ALLOC_MSIX() attempts to allocate a single MSI-X message.
- PCIB_RELEASE_MSIX() releases a single MSI-X message.
- Add default implementations for these 4 methods that just pass the
request up to the parent bus's parent bridge driver and use the
default implementation in the various MI PCI bridge drivers.
- Add MI functions for use by MD code when managing MSI and MSI-X
interrupts:
- pci_enable_msi(dev, address, data) programs the MSI capability address
and data registers for a group of MSI messages
- pci_enable_msix(dev, index, address, data) initializes a single MSI-X
message in the MSI-X table
- pci_mask_msix(dev, index) masks a single MSI-X message
- pci_unmask_msix(dev, index) unmasks a single MSI-X message
- pci_pending_msix(dev, index) returns true if the specified MSI-X
message is currently pending
- Save the MSI capability address and data registers in the pci_cfgreg
block in a PCI devices ivars and restore the values when a device is
resumed. Note that the MSI-X table is not currently restored during
resume.
- Add constants for MSI-X register offsets and fields.
- Record interesting data about any MSI-X capability blocks we come
across in the pci_cfgreg block in the ivars for PCI devices.
Tested on: em (i386, MSI), bce (amd64/i386, MSI), mpt (amd64, MSI-X)
Reviewed by: scottl, grehan, jfv
MFC after: 2 months
2006-11-13 21:47:30 +00:00
|
|
|
int pcib_release_msix(device_t pcib, device_t dev, int irq);
|
2007-05-02 17:50:36 +00:00
|
|
|
int pcib_map_msi(device_t pcib, device_t dev, int irq, uint64_t *addr, uint32_t *data);
|
2002-08-26 15:57:08 +00:00
|
|
|
|
|
|
|
#endif
|