Prefer the uintXX_t to the u_intXX_t names.
This commit is contained in:
Warner Losh
parent
d586a2745c
commit
b0cb115fb7
@ -60,7 +60,7 @@
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#include "pcib_if.h"
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#include "pci_if.h"
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static u_int32_t pci_mapbase(unsigned mapreg);
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static uint32_t pci_mapbase(unsigned mapreg);
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static int pci_maptype(unsigned mapreg);
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static int pci_mapsize(unsigned testval);
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static int pci_maprange(unsigned mapreg);
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@ -140,7 +140,7 @@ static size_t pci_vendordata_size;
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struct pci_quirk {
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u_int32_t devid; /* Vendor/device of the card */
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uint32_t devid; /* Vendor/device of the card */
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int type;
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#define PCI_QUIRK_MAP_REG 1 /* PCI map register in weird place */
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int arg1;
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@ -163,8 +163,8 @@ struct pci_quirk pci_quirks[] = {
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#define PCI_MAPPORT 0x04 /* port map */
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struct devlist pci_devq;
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u_int32_t pci_generation;
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u_int32_t pci_numdevs = 0;
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uint32_t pci_generation;
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uint32_t pci_numdevs = 0;
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/* sysctl vars */
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SYSCTL_NODE(_hw, OID_AUTO, pci, CTLFLAG_RD, 0, "PCI bus tuning parameters");
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@ -180,7 +180,7 @@ are some peripherals that this causes problems with.");
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/* Find a device_t by bus/slot/function */
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device_t
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pci_find_bsf(u_int8_t bus, u_int8_t slot, u_int8_t func)
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pci_find_bsf(uint8_t bus, uint8_t slot, uint8_t func)
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{
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struct pci_devinfo *dinfo;
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@ -198,7 +198,7 @@ pci_find_bsf(u_int8_t bus, u_int8_t slot, u_int8_t func)
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/* Find a device_t by vendor/device ID */
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device_t
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pci_find_device(u_int16_t vendor, u_int16_t device)
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pci_find_device(uint16_t vendor, uint16_t device)
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{
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struct pci_devinfo *dinfo;
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@ -214,7 +214,7 @@ pci_find_device(u_int16_t vendor, u_int16_t device)
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/* return base address of memory or port map */
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static u_int32_t
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static uint32_t
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pci_mapbase(unsigned mapreg)
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{
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int mask = 0x03;
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@ -228,7 +228,7 @@ pci_mapbase(unsigned mapreg)
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static int
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pci_maptype(unsigned mapreg)
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{
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static u_int8_t maptype[0x10] = {
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static uint8_t maptype[0x10] = {
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PCI_MAPMEM, PCI_MAPPORT,
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PCI_MAPMEM, 0,
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PCI_MAPMEM, PCI_MAPPORT,
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@ -474,7 +474,7 @@ pci_set_powerstate_method(device_t dev, device_t child, int state)
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{
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struct pci_devinfo *dinfo = device_get_ivars(child);
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pcicfgregs *cfg = &dinfo->cfg;
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u_int16_t status;
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uint16_t status;
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int result;
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if (cfg->pp_cap != 0) {
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@ -517,7 +517,7 @@ pci_get_powerstate_method(device_t dev, device_t child)
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{
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struct pci_devinfo *dinfo = device_get_ivars(child);
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pcicfgregs *cfg = &dinfo->cfg;
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u_int16_t status;
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uint16_t status;
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int result;
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if (cfg->pp_cap != 0) {
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@ -551,9 +551,9 @@ pci_get_powerstate_method(device_t dev, device_t child)
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*/
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static __inline void
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pci_set_command_bit(device_t dev, device_t child, u_int16_t bit)
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pci_set_command_bit(device_t dev, device_t child, uint16_t bit)
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{
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u_int16_t command;
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uint16_t command;
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command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
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command |= bit;
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@ -561,9 +561,9 @@ pci_set_command_bit(device_t dev, device_t child, u_int16_t bit)
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}
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static __inline void
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pci_clear_command_bit(device_t dev, device_t child, u_int16_t bit)
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pci_clear_command_bit(device_t dev, device_t child, uint16_t bit)
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{
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u_int16_t command;
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uint16_t command;
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command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
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command &= ~bit;
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@ -587,8 +587,8 @@ pci_disable_busmaster_method(device_t dev, device_t child)
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int
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pci_enable_io_method(device_t dev, device_t child, int space)
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{
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u_int16_t command;
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u_int16_t bit;
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uint16_t command;
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uint16_t bit;
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char *error;
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bit = 0;
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@ -617,8 +617,8 @@ pci_enable_io_method(device_t dev, device_t child, int space)
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int
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pci_disable_io_method(device_t dev, device_t child, int space)
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{
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u_int16_t command;
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u_int16_t bit;
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uint16_t command;
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uint16_t bit;
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char *error;
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bit = 0;
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@ -672,7 +672,7 @@ pci_print_verbose(struct pci_devinfo *dinfo)
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printf("\tintpin=%c, irq=%d\n",
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cfg->intpin +'a' -1, cfg->intline);
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if (cfg->pp_cap) {
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u_int16_t status;
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uint16_t status;
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status = pci_read_config(cfg->dev, cfg->pp_status, 2);
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printf("\tpowerspec %d supports D0%s%s D3 current D%d\n",
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@ -706,12 +706,12 @@ static int
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pci_add_map(device_t pcib, int b, int s, int f, int reg,
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struct resource_list *rl)
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{
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u_int32_t map;
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u_int64_t base;
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u_int8_t ln2size;
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u_int8_t ln2range;
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u_int32_t testval;
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u_int16_t cmd;
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uint32_t map;
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uint64_t base;
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uint8_t ln2size;
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uint8_t ln2range;
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uint32_t testval;
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uint16_t cmd;
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int type;
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map = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4);
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@ -732,7 +732,7 @@ pci_add_map(device_t pcib, int b, int s, int f, int reg,
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ln2range = pci_maprange(testval);
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if (ln2range == 64) {
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/* Read the other half of a 64bit map register */
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base |= (u_int64_t) PCIB_READ_CONFIG(pcib, b, s, f, reg + 4, 4) << 32;
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base |= (uint64_t) PCIB_READ_CONFIG(pcib, b, s, f, reg + 4, 4) << 32;
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}
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if (bootverbose) {
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@ -826,7 +826,7 @@ pci_add_children(device_t dev, int busno, size_t dinfo_size)
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struct pci_devinfo *dinfo;
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int maxslots;
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int s, f, pcifunchigh;
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u_int8_t hdrtype;
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uint8_t hdrtype;
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KASSERT(dinfo_size >= sizeof(struct pci_devinfo),
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("dinfo_size too small"));
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@ -1176,7 +1176,7 @@ pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
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* The generic accessor doesn't deal with failure, so
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* we set the return value, then return an error.
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*/
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*((u_int8_t **) result) = NULL;
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*((uint8_t **) result) = NULL;
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return (EINVAL);
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case PCI_IVAR_SUBVENDOR:
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*result = cfg->subvendor;
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@ -1406,7 +1406,7 @@ pci_get_resource_list (device_t dev, device_t child)
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return (rl);
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}
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u_int32_t
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uint32_t
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pci_read_config_method(device_t dev, device_t child, int reg, int width)
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{
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struct pci_devinfo *dinfo = device_get_ivars(child);
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@ -1418,7 +1418,7 @@ pci_read_config_method(device_t dev, device_t child, int reg, int width)
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void
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pci_write_config_method(device_t dev, device_t child, int reg,
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u_int32_t val, int width)
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uint32_t val, int width)
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{
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struct pci_devinfo *dinfo = device_get_ivars(child);
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pcicfgregs *cfg = &dinfo->cfg;
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@ -120,7 +120,7 @@ void
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pcib_attach_common(device_t dev)
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{
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struct pcib_softc *sc;
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u_int8_t iolow;
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uint8_t iolow;
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sc = device_get_softc(dev);
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sc->dev = dev;
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@ -174,7 +174,7 @@ pcib_attach_common(device_t dev)
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switch (pci_get_devid(dev)) {
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case 0x12258086: /* Intel 82454KX/GX (Orion) */
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{
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u_int8_t supbus;
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uint8_t supbus;
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supbus = pci_read_config(dev, 0x41, 1);
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if (supbus != 0xff) {
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@ -462,14 +462,14 @@ pcib_maxslots(device_t dev)
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/*
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* Since we are a child of a PCI bus, its parent must support the pcib interface.
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*/
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u_int32_t
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uint32_t
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pcib_read_config(device_t dev, int b, int s, int f, int reg, int width)
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{
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return(PCIB_READ_CONFIG(device_get_parent(device_get_parent(dev)), b, s, f, reg, width));
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}
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void
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pcib_write_config(device_t dev, int b, int s, int f, int reg, u_int32_t val, int width)
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pcib_write_config(device_t dev, int b, int s, int f, int reg, uint32_t val, int width)
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{
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PCIB_WRITE_CONFIG(device_get_parent(device_get_parent(dev)), b, s, f, reg, val, width);
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}
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@ -516,9 +516,9 @@ pcib_route_interrupt(device_t pcib, device_t dev, int pin)
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*/
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int
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host_pcib_get_busno(pci_read_config_fn read_config, int bus, int slot, int func,
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u_int8_t *busnum)
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uint8_t *busnum)
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{
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u_int32_t id;
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uint32_t id;
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id = read_config(bus, slot, func, PCIR_DEVVENDOR, 4);
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if (id == 0xffffffff)
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@ -50,10 +50,10 @@ int pci_write_ivar(device_t dev, device_t child, int which,
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int pci_set_powerstate_method(device_t dev, device_t child,
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int state);
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int pci_get_powerstate_method(device_t dev, device_t child);
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u_int32_t pci_read_config_method(device_t dev, device_t child,
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uint32_t pci_read_config_method(device_t dev, device_t child,
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int reg, int width);
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void pci_write_config_method(device_t dev, device_t child,
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int reg, u_int32_t val, int width);
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int reg, uint32_t val, int width);
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int pci_enable_busmaster_method(device_t dev, device_t child);
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int pci_disable_busmaster_method(device_t dev, device_t child);
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int pci_enable_io_method(device_t dev, device_t child, int space);
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@ -44,24 +44,24 @@
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struct pcib_softc
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{
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device_t dev;
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u_int16_t command; /* command register */
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u_int8_t secbus; /* secondary bus number */
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u_int8_t subbus; /* subordinate bus number */
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uint16_t command; /* command register */
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uint8_t secbus; /* secondary bus number */
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uint8_t subbus; /* subordinate bus number */
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pci_addr_t pmembase; /* base address of prefetchable memory */
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pci_addr_t pmemlimit; /* topmost address of prefetchable memory */
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pci_addr_t membase; /* base address of memory window */
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pci_addr_t memlimit; /* topmost address of memory window */
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u_int32_t iobase; /* base address of port window */
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u_int32_t iolimit; /* topmost address of port window */
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u_int16_t secstat; /* secondary bus status register */
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u_int16_t bridgectl; /* bridge control register */
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u_int8_t seclat; /* secondary bus latency timer */
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uint32_t iobase; /* base address of port window */
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uint32_t iolimit; /* topmost address of port window */
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uint16_t secstat; /* secondary bus status register */
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uint16_t bridgectl; /* bridge control register */
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uint8_t seclat; /* secondary bus latency timer */
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};
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typedef u_int32_t pci_read_config_fn(int b, int s, int f, int reg, int width);
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typedef uint32_t pci_read_config_fn(int b, int s, int f, int reg, int width);
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int host_pcib_get_busno(pci_read_config_fn read_config, int bus,
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int slot, int func, u_int8_t *busnum);
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int slot, int func, uint8_t *busnum);
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int pcib_attach(device_t dev);
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void pcib_attach_common(device_t dev);
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int pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result);
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@ -69,8 +69,8 @@ int pcib_write_ivar(device_t dev, device_t child, int which, uintptr_t value);
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struct resource *pcib_alloc_resource(device_t dev, device_t child, int type, int *rid,
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u_long start, u_long end, u_long count, u_int flags);
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int pcib_maxslots(device_t dev);
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u_int32_t pcib_read_config(device_t dev, int b, int s, int f, int reg, int width);
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void pcib_write_config(device_t dev, int b, int s, int f, int reg, u_int32_t val, int width);
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uint32_t pcib_read_config(device_t dev, int b, int s, int f, int reg, int width);
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void pcib_write_config(device_t dev, int b, int s, int f, int reg, uint32_t val, int width);
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int pcib_route_interrupt(device_t pcib, device_t dev, int pin);
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extern devclass_t pcib_devclass;
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@ -46,9 +46,9 @@
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/* pci_addr_t covers this system's PCI bus address space: 32 or 64 bit */
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#ifdef PCI_A64
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typedef u_int64_t pci_addr_t; /* u_int64_t for system with 64bit addresses */
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typedef uint64_t pci_addr_t; /* uint64_t for system with 64bit addresses */
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#else
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typedef u_int32_t pci_addr_t; /* u_int64_t for system with 64bit addresses */
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typedef uint32_t pci_addr_t; /* uint64_t for system with 64bit addresses */
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#endif
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/* config header information common to all header types */
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@ -56,39 +56,39 @@ typedef u_int32_t pci_addr_t; /* u_int64_t for system with 64bit addresses */
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typedef struct pcicfg {
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struct device *dev; /* device which owns this */
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u_int16_t subvendor; /* card vendor ID */
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u_int16_t subdevice; /* card device ID, assigned by card vendor */
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u_int16_t vendor; /* chip vendor ID */
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u_int16_t device; /* chip device ID, assigned by chip vendor */
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uint16_t subvendor; /* card vendor ID */
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uint16_t subdevice; /* card device ID, assigned by card vendor */
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uint16_t vendor; /* chip vendor ID */
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uint16_t device; /* chip device ID, assigned by chip vendor */
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u_int16_t cmdreg; /* disable/enable chip and PCI options */
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u_int16_t statreg; /* supported PCI features and error state */
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uint16_t cmdreg; /* disable/enable chip and PCI options */
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uint16_t statreg; /* supported PCI features and error state */
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u_int8_t baseclass; /* chip PCI class */
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u_int8_t subclass; /* chip PCI subclass */
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u_int8_t progif; /* chip PCI programming interface */
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u_int8_t revid; /* chip revision ID */
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uint8_t baseclass; /* chip PCI class */
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uint8_t subclass; /* chip PCI subclass */
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uint8_t progif; /* chip PCI programming interface */
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uint8_t revid; /* chip revision ID */
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u_int8_t hdrtype; /* chip config header type */
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u_int8_t cachelnsz; /* cache line size in 4byte units */
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u_int8_t intpin; /* PCI interrupt pin */
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u_int8_t intline; /* interrupt line (IRQ for PC arch) */
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uint8_t hdrtype; /* chip config header type */
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uint8_t cachelnsz; /* cache line size in 4byte units */
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uint8_t intpin; /* PCI interrupt pin */
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uint8_t intline; /* interrupt line (IRQ for PC arch) */
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u_int8_t mingnt; /* min. useful bus grant time in 250ns units */
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u_int8_t maxlat; /* max. tolerated bus grant latency in 250ns */
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u_int8_t lattimer; /* latency timer in units of 30ns bus cycles */
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uint8_t mingnt; /* min. useful bus grant time in 250ns units */
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uint8_t maxlat; /* max. tolerated bus grant latency in 250ns */
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uint8_t lattimer; /* latency timer in units of 30ns bus cycles */
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u_int8_t mfdev; /* multi-function device (from hdrtype reg) */
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u_int8_t nummaps; /* actual number of PCI maps used */
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uint8_t mfdev; /* multi-function device (from hdrtype reg) */
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uint8_t nummaps; /* actual number of PCI maps used */
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u_int8_t bus; /* config space bus address */
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u_int8_t slot; /* config space slot address */
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u_int8_t func; /* config space function number */
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uint8_t bus; /* config space bus address */
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uint8_t slot; /* config space slot address */
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uint8_t func; /* config space function number */
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u_int16_t pp_cap; /* PCI power management capabilities */
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u_int8_t pp_status; /* config space address of PCI power status reg */
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u_int8_t pp_pmcsr; /* config space address of PMCSR reg */
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u_int8_t pp_data; /* config space address of PCI power data reg */
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uint16_t pp_cap; /* PCI power management capabilities */
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uint8_t pp_status; /* config space address of PCI power status reg */
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uint8_t pp_pmcsr; /* config space address of PMCSR reg */
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uint8_t pp_data; /* config space address of PCI power data reg */
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} pcicfgregs;
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|
||||
@ -108,33 +108,33 @@ typedef struct pcicfg {
|
||||
typedef struct {
|
||||
pci_addr_t pmembase; /* base address of prefetchable memory */
|
||||
pci_addr_t pmemlimit; /* topmost address of prefetchable memory */
|
||||
u_int32_t membase; /* base address of memory window */
|
||||
u_int32_t memlimit; /* topmost address of memory window */
|
||||
u_int32_t iobase; /* base address of port window */
|
||||
u_int32_t iolimit; /* topmost address of port window */
|
||||
u_int16_t secstat; /* secondary bus status register */
|
||||
u_int16_t bridgectl; /* bridge control register */
|
||||
u_int8_t seclat; /* CardBus latency timer */
|
||||
uint32_t membase; /* base address of memory window */
|
||||
uint32_t memlimit; /* topmost address of memory window */
|
||||
uint32_t iobase; /* base address of port window */
|
||||
uint32_t iolimit; /* topmost address of port window */
|
||||
uint16_t secstat; /* secondary bus status register */
|
||||
uint16_t bridgectl; /* bridge control register */
|
||||
uint8_t seclat; /* CardBus latency timer */
|
||||
} pcih1cfgregs;
|
||||
|
||||
/* additional type 2 device config header information (CardBus bridge) */
|
||||
|
||||
typedef struct {
|
||||
u_int32_t membase0; /* base address of memory window */
|
||||
u_int32_t memlimit0; /* topmost address of memory window */
|
||||
u_int32_t membase1; /* base address of memory window */
|
||||
u_int32_t memlimit1; /* topmost address of memory window */
|
||||
u_int32_t iobase0; /* base address of port window */
|
||||
u_int32_t iolimit0; /* topmost address of port window */
|
||||
u_int32_t iobase1; /* base address of port window */
|
||||
u_int32_t iolimit1; /* topmost address of port window */
|
||||
u_int32_t pccardif; /* PC Card 16bit IF legacy more base addr. */
|
||||
u_int16_t secstat; /* secondary bus status register */
|
||||
u_int16_t bridgectl; /* bridge control register */
|
||||
u_int8_t seclat; /* CardBus latency timer */
|
||||
uint32_t membase0; /* base address of memory window */
|
||||
uint32_t memlimit0; /* topmost address of memory window */
|
||||
uint32_t membase1; /* base address of memory window */
|
||||
uint32_t memlimit1; /* topmost address of memory window */
|
||||
uint32_t iobase0; /* base address of port window */
|
||||
uint32_t iolimit0; /* topmost address of port window */
|
||||
uint32_t iobase1; /* base address of port window */
|
||||
uint32_t iolimit1; /* topmost address of port window */
|
||||
uint32_t pccardif; /* PC Card 16bit IF legacy more base addr. */
|
||||
uint16_t secstat; /* secondary bus status register */
|
||||
uint16_t bridgectl; /* bridge control register */
|
||||
uint8_t seclat; /* CardBus latency timer */
|
||||
} pcih2cfgregs;
|
||||
|
||||
extern u_int32_t pci_numdevs;
|
||||
extern uint32_t pci_numdevs;
|
||||
|
||||
/* Only if the prerequisites are present */
|
||||
#if defined(_SYS_BUS_H_) && defined(_SYS_PCIIO_H_)
|
||||
@ -186,35 +186,35 @@ enum pci_device_ivars {
|
||||
#define PCI_ACCESSOR(var, ivar, type) \
|
||||
__BUS_ACCESSOR(pci, var, PCI, ivar, type)
|
||||
|
||||
PCI_ACCESSOR(subvendor, SUBVENDOR, u_int16_t)
|
||||
PCI_ACCESSOR(subdevice, SUBDEVICE, u_int16_t)
|
||||
PCI_ACCESSOR(vendor, VENDOR, u_int16_t)
|
||||
PCI_ACCESSOR(device, DEVICE, u_int16_t)
|
||||
PCI_ACCESSOR(devid, DEVID, u_int32_t)
|
||||
PCI_ACCESSOR(class, CLASS, u_int8_t)
|
||||
PCI_ACCESSOR(subclass, SUBCLASS, u_int8_t)
|
||||
PCI_ACCESSOR(progif, PROGIF, u_int8_t)
|
||||
PCI_ACCESSOR(revid, REVID, u_int8_t)
|
||||
PCI_ACCESSOR(intpin, INTPIN, u_int8_t)
|
||||
PCI_ACCESSOR(irq, IRQ, u_int8_t)
|
||||
PCI_ACCESSOR(bus, BUS, u_int8_t)
|
||||
PCI_ACCESSOR(slot, SLOT, u_int8_t)
|
||||
PCI_ACCESSOR(function, FUNCTION, u_int8_t)
|
||||
PCI_ACCESSOR(ether, ETHADDR, u_int8_t *)
|
||||
PCI_ACCESSOR(subvendor, SUBVENDOR, uint16_t)
|
||||
PCI_ACCESSOR(subdevice, SUBDEVICE, uint16_t)
|
||||
PCI_ACCESSOR(vendor, VENDOR, uint16_t)
|
||||
PCI_ACCESSOR(device, DEVICE, uint16_t)
|
||||
PCI_ACCESSOR(devid, DEVID, uint32_t)
|
||||
PCI_ACCESSOR(class, CLASS, uint8_t)
|
||||
PCI_ACCESSOR(subclass, SUBCLASS, uint8_t)
|
||||
PCI_ACCESSOR(progif, PROGIF, uint8_t)
|
||||
PCI_ACCESSOR(revid, REVID, uint8_t)
|
||||
PCI_ACCESSOR(intpin, INTPIN, uint8_t)
|
||||
PCI_ACCESSOR(irq, IRQ, uint8_t)
|
||||
PCI_ACCESSOR(bus, BUS, uint8_t)
|
||||
PCI_ACCESSOR(slot, SLOT, uint8_t)
|
||||
PCI_ACCESSOR(function, FUNCTION, uint8_t)
|
||||
PCI_ACCESSOR(ether, ETHADDR, uint8_t *)
|
||||
|
||||
#undef PCI_ACCESSOR
|
||||
|
||||
/*
|
||||
* Operations on configuration space.
|
||||
*/
|
||||
static __inline u_int32_t
|
||||
static __inline uint32_t
|
||||
pci_read_config(device_t dev, int reg, int width)
|
||||
{
|
||||
return PCI_READ_CONFIG(device_get_parent(dev), dev, reg, width);
|
||||
}
|
||||
|
||||
static __inline void
|
||||
pci_write_config(device_t dev, int reg, u_int32_t val, int width)
|
||||
pci_write_config(device_t dev, int reg, uint32_t val, int width)
|
||||
{
|
||||
PCI_WRITE_CONFIG(device_get_parent(dev), dev, reg, val, width);
|
||||
}
|
||||
@ -231,7 +231,7 @@ enum pcib_device_ivars {
|
||||
#define PCIB_ACCESSOR(var, ivar, type) \
|
||||
__BUS_ACCESSOR(pcib, var, PCIB, ivar, type)
|
||||
|
||||
PCIB_ACCESSOR(bus, BUS, u_int32_t)
|
||||
PCIB_ACCESSOR(bus, BUS, uint32_t)
|
||||
|
||||
#undef PCIB_ACCESSOR
|
||||
|
||||
@ -306,8 +306,8 @@ pci_get_powerstate(device_t dev)
|
||||
return PCI_GET_POWERSTATE(device_get_parent(dev), dev);
|
||||
}
|
||||
|
||||
device_t pci_find_bsf(u_int8_t, u_int8_t, u_int8_t);
|
||||
device_t pci_find_device(u_int16_t, u_int16_t);
|
||||
device_t pci_find_bsf(uint8_t, uint8_t, uint8_t);
|
||||
device_t pci_find_device(uint16_t, uint16_t);
|
||||
#endif /* _SYS_BUS_H_ */
|
||||
|
||||
/*
|
||||
@ -321,6 +321,6 @@ extern struct cdevsw pcicdev;
|
||||
STAILQ_HEAD(devlist, pci_devinfo);
|
||||
|
||||
extern struct devlist pci_devq;
|
||||
extern u_int32_t pci_generation;
|
||||
extern uint32_t pci_generation;
|
||||
|
||||
#endif /* _PCIVAR_H_ */
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user