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actually enable gate control for allwinner's r-ccu ir clock

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The gate control bit offset was correctly specified, but AW_CLK_HAS_GATE
flag was not set.
Tested with (C)IR receiver on Orange Pi PC Plus.

Reviewed by:	manu
MFC after:	1 week
This commit is contained in:
Andriy Gapon 2020-07-27 09:10:02 +00:00
parent 9af3bcd7c9
commit 062528c5f2
1 changed files with 1 additions and 1 deletions
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2
sys/arm/allwinner/clkng/ccu_sun8i_r.c
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@ -122,7 +122,7 @@ NM_CLK(r_ccu_ir_clk,
16, 2, 0, 0, /* M flags */ 16, 2, 0, 0, /* M flags */
24, 2, /* mux */ 24, 2, /* mux */
31, /* gate */ 31, /* gate */
AW_CLK_HAS_MUX | AW_CLK_REPARENT); /* flags */ AW_CLK_HAS_MUX | AW_CLK_REPARENT | AW_CLK_HAS_GATE);/* flags */
static const char *a83t_ir_parents[] = {"osc16M", "osc24M"}; static const char *a83t_ir_parents[] = {"osc16M", "osc24M"};
static struct aw_clk_nm_def a83t_ir_clk = { static struct aw_clk_nm_def a83t_ir_clk = {