Remove old CPU_ values from the arm cpufunc code. These have been removed.
This commit is contained in:
Andrew Turner
parent
96690e0dc4
commit
0faf121391
@ -61,10 +61,6 @@ __FBSDID("$FreeBSD$");
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#include <machine/cpufunc.h>
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#if defined(CPU_XSCALE_81342)
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#include <arm/xscale/i8134x/i81342reg.h>
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#endif
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/* PRIMARY CACHE VARIABLES */
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int arm_picache_size;
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int arm_picache_line_size;
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@ -84,57 +80,6 @@ u_int arm_cache_level;
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u_int arm_cache_type[14];
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u_int arm_cache_loc;
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#ifdef CPU_ARM9
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struct cpu_functions arm9_cpufuncs = {
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/* CPU functions */
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cpufunc_nullop, /* cpwait */
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/* MMU functions */
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cpufunc_control, /* control */
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arm9_setttb, /* Setttb */
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/* TLB functions */
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armv4_tlb_flushID, /* tlb_flushID */
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arm9_tlb_flushID_SE, /* tlb_flushID_SE */
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armv4_tlb_flushD, /* tlb_flushD */
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armv4_tlb_flushD_SE, /* tlb_flushD_SE */
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/* Cache operations */
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arm9_icache_sync_range, /* icache_sync_range */
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arm9_dcache_wbinv_all, /* dcache_wbinv_all */
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arm9_dcache_wbinv_range, /* dcache_wbinv_range */
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arm9_dcache_inv_range, /* dcache_inv_range */
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arm9_dcache_wb_range, /* dcache_wb_range */
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armv4_idcache_inv_all, /* idcache_inv_all */
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arm9_idcache_wbinv_all, /* idcache_wbinv_all */
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arm9_idcache_wbinv_range, /* idcache_wbinv_range */
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cpufunc_nullop, /* l2cache_wbinv_all */
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(void *)cpufunc_nullop, /* l2cache_wbinv_range */
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(void *)cpufunc_nullop, /* l2cache_inv_range */
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(void *)cpufunc_nullop, /* l2cache_wb_range */
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(void *)cpufunc_nullop, /* l2cache_drain_writebuf */
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/* Other functions */
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armv4_drain_writebuf, /* drain_writebuf */
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(void *)cpufunc_nullop, /* sleep */
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/* Soft functions */
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arm9_context_switch, /* context_switch */
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arm9_setup /* cpu setup */
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};
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#endif /* CPU_ARM9 */
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#if defined(CPU_ARM9E)
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struct cpu_functions armv5_ec_cpufuncs = {
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/* CPU functions */
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@ -254,160 +199,6 @@ struct cpu_functions pj4bv7_cpufuncs = {
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};
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#endif /* CPU_MV_PJ4B */
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#if defined(CPU_XSCALE_PXA2X0)
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struct cpu_functions xscale_cpufuncs = {
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/* CPU functions */
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xscale_cpwait, /* cpwait */
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/* MMU functions */
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xscale_control, /* control */
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xscale_setttb, /* setttb */
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/* TLB functions */
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armv4_tlb_flushID, /* tlb_flushID */
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xscale_tlb_flushID_SE, /* tlb_flushID_SE */
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armv4_tlb_flushD, /* tlb_flushD */
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armv4_tlb_flushD_SE, /* tlb_flushD_SE */
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/* Cache operations */
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xscale_cache_syncI_rng, /* icache_sync_range */
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xscale_cache_purgeD, /* dcache_wbinv_all */
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xscale_cache_purgeD_rng, /* dcache_wbinv_range */
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xscale_cache_flushD_rng, /* dcache_inv_range */
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xscale_cache_cleanD_rng, /* dcache_wb_range */
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xscale_cache_flushID, /* idcache_inv_all */
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xscale_cache_purgeID, /* idcache_wbinv_all */
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xscale_cache_purgeID_rng, /* idcache_wbinv_range */
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cpufunc_nullop, /* l2cache_wbinv_all */
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(void *)cpufunc_nullop, /* l2cache_wbinv_range */
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(void *)cpufunc_nullop, /* l2cache_inv_range */
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(void *)cpufunc_nullop, /* l2cache_wb_range */
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(void *)cpufunc_nullop, /* l2cache_drain_writebuf */
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/* Other functions */
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armv4_drain_writebuf, /* drain_writebuf */
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xscale_cpu_sleep, /* sleep */
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/* Soft functions */
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xscale_context_switch, /* context_switch */
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xscale_setup /* cpu setup */
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};
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#endif
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/* CPU_XSCALE_PXA2X0 */
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#ifdef CPU_XSCALE_81342
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struct cpu_functions xscalec3_cpufuncs = {
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/* CPU functions */
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xscale_cpwait, /* cpwait */
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/* MMU functions */
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xscale_control, /* control */
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xscalec3_setttb, /* setttb */
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/* TLB functions */
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armv4_tlb_flushID, /* tlb_flushID */
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xscale_tlb_flushID_SE, /* tlb_flushID_SE */
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armv4_tlb_flushD, /* tlb_flushD */
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armv4_tlb_flushD_SE, /* tlb_flushD_SE */
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/* Cache operations */
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xscalec3_cache_syncI_rng, /* icache_sync_range */
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xscalec3_cache_purgeD, /* dcache_wbinv_all */
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xscalec3_cache_purgeD_rng, /* dcache_wbinv_range */
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xscale_cache_flushD_rng, /* dcache_inv_range */
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xscalec3_cache_cleanD_rng, /* dcache_wb_range */
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xscale_cache_flushID, /* idcache_inv_all */
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xscalec3_cache_purgeID, /* idcache_wbinv_all */
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xscalec3_cache_purgeID_rng, /* idcache_wbinv_range */
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xscalec3_l2cache_purge, /* l2cache_wbinv_all */
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xscalec3_l2cache_purge_rng, /* l2cache_wbinv_range */
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xscalec3_l2cache_flush_rng, /* l2cache_inv_range */
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xscalec3_l2cache_clean_rng, /* l2cache_wb_range */
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(void *)cpufunc_nullop, /* l2cache_drain_writebuf */
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/* Other functions */
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armv4_drain_writebuf, /* drain_writebuf */
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xscale_cpu_sleep, /* sleep */
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/* Soft functions */
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xscalec3_context_switch, /* context_switch */
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xscale_setup /* cpu setup */
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};
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#endif /* CPU_XSCALE_81342 */
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#if defined(CPU_FA526)
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struct cpu_functions fa526_cpufuncs = {
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/* CPU functions */
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cpufunc_nullop, /* cpwait */
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/* MMU functions */
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cpufunc_control, /* control */
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fa526_setttb, /* setttb */
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/* TLB functions */
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armv4_tlb_flushID, /* tlb_flushID */
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fa526_tlb_flushID_SE, /* tlb_flushID_SE */
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armv4_tlb_flushD, /* tlb_flushD */
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armv4_tlb_flushD_SE, /* tlb_flushD_SE */
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/* Cache operations */
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fa526_icache_sync_range, /* icache_sync_range */
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fa526_dcache_wbinv_all, /* dcache_wbinv_all */
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fa526_dcache_wbinv_range, /* dcache_wbinv_range */
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fa526_dcache_inv_range, /* dcache_inv_range */
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fa526_dcache_wb_range, /* dcache_wb_range */
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armv4_idcache_inv_all, /* idcache_inv_all */
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fa526_idcache_wbinv_all, /* idcache_wbinv_all */
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fa526_idcache_wbinv_range, /* idcache_wbinv_range */
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cpufunc_nullop, /* l2cache_wbinv_all */
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(void *)cpufunc_nullop, /* l2cache_wbinv_range */
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(void *)cpufunc_nullop, /* l2cache_inv_range */
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(void *)cpufunc_nullop, /* l2cache_wb_range */
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(void *)cpufunc_nullop, /* l2cache_drain_writebuf */
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/* Other functions */
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armv4_drain_writebuf, /* drain_writebuf */
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fa526_cpu_sleep, /* sleep */
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/* Soft functions */
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fa526_context_switch, /* context_switch */
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fa526_setup /* cpu setup */
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};
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#endif /* CPU_FA526 */
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#if defined(CPU_ARM1176)
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struct cpu_functions arm1176_cpufuncs = {
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@ -459,12 +250,9 @@ u_int cputype;
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u_int cpu_reset_needs_v4_MMU_disable; /* flag used in locore-v4.s */
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#endif
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#if defined(CPU_ARM9) || \
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defined (CPU_ARM9E) || \
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#if defined (CPU_ARM9E) || \
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defined(CPU_ARM1176) || \
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defined(CPU_XSCALE_PXA2X0) || \
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defined(CPU_FA526) || defined(CPU_MV_PJ4B) || \
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defined(CPU_XSCALE_81342) || \
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defined(CPU_MV_PJ4B) || \
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defined(CPU_CORTEXA) || defined(CPU_KRAIT)
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/* Global cache line sizes, use 32 as default */
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@ -601,22 +389,6 @@ set_cpufuncs(void)
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cputype = cpu_ident();
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cputype &= CPU_ID_CPU_MASK;
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#ifdef CPU_ARM9
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if (((cputype & CPU_ID_IMPLEMENTOR_MASK) == CPU_ID_ARM_LTD ||
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(cputype & CPU_ID_IMPLEMENTOR_MASK) == CPU_ID_TI) &&
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(cputype & 0x0000f000) == 0x00009000) {
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cpufuncs = arm9_cpufuncs;
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cpu_reset_needs_v4_MMU_disable = 1; /* V4 or higher */
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get_cachetype_cp15();
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arm9_dcache_sets_inc = 1U << arm_dcache_l2_linesize;
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arm9_dcache_sets_max = (1U << (arm_dcache_l2_linesize +
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arm_dcache_l2_nsets)) - arm9_dcache_sets_inc;
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arm9_dcache_index_inc = 1U << (32 - arm_dcache_l2_assoc);
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arm9_dcache_index_max = 0U - arm9_dcache_index_inc;
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pmap_pte_init_generic();
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goto out;
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}
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#endif /* CPU_ARM9 */
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#if defined(CPU_ARM9E)
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if (cputype == CPU_ID_MV88FR131 || cputype == CPU_ID_MV88FR571_VD ||
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cputype == CPU_ID_MV88FR571_41) {
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@ -686,40 +458,6 @@ set_cpufuncs(void)
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}
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#endif /* CPU_MV_PJ4B */
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#if defined(CPU_FA526)
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if (cputype == CPU_ID_FA526 || cputype == CPU_ID_FA626TE) {
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cpufuncs = fa526_cpufuncs;
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cpu_reset_needs_v4_MMU_disable = 1; /* SA needs it */
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get_cachetype_cp15();
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pmap_pte_init_generic();
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goto out;
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}
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#endif /* CPU_FA526 */
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#if defined(CPU_XSCALE_81342)
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if (cputype == CPU_ID_81342) {
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cpufuncs = xscalec3_cpufuncs;
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cpu_reset_needs_v4_MMU_disable = 1; /* XScale needs it */
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get_cachetype_cp15();
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pmap_pte_init_xscale();
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goto out;
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}
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#endif /* CPU_XSCALE_81342 */
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#ifdef CPU_XSCALE_PXA2X0
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/* ignore core revision to test PXA2xx CPUs */
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if ((cputype & ~CPU_ID_XSCALE_COREREV_MASK) == CPU_ID_PXA250 ||
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(cputype & ~CPU_ID_XSCALE_COREREV_MASK) == CPU_ID_PXA27X ||
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(cputype & ~CPU_ID_XSCALE_COREREV_MASK) == CPU_ID_PXA210) {
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cpufuncs = xscale_cpufuncs;
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cpu_reset_needs_v4_MMU_disable = 1; /* XScale needs it */
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get_cachetype_cp15();
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pmap_pte_init_xscale();
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goto out;
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}
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#endif /* CPU_XSCALE_PXA2X0 */
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/*
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* Bzzzz. And the answer was ...
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*/
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@ -734,44 +472,6 @@ set_cpufuncs(void)
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* CPU Setup code
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*/
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#ifdef CPU_ARM9
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void
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arm9_setup(void)
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{
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int cpuctrl, cpuctrlmask;
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cpuctrl = CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_32BP_ENABLE
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| CPU_CONTROL_32BD_ENABLE | CPU_CONTROL_SYST_ENABLE
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| CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE
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| CPU_CONTROL_WBUF_ENABLE | CPU_CONTROL_LABT_ENABLE |
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CPU_CONTROL_ROUNDROBIN;
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cpuctrlmask = CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_32BP_ENABLE
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| CPU_CONTROL_32BD_ENABLE | CPU_CONTROL_SYST_ENABLE
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| CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE
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| CPU_CONTROL_WBUF_ENABLE | CPU_CONTROL_ROM_ENABLE
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| CPU_CONTROL_BEND_ENABLE | CPU_CONTROL_AFLT_ENABLE
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| CPU_CONTROL_LABT_ENABLE | CPU_CONTROL_VECRELOC
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| CPU_CONTROL_ROUNDROBIN;
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#ifndef ARM32_DISABLE_ALIGNMENT_FAULTS
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cpuctrl |= CPU_CONTROL_AFLT_ENABLE;
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#endif
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#ifdef __ARMEB__
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cpuctrl |= CPU_CONTROL_BEND_ENABLE;
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#endif
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if (vector_page == ARM_VECTORS_HIGH)
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cpuctrl |= CPU_CONTROL_VECRELOC;
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/* Clear out the cache */
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cpu_idcache_wbinv_all();
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/* Set the control register (SCTLR) */
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cpu_control(cpuctrlmask, cpuctrl);
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}
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#endif /* CPU_ARM9 */
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#if defined(CPU_ARM9E)
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void
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arm10_setup(void)
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@ -894,109 +594,3 @@ cortexa_setup(void)
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cpu_scc_setup_ccnt();
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}
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#endif /* CPU_CORTEXA || CPU_KRAIT */
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#if defined(CPU_FA526)
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void
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fa526_setup(void)
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{
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int cpuctrl, cpuctrlmask;
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cpuctrl = CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_32BP_ENABLE
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| CPU_CONTROL_32BD_ENABLE | CPU_CONTROL_SYST_ENABLE
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| CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE
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| CPU_CONTROL_WBUF_ENABLE | CPU_CONTROL_LABT_ENABLE
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| CPU_CONTROL_BPRD_ENABLE;
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cpuctrlmask = CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_32BP_ENABLE
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| CPU_CONTROL_32BD_ENABLE | CPU_CONTROL_SYST_ENABLE
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| CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE
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| CPU_CONTROL_WBUF_ENABLE | CPU_CONTROL_ROM_ENABLE
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| CPU_CONTROL_BEND_ENABLE | CPU_CONTROL_AFLT_ENABLE
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| CPU_CONTROL_LABT_ENABLE | CPU_CONTROL_BPRD_ENABLE
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| CPU_CONTROL_CPCLK | CPU_CONTROL_VECRELOC;
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#ifndef ARM32_DISABLE_ALIGNMENT_FAULTS
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cpuctrl |= CPU_CONTROL_AFLT_ENABLE;
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#endif
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#ifdef __ARMEB__
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cpuctrl |= CPU_CONTROL_BEND_ENABLE;
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#endif
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if (vector_page == ARM_VECTORS_HIGH)
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cpuctrl |= CPU_CONTROL_VECRELOC;
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/* Clear out the cache */
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cpu_idcache_wbinv_all();
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/* Set the control register */
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cpu_control(0xffffffff, cpuctrl);
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}
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#endif /* CPU_FA526 */
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#if defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_81342)
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void
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xscale_setup(void)
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{
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uint32_t auxctl;
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int cpuctrl, cpuctrlmask;
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/*
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* The XScale Write Buffer is always enabled. Our option
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* is to enable/disable coalescing. Note that bits 6:3
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* must always be enabled.
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*/
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cpuctrl = CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_32BP_ENABLE
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| CPU_CONTROL_32BD_ENABLE | CPU_CONTROL_SYST_ENABLE
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| CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE
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| CPU_CONTROL_WBUF_ENABLE | CPU_CONTROL_LABT_ENABLE
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| CPU_CONTROL_BPRD_ENABLE;
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cpuctrlmask = CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_32BP_ENABLE
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| CPU_CONTROL_32BD_ENABLE | CPU_CONTROL_SYST_ENABLE
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| CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE
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| CPU_CONTROL_WBUF_ENABLE | CPU_CONTROL_ROM_ENABLE
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| CPU_CONTROL_BEND_ENABLE | CPU_CONTROL_AFLT_ENABLE
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| CPU_CONTROL_LABT_ENABLE | CPU_CONTROL_BPRD_ENABLE
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| CPU_CONTROL_CPCLK | CPU_CONTROL_VECRELOC | \
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CPU_CONTROL_L2_ENABLE;
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#ifndef ARM32_DISABLE_ALIGNMENT_FAULTS
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cpuctrl |= CPU_CONTROL_AFLT_ENABLE;
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#endif
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#ifdef __ARMEB__
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cpuctrl |= CPU_CONTROL_BEND_ENABLE;
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#endif
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if (vector_page == ARM_VECTORS_HIGH)
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cpuctrl |= CPU_CONTROL_VECRELOC;
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#ifdef CPU_XSCALE_CORE3
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cpuctrl |= CPU_CONTROL_L2_ENABLE;
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#endif
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/* Clear out the cache */
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cpu_idcache_wbinv_all();
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/*
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* Set the control register. Note that bits 6:3 must always
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* be set to 1.
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*/
|
||||
/* cpu_control(cpuctrlmask, cpuctrl);*/
|
||||
cpu_control(0xffffffff, cpuctrl);
|
||||
|
||||
/* Make sure write coalescing is turned on */
|
||||
__asm __volatile("mrc p15, 0, %0, c1, c0, 1"
|
||||
: "=r" (auxctl));
|
||||
#ifdef XSCALE_NO_COALESCE_WRITES
|
||||
auxctl |= XSCALE_AUXCTL_K;
|
||||
#else
|
||||
auxctl &= ~XSCALE_AUXCTL_K;
|
||||
#endif
|
||||
#ifdef CPU_XSCALE_CORE3
|
||||
auxctl |= XSCALE_AUXCTL_LLR;
|
||||
auxctl |= XSCALE_AUXCTL_MD_MASK;
|
||||
#endif
|
||||
__asm __volatile("mcr p15, 0, %0, c1, c0, 1"
|
||||
: : "r" (auxctl));
|
||||
}
|
||||
#endif /* CPU_XSCALE_PXA2X0 */
|
||||
|
||||
@ -34,23 +34,6 @@
|
||||
#include <machine/asm.h>
|
||||
__FBSDID("$FreeBSD$");
|
||||
|
||||
/*
|
||||
* Functions to set the MMU Translation Table Base register
|
||||
*
|
||||
* We need to clean and flush the cache as it uses virtual
|
||||
* addresses that are about to change.
|
||||
*/
|
||||
ENTRY(arm9_setttb)
|
||||
stmfd sp!, {r0, lr}
|
||||
bl _C_LABEL(arm9_idcache_wbinv_all)
|
||||
ldmfd sp!, {r0, lr}
|
||||
|
||||
mcr p15, 0, r0, c2, c0, 0 /* load new TTB */
|
||||
|
||||
mcr p15, 0, r0, c8, c7, 0 /* invalidate I+D TLBs */
|
||||
mov pc, lr
|
||||
END(arm9_setttb)
|
||||
|
||||
/*
|
||||
* TLB functions
|
||||
*/
|
||||
@ -60,160 +43,6 @@ ENTRY(arm9_tlb_flushID_SE)
|
||||
mov pc, lr
|
||||
END(arm9_tlb_flushID_SE)
|
||||
|
||||
/*
|
||||
* Cache operations. For the entire cache we use the set/index
|
||||
* operations.
|
||||
*/
|
||||
s_max .req r0
|
||||
i_max .req r1
|
||||
s_inc .req r2
|
||||
i_inc .req r3
|
||||
|
||||
ENTRY_NP(arm9_icache_sync_range)
|
||||
ldr ip, .Larm9_line_size
|
||||
cmp r1, #0x4000
|
||||
bcs .Larm9_icache_sync_all
|
||||
ldr ip, [ip]
|
||||
sub r3, ip, #1
|
||||
and r2, r0, r3
|
||||
add r1, r1, r2
|
||||
bic r0, r0, r3
|
||||
.Larm9_sync_next:
|
||||
mcr p15, 0, r0, c7, c5, 1 /* Invalidate I cache SE with VA */
|
||||
mcr p15, 0, r0, c7, c10, 1 /* Clean D cache SE with VA */
|
||||
add r0, r0, ip
|
||||
subs r1, r1, ip
|
||||
bhi .Larm9_sync_next
|
||||
mov pc, lr
|
||||
|
||||
.Larm9_icache_sync_all:
|
||||
/*
|
||||
* We assume that the code here can never be out of sync with the
|
||||
* dcache, so that we can safely flush the Icache and fall through
|
||||
* into the Dcache cleaning code.
|
||||
*/
|
||||
mcr p15, 0, r0, c7, c5, 0 /* Flush I cache */
|
||||
/* Fall through to clean Dcache. */
|
||||
|
||||
.Larm9_dcache_wb:
|
||||
ldr ip, .Larm9_cache_data
|
||||
ldmia ip, {s_max, i_max, s_inc, i_inc}
|
||||
.Lnext_set:
|
||||
orr ip, s_max, i_max
|
||||
.Lnext_index:
|
||||
mcr p15, 0, ip, c7, c10, 2 /* Clean D cache SE with Set/Index */
|
||||
subs ip, ip, i_inc
|
||||
bhs .Lnext_index /* Next index */
|
||||
subs s_max, s_max, s_inc
|
||||
bhs .Lnext_set /* Next set */
|
||||
mov pc, lr
|
||||
END(arm9_icache_sync_range)
|
||||
|
||||
.Larm9_line_size:
|
||||
.word _C_LABEL(arm_pdcache_line_size)
|
||||
|
||||
ENTRY(arm9_dcache_wb_range)
|
||||
ldr ip, .Larm9_line_size
|
||||
cmp r1, #0x4000
|
||||
bcs .Larm9_dcache_wb
|
||||
ldr ip, [ip]
|
||||
sub r3, ip, #1
|
||||
and r2, r0, r3
|
||||
add r1, r1, r2
|
||||
bic r0, r0, r3
|
||||
.Larm9_wb_next:
|
||||
mcr p15, 0, r0, c7, c10, 1 /* Clean D cache SE with VA */
|
||||
add r0, r0, ip
|
||||
subs r1, r1, ip
|
||||
bhi .Larm9_wb_next
|
||||
mov pc, lr
|
||||
END(arm9_dcache_wb_range)
|
||||
|
||||
ENTRY(arm9_dcache_wbinv_range)
|
||||
ldr ip, .Larm9_line_size
|
||||
cmp r1, #0x4000
|
||||
bcs .Larm9_dcache_wbinv_all
|
||||
ldr ip, [ip]
|
||||
sub r3, ip, #1
|
||||
and r2, r0, r3
|
||||
add r1, r1, r2
|
||||
bic r0, r0, r3
|
||||
.Larm9_wbinv_next:
|
||||
mcr p15, 0, r0, c7, c14, 1 /* Purge D cache SE with VA */
|
||||
add r0, r0, ip
|
||||
subs r1, r1, ip
|
||||
bhi .Larm9_wbinv_next
|
||||
mov pc, lr
|
||||
END(arm9_dcache_wbinv_range)
|
||||
|
||||
/*
|
||||
* Note, we must not invalidate everything. If the range is too big we
|
||||
* must use wb-inv of the entire cache.
|
||||
*/
|
||||
ENTRY(arm9_dcache_inv_range)
|
||||
ldr ip, .Larm9_line_size
|
||||
cmp r1, #0x4000
|
||||
bcs .Larm9_dcache_wbinv_all
|
||||
ldr ip, [ip]
|
||||
sub r3, ip, #1
|
||||
and r2, r0, r3
|
||||
add r1, r1, r2
|
||||
bic r0, r0, r3
|
||||
.Larm9_inv_next:
|
||||
mcr p15, 0, r0, c7, c6, 1 /* Invalidate D cache SE with VA */
|
||||
add r0, r0, ip
|
||||
subs r1, r1, ip
|
||||
bhi .Larm9_inv_next
|
||||
mov pc, lr
|
||||
END(arm9_dcache_inv_range)
|
||||
|
||||
ENTRY(arm9_idcache_wbinv_range)
|
||||
ldr ip, .Larm9_line_size
|
||||
cmp r1, #0x4000
|
||||
bcs .Larm9_idcache_wbinv_all
|
||||
ldr ip, [ip]
|
||||
sub r3, ip, #1
|
||||
and r2, r0, r3
|
||||
add r1, r1, r2
|
||||
bic r0, r0, r3
|
||||
.Larm9_id_wbinv_next:
|
||||
mcr p15, 0, r0, c7, c5, 1 /* Invalidate I cache SE with VA */
|
||||
mcr p15, 0, r0, c7, c14, 1 /* Purge D cache SE with VA */
|
||||
add r0, r0, ip
|
||||
subs r1, r1, ip
|
||||
bhi .Larm9_id_wbinv_next
|
||||
mov pc, lr
|
||||
END(arm9_idcache_wbinv_range)
|
||||
|
||||
ENTRY_NP(arm9_idcache_wbinv_all)
|
||||
.Larm9_idcache_wbinv_all:
|
||||
/*
|
||||
* We assume that the code here can never be out of sync with the
|
||||
* dcache, so that we can safely flush the Icache and fall through
|
||||
* into the Dcache purging code.
|
||||
*/
|
||||
mcr p15, 0, r0, c7, c5, 0 /* Flush I cache */
|
||||
/* Fall through */
|
||||
|
||||
EENTRY(arm9_dcache_wbinv_all)
|
||||
.Larm9_dcache_wbinv_all:
|
||||
ldr ip, .Larm9_cache_data
|
||||
ldmia ip, {s_max, i_max, s_inc, i_inc}
|
||||
.Lnext_set_inv:
|
||||
orr ip, s_max, i_max
|
||||
.Lnext_index_inv:
|
||||
mcr p15, 0, ip, c7, c14, 2 /* Purge D cache SE with Set/Index */
|
||||
subs ip, ip, i_inc
|
||||
bhs .Lnext_index_inv /* Next index */
|
||||
subs s_max, s_max, s_inc
|
||||
bhs .Lnext_set_inv /* Next set */
|
||||
mov pc, lr
|
||||
EEND(arm9_dcache_wbinv_all)
|
||||
END(arm9_idcache_wbinv_all)
|
||||
|
||||
.Larm9_cache_data:
|
||||
.word _C_LABEL(arm9_dcache_sets_max)
|
||||
|
||||
/*
|
||||
* Context switch.
|
||||
*
|
||||
@ -238,24 +67,3 @@ ENTRY(arm9_context_switch)
|
||||
nop
|
||||
mov pc, lr
|
||||
END(arm9_context_switch)
|
||||
|
||||
.bss
|
||||
|
||||
/* XXX The following macros should probably be moved to asm.h */
|
||||
#define _DATA_OBJECT(x) .globl x; .type x,_ASM_TYPE_OBJECT; x:
|
||||
#define C_OBJECT(x) _DATA_OBJECT(_C_LABEL(x))
|
||||
|
||||
/*
|
||||
* Parameters for the cache cleaning code. Note that the order of these
|
||||
* four variables is assumed in the code above. Hence the reason for
|
||||
* declaring them in the assembler file.
|
||||
*/
|
||||
.align 2
|
||||
C_OBJECT(arm9_dcache_sets_max)
|
||||
.space 4
|
||||
C_OBJECT(arm9_dcache_index_max)
|
||||
.space 4
|
||||
C_OBJECT(arm9_dcache_sets_inc)
|
||||
.space 4
|
||||
C_OBJECT(arm9_dcache_index_inc)
|
||||
.space 4
|
||||
|
||||
@ -216,49 +216,10 @@ u_int cpu_faultaddress (void);
|
||||
u_int cpu_get_control (void);
|
||||
u_int cpu_pfr (int);
|
||||
|
||||
#if defined(CPU_FA526)
|
||||
void fa526_setup (void);
|
||||
void fa526_setttb (u_int ttb);
|
||||
void fa526_context_switch (void);
|
||||
void fa526_cpu_sleep (int);
|
||||
void fa526_tlb_flushID_SE (u_int);
|
||||
|
||||
void fa526_icache_sync_range(vm_offset_t start, vm_size_t end);
|
||||
void fa526_dcache_wbinv_all (void);
|
||||
void fa526_dcache_wbinv_range(vm_offset_t start, vm_size_t end);
|
||||
void fa526_dcache_inv_range (vm_offset_t start, vm_size_t end);
|
||||
void fa526_dcache_wb_range (vm_offset_t start, vm_size_t end);
|
||||
void fa526_idcache_wbinv_all(void);
|
||||
void fa526_idcache_wbinv_range(vm_offset_t start, vm_size_t end);
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(CPU_ARM9) || defined(CPU_ARM9E)
|
||||
void arm9_setttb (u_int);
|
||||
#if defined(CPU_ARM9E)
|
||||
void arm9_tlb_flushID_SE (u_int va);
|
||||
void arm9_context_switch (void);
|
||||
#endif
|
||||
|
||||
#if defined(CPU_ARM9)
|
||||
void arm9_icache_sync_range (vm_offset_t, vm_size_t);
|
||||
|
||||
void arm9_dcache_wbinv_all (void);
|
||||
void arm9_dcache_wbinv_range (vm_offset_t, vm_size_t);
|
||||
void arm9_dcache_inv_range (vm_offset_t, vm_size_t);
|
||||
void arm9_dcache_wb_range (vm_offset_t, vm_size_t);
|
||||
|
||||
void arm9_idcache_wbinv_all (void);
|
||||
void arm9_idcache_wbinv_range (vm_offset_t, vm_size_t);
|
||||
|
||||
void arm9_setup (void);
|
||||
|
||||
extern unsigned arm9_dcache_sets_max;
|
||||
extern unsigned arm9_dcache_sets_inc;
|
||||
extern unsigned arm9_dcache_index_max;
|
||||
extern unsigned arm9_dcache_index_inc;
|
||||
#endif
|
||||
|
||||
#if defined(CPU_ARM9E)
|
||||
void arm10_setup (void);
|
||||
|
||||
u_int sheeva_control_ext (u_int, u_int);
|
||||
@ -303,11 +264,6 @@ void armv5_ec_dcache_wb_range(vm_offset_t, vm_size_t);
|
||||
|
||||
void armv5_ec_idcache_wbinv_all(void);
|
||||
void armv5_ec_idcache_wbinv_range(vm_offset_t, vm_size_t);
|
||||
#endif
|
||||
|
||||
#if defined(CPU_ARM9) || defined(CPU_ARM9E) || \
|
||||
defined(CPU_FA526) || \
|
||||
defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_81342)
|
||||
|
||||
void armv4_tlb_flushID (void);
|
||||
void armv4_tlb_flushD (void);
|
||||
@ -317,71 +273,6 @@ void armv4_drain_writebuf (void);
|
||||
void armv4_idcache_inv_all (void);
|
||||
#endif
|
||||
|
||||
#if defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_81342)
|
||||
void xscale_cpwait (void);
|
||||
|
||||
void xscale_cpu_sleep (int mode);
|
||||
|
||||
u_int xscale_control (u_int clear, u_int bic);
|
||||
|
||||
void xscale_setttb (u_int ttb);
|
||||
|
||||
void xscale_tlb_flushID_SE (u_int va);
|
||||
|
||||
void xscale_cache_flushID (void);
|
||||
void xscale_cache_flushI (void);
|
||||
void xscale_cache_flushD (void);
|
||||
void xscale_cache_flushD_SE (u_int entry);
|
||||
|
||||
void xscale_cache_cleanID (void);
|
||||
void xscale_cache_cleanD (void);
|
||||
void xscale_cache_cleanD_E (u_int entry);
|
||||
|
||||
void xscale_cache_clean_minidata (void);
|
||||
|
||||
void xscale_cache_purgeID (void);
|
||||
void xscale_cache_purgeID_E (u_int entry);
|
||||
void xscale_cache_purgeD (void);
|
||||
void xscale_cache_purgeD_E (u_int entry);
|
||||
|
||||
void xscale_cache_syncI (void);
|
||||
void xscale_cache_cleanID_rng (vm_offset_t start, vm_size_t end);
|
||||
void xscale_cache_cleanD_rng (vm_offset_t start, vm_size_t end);
|
||||
void xscale_cache_purgeID_rng (vm_offset_t start, vm_size_t end);
|
||||
void xscale_cache_purgeD_rng (vm_offset_t start, vm_size_t end);
|
||||
void xscale_cache_syncI_rng (vm_offset_t start, vm_size_t end);
|
||||
void xscale_cache_flushD_rng (vm_offset_t start, vm_size_t end);
|
||||
|
||||
void xscale_context_switch (void);
|
||||
|
||||
void xscale_setup (void);
|
||||
#endif /* CPU_XSCALE_PXA2X0 */
|
||||
|
||||
#ifdef CPU_XSCALE_81342
|
||||
|
||||
void xscalec3_l2cache_purge (void);
|
||||
void xscalec3_cache_purgeID (void);
|
||||
void xscalec3_cache_purgeD (void);
|
||||
void xscalec3_cache_cleanID (void);
|
||||
void xscalec3_cache_cleanD (void);
|
||||
void xscalec3_cache_syncI (void);
|
||||
|
||||
void xscalec3_cache_purgeID_rng (vm_offset_t start, vm_size_t end);
|
||||
void xscalec3_cache_purgeD_rng (vm_offset_t start, vm_size_t end);
|
||||
void xscalec3_cache_cleanID_rng (vm_offset_t start, vm_size_t end);
|
||||
void xscalec3_cache_cleanD_rng (vm_offset_t start, vm_size_t end);
|
||||
void xscalec3_cache_syncI_rng (vm_offset_t start, vm_size_t end);
|
||||
|
||||
void xscalec3_l2cache_flush_rng (vm_offset_t, vm_size_t);
|
||||
void xscalec3_l2cache_clean_rng (vm_offset_t start, vm_size_t end);
|
||||
void xscalec3_l2cache_purge_rng (vm_offset_t start, vm_size_t end);
|
||||
|
||||
|
||||
void xscalec3_setttb (u_int ttb);
|
||||
void xscalec3_context_switch (void);
|
||||
|
||||
#endif /* CPU_XSCALE_81342 */
|
||||
|
||||
/*
|
||||
* Macros for manipulating CPU interrupts
|
||||
*/
|
||||
|
||||
Loading…
Reference in New Issue
Block a user