d/freebsd-nq
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Improved Cyrix 486DX supports for NEC PC-98.

Browse Source 
- Enable WB cache via CCR2 and CR0.
  - Set the need_pre_dma_flush when the CPU_I486_ON_386 option is
    defined.

Submitted by:	Kaho Toshikazu <kaho@elam.kais.kyoto-u.ac.jp>
This commit is contained in:
KATO Takenori 2000-08-31 10:33:06 +00:00
parent 8b6a5e91bb
commit 1cfd836f65
2 changed files with 30 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

15
sys/amd64/amd64/initcpu.c
View File

@ -164,6 +164,15 @@ init_cy486dx(void)
#ifdef CPU_SUSP_HLT
ccr2 |= CCR2_SUSP_HLT;
#endif
#ifdef PC98
/* Enables WB cache interface pin and Lock NW bit in CR0. */
ccr2 |= CCR2_WB | CCR2_LOCK_NW;
/* Unlock NW bit in CR0. */
write_cyrix_reg(CCR2, ccr2 & ~CCR2_LOCK_NW);
load_cr0((rcr0() & ~CR0_CD) | CR0_NW); /* CD = 0, NW = 1 */
#endif
write_cyrix_reg(CCR2, ccr2);
write_eflags(eflags);
}
@ -561,6 +570,12 @@ initializecpu(void)
case CPU_M1SC:
need_pre_dma_flush = 1;
break;
case CPU_CY486DX:
need_pre_dma_flush = 1;
#ifdef CPU_I486_ON_386
need_post_dma_flush = 1;
#endif
break;
#endif
default:
break;

15
sys/i386/i386/initcpu.c
View File

@ -164,6 +164,15 @@ init_cy486dx(void)
#ifdef CPU_SUSP_HLT
ccr2 |= CCR2_SUSP_HLT;
#endif
#ifdef PC98
/* Enables WB cache interface pin and Lock NW bit in CR0. */
ccr2 |= CCR2_WB | CCR2_LOCK_NW;
/* Unlock NW bit in CR0. */
write_cyrix_reg(CCR2, ccr2 & ~CCR2_LOCK_NW);
load_cr0((rcr0() & ~CR0_CD) | CR0_NW); /* CD = 0, NW = 1 */
#endif
write_cyrix_reg(CCR2, ccr2);
write_eflags(eflags);
}
@ -561,6 +570,12 @@ initializecpu(void)
case CPU_M1SC:
need_pre_dma_flush = 1;
break;
case CPU_CY486DX:
need_pre_dma_flush = 1;
#ifdef CPU_I486_ON_386
need_post_dma_flush = 1;
#endif
break;
#endif
default:
break;