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Update the comments above the 0xcf9 register reset attempt to match the

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code.  We only attempt a single reset using this method (a "hard" reset),
and we use two writes to ensure there is a 0 -> 1 transition in bit 2 to
force a reset.

MFC after:	1 week
This commit is contained in:
John Baldwin 2008-09-11 18:33:57 +00:00
parent 0d62170990
commit 289f40c67b
2 changed files with 14 additions and 8 deletions
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11
sys/amd64/amd64/vm_machdep.c
View File

@ -466,10 +466,13 @@ cpu_reset_real()
/*
* Attempt to force a reset via the Reset Control register at
* I/O port 0xcf9. Bit 2 forces a system reset when it is
* written as 1. Bit 1 selects the type of reset to attempt:
* 0 selects a "soft" reset, and 1 selects a "hard" reset. We
* try to do a "soft" reset first, and then a "hard" reset.
* I/O port 0xcf9. Bit 2 forces a system reset when it
* transitions from 0 to 1. Bit 1 selects the type of reset
* to attempt: 0 selects a "soft" reset, and 1 selects a
* "hard" reset. We try a "hard" reset. The first write sets
* bit 1 to select a "hard" reset and clears bit 2. The
* second write forces a 0 -> 1 transition in bit 2 to trigger
* a reset.
*/
outb(0xcf9, 0x2);
outb(0xcf9, 0x6);

11
sys/i386/i386/vm_machdep.c
View File

@ -643,10 +643,13 @@ cpu_reset_real()
/*
* Attempt to force a reset via the Reset Control register at
* I/O port 0xcf9. Bit 2 forces a system reset when it is
* written as 1. Bit 1 selects the type of reset to attempt:
* 0 selects a "soft" reset, and 1 selects a "hard" reset. We
* try to do a "soft" reset first, and then a "hard" reset.
* I/O port 0xcf9. Bit 2 forces a system reset when it
* transitions from 0 to 1. Bit 1 selects the type of reset
* to attempt: 0 selects a "soft" reset, and 1 selects a
* "hard" reset. We try a "hard" reset. The first write sets
* bit 1 to select a "hard" reset and clears bit 2. The
* second write forces a 0 -> 1 transition in bit 2 to trigger
* a reset.
*/
outb(0xcf9, 0x2);
outb(0xcf9, 0x6);