[PowerPC64LE] Tell the hypervisor to switch interrupts to LE at CHRP attach.
Since we will need to be able to take traps relatively early in the process, ensure that the hypervisor changes our ILE for us as soon as we are ready. Sponsored by: Tag1 Consulting, Inc.
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@ -170,6 +170,13 @@
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#define H_PP1 (1UL<<(63-62))
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#define H_PP2 (1UL<<(63-63))
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/* H_SET_MODE resource identifiers from 14.5.4.3.5. */
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#define H_SET_MODE_RSRC_CIABR 0x1 /* All versions */
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#define H_SET_MODE_RSRC_DAWR0 0x2 /* All versions */
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#define H_SET_MODE_RSRC_INTR_TRANS_MODE 0x3 /* All versions */
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#define H_SET_MODE_RSRC_ILE 0x4 /* PAPR 2.8 / ISA 2.07 */
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#define H_SET_MODE_RSRC_DAWR1 0x5 /* ISA 3.1 Future support */
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/* pSeries hypervisor opcodes. */
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#define H_REMOVE 0x04
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#define H_ENTER 0x08
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@ -136,6 +136,9 @@ chrp_attach(platform_t plat)
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int quiesce;
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#ifdef __powerpc64__
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int i;
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#if BYTE_ORDER == LITTLE_ENDIAN
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int result;
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#endif
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/* XXX: check for /rtas/ibm,hypertas-functions? */
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if (!(mfmsr() & PSL_HV)) {
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@ -171,6 +174,24 @@ chrp_attach(platform_t plat)
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/* Set up hypervisor CPU stuff */
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chrp_smp_ap_init(plat);
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#if BYTE_ORDER == LITTLE_ENDIAN
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/*
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* Ask the hypervisor to update the LPAR ILE bit.
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*
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* This involves all processors reentering the hypervisor
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* so the change appears simultaneously in all processors.
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* This can take a long time.
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*/
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for(;;) {
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result = phyp_hcall(H_SET_MODE, 1UL,
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H_SET_MODE_RSRC_ILE, 0, 0);
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if (result == H_SUCCESS)
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break;
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DELAY(1000);
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}
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#endif
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}
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#endif
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chrp_cpuref_init();
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