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CACHE_LINE_SIZE is 64 on athlon and amd64 chips, not 32. This should

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probably be 128 since that is what the hardware prefetch fill size is
on both the p3, p4 and athlon* cpus.
This commit is contained in:
Peter Wemm 2003-12-11 04:47:53 +00:00
parent 2e227f0406
commit 40a7c81112
1 changed files with 1 additions and 1 deletions
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2
libexec/rtld-elf/amd64/lockdflt.c
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@ -55,7 +55,7 @@
#include "debug.h"
#include "rtld.h"
#define CACHE_LINE_SIZE 32
#define CACHE_LINE_SIZE 64
#define WAFLAG 0x1 /* A writer holds the lock */
#define RC_INCR 0x2 /* Adjusts count of readers desiring lock */