Add a driver for the AVR32 series USB Device Controller. Not hooked up as
FreeBSD does not yet support this platform but it makes it easier to stay in sync. Submitted by: Hans Petter Selasky
This commit is contained in:
Andrew Thompson
parent
476183df94
commit
55e76c210e
2065
sys/dev/usb/controller/avr32dci.c
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2065
sys/dev/usb/controller/avr32dci.c
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sys/dev/usb/controller/avr32dci.h
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sys/dev/usb/controller/avr32dci.h
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/* $FreeBSD$ */
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/*-
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* Copyright (c) 2009 Hans Petter Selasky. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#ifndef _AVR32DCI_H_
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#define _AVR32DCI_H_
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#define AVR32_MAX_DEVICES (USB_MIN_DEVICES + 1)
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/* Register definitions */
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#define AVR32_CTRL 0x00 /* Control */
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#define AVR32_CTRL_DEV_ADDR 0x7F
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#define AVR32_CTRL_DEV_FADDR_EN 0x80
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#define AVR32_CTRL_DEV_EN_USBA 0x100
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#define AVR32_CTRL_DEV_DETACH 0x200
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#define AVR32_CTRL_DEV_REWAKEUP 0x400
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#define AVR32_FNUM 0x04 /* Frame Number */
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#define AVR32_FNUM_MASK 0x3FFF
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#define AVR32_FRAME_MASK 0x7FF
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/* 0x08 - 0x0C Reserved */
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#define AVR32_IEN 0x10 /* Interrupt Enable */
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#define AVR32_INTSTA 0x14 /* Interrupt Status */
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#define AVR32_CLRINT 0x18 /* Clear Interrupt */
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#define AVR32_INT_SPEED 0x00000001 /* set if High Speed else Full Speed */
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#define AVR32_INT_DET_SUSPD 0x00000002
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#define AVR32_INT_MICRO_SOF 0x00000004
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#define AVR32_INT_INT_SOF 0x00000008
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#define AVR32_INT_ENDRESET 0x00000010
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#define AVR32_INT_WAKE_UP 0x00000020
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#define AVR32_INT_ENDOFRSM 0x00000040
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#define AVR32_INT_UPSTR_RES 0x00000080
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#define AVR32_INT_EPT_INT(n) (0x00000100 << (n))
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#define AVR32_INT_DMA_INT(n) (0x01000000 << (n))
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#define AVR32_EPTRST 0x1C /* Endpoints Reset */
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#define AVR32_EPTRST_MASK(n) (0x00000001 << (n))
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/* 0x20 - 0xCC Reserved */
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#define AVR32_TSTSOFCNT 0xD0 /* Test SOF Counter */
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#define AVR32_TSTCNTA 0xD4 /* Test A Counter */
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#define AVR32_TSTCNTB 0xD8 /* Test B Counter */
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#define AVR32_TSTMODEREG 0xDC /* Test Mode */
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#define AVR32_TST 0xE0 /* Test */
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#define AVR32_TST_NORMAL 0x00000000
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#define AVR32_TST_HS_ONLY 0x00000002
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#define AVR32_TST_FS_ONLY 0x00000003
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/* 0xE4 - 0xE8 Reserved */
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#define AVR32_IPPADDRSIZE 0xEC /* PADDRSIZE */
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#define AVR32_IPNAME1 0xF0 /* Name1 */
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#define AVR32_IPNAME2 0xF4 /* Name2 */
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#define AVR32_IPFEATURES 0xF8 /* Features */
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#define AVR32_IPFEATURES_NEP(x) (((x) & 0xF) ? ((x) & 0xF) : 0x10)
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#define AVR32_IPVERSION 0xFC /* IP Version */
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#define _A(base,n) ((base) + (0x20*(n)))
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#define AVR32_EPTCFG(n) _A(0x100, n) /* Endpoint Configuration */
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#define AVR32_EPTCFG_EPSIZE(n) ((n)-3) /* power of two */
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#define AVR32_EPTCFG_EPDIR_OUT 0x00000000
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#define AVR32_EPTCFG_EPDIR_IN 0x00000008
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#define AVR32_EPTCFG_TYPE_CTRL 0x00000000
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#define AVR32_EPTCFG_TYPE_ISOC 0x00000100
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#define AVR32_EPTCFG_TYPE_BULK 0x00000200
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#define AVR32_EPTCFG_TYPE_INTR 0x00000300
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#define AVR32_EPTCFG_NBANK(n) (0x00000400*(n))
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#define AVR32_EPTCFG_NB_TRANS(n) (0x00001000*(n))
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#define AVR32_EPTCFG_EPT_MAPD 0x80000000
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#define AVR32_EPTCTLENB(n) _A(0x104, n) /* Endpoint Control Enable */
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#define AVR32_EPTCTLDIS(n) _A(0x108, n) /* Endpoint Control Disable */
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#define AVR32_EPTCTL(n) _A(0x10C, n) /* Endpoint Control */
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#define AVR32_EPTCTL_EPT_ENABL 0x00000001
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#define AVR32_EPTCTL_AUTO_VALID 0x00000002
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#define AVR32_EPTCTL_INTDIS_DMA 0x00000008
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#define AVR32_EPTCTL_NYET_DIS 0x00000010
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#define AVR32_EPTCTL_DATAX_RX 0x00000040
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#define AVR32_EPTCTL_MDATA_RX 0x00000080
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#define AVR32_EPTCTL_ERR_OVFLW 0x00000100
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#define AVR32_EPTCTL_RX_BK_RDY 0x00000200
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#define AVR32_EPTCTL_TX_COMPLT 0x00000400
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#define AVR32_EPTCTL_TX_PK_RDY 0x00000800
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#define AVR32_EPTCTL_RX_SETUP 0x00001000
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#define AVR32_EPTCTL_STALL_SNT 0x00002000
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#define AVR32_EPTCTL_NAK_IN 0x00004000
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#define AVR32_EPTCTL_NAK_OUT 0x00008000
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#define AVR32_EPTCTL_BUSY_BANK 0x00040000
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#define AVR32_EPTCTL_SHORT_PCKT 0x80000000
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/* 0x110 Reserved */
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#define AVR32_EPTSETSTA(n) _A(0x114, n) /* Endpoint Set Status */
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#define AVR32_EPTCLRSTA(n) _A(0x118, n) /* Endpoint Clear Status */
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#define AVR32_EPTSTA(n) _A(0x11C, n) /* Endpoint Status */
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#define AVR32_EPTSTA_FRCESTALL 0x00000020
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#define AVR32_EPTSTA_TOGGLESQ_STA(x) (((x) & 0xC0) >> 6)
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#define AVR32_EPTSTA_TOGGLESQ 0x00000040
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#define AVR32_EPTSTA_ERR_OVFLW 0x00000100
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#define AVR32_EPTSTA_RX_BK_RDY 0x00000200
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#define AVR32_EPTSTA_TX_COMPLT 0x00000400
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#define AVR32_EPTSTA_TX_PK_RDY 0x00000800
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#define AVR32_EPTSTA_RX_SETUP 0x00001000
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#define AVR32_EPTSTA_STALL_SNT 0x00002000
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#define AVR32_EPTSTA_NAK_IN 0x00004000
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#define AVR32_EPTSTA_NAK_OUT 0x00008000
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#define AVR32_EPTSTA_CURRENT_BANK(x) (((x) & 0x00030000) >> 16)
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#define AVR32_EPTSTA_BUSY_BANK_STA(x) (((x) & 0x000C0000) >> 18)
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#define AVR32_EPTSTA_BYTE_COUNT(x) (((x) & 0x7FF00000) >> 20)
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#define AVR32_EPTSTA_SHRT_PCKT 0x80000000
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/* 0x300 - 0x30C Reserved */
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#define AVR32_DMANXTDSC 0x310 /* DMA Next Descriptor Address */
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#define AVR32_DMAADDRESS 0x314 /* DMA Channel Address */
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#define AVR32_READ_4(sc, reg) \
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bus_space_read_4((sc)->sc_io_tag, (sc)->sc_io_hdl, reg)
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#define AVR32_WRITE_4(sc, reg, data) \
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bus_space_write_4((sc)->sc_io_tag, (sc)->sc_io_hdl, reg, data)
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#define AVR32_WRITE_MULTI_4(sc, reg, ptr, len) \
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bus_space_write_multi_4((sc)->sc_io_tag, (sc)->sc_io_hdl, reg, ptr, len)
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#define AVR32_READ_MULTI_4(sc, reg, ptr, len) \
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bus_space_read_multi_4((sc)->sc_io_tag, (sc)->sc_io_hdl, reg, ptr, len)
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/*
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* Maximum number of endpoints supported:
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*/
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#define AVR32_EP_MAX 7
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struct avr32dci_td;
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typedef uint8_t (avr32dci_cmd_t)(struct avr32dci_td *td);
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typedef void (avr32dci_clocks_t)(struct usb2_bus *);
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struct avr32dci_td {
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struct avr32dci_td *obj_next;
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avr32dci_cmd_t *func;
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struct usb2_page_cache *pc;
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uint32_t offset;
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uint32_t remainder;
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uint16_t max_packet_size;
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uint8_t error:1;
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uint8_t alt_next:1;
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uint8_t short_pkt:1;
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uint8_t support_multi_buffer:1;
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uint8_t did_stall:1;
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uint8_t ep_no:3;
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};
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struct avr32dci_std_temp {
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avr32dci_cmd_t *func;
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struct usb2_page_cache *pc;
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struct avr32dci_td *td;
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struct avr32dci_td *td_next;
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uint32_t len;
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uint32_t offset;
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uint16_t max_frame_size;
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uint8_t bank_shift;
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uint8_t short_pkt;
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/*
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* short_pkt = 0: transfer should be short terminated
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* short_pkt = 1: transfer should not be short terminated
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*/
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uint8_t setup_alt_next;
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uint8_t did_stall;
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};
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struct avr32dci_config_desc {
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struct usb2_config_descriptor confd;
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struct usb2_interface_descriptor ifcd;
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struct usb2_endpoint_descriptor endpd;
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} __packed;
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union avr32dci_hub_temp {
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uWord wValue;
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struct usb2_port_status ps;
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};
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struct avr32dci_flags {
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uint8_t change_connect:1;
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uint8_t change_suspend:1;
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uint8_t status_suspend:1; /* set if suspended */
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uint8_t status_vbus:1; /* set if present */
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uint8_t status_bus_reset:1; /* set if reset complete */
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uint8_t remote_wakeup:1;
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uint8_t self_powered:1;
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uint8_t clocks_off:1;
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uint8_t port_powered:1;
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uint8_t port_enabled:1;
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uint8_t d_pulled_up:1;
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};
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struct avr32dci_softc {
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struct usb2_bus sc_bus;
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union avr32dci_hub_temp sc_hub_temp;
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/* must be set by by the bus interface layer */
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avr32dci_clocks_t *sc_clocks_on;
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avr32dci_clocks_t *sc_clocks_off;
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struct usb2_device *sc_devices[AVR32_MAX_DEVICES];
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struct resource *sc_irq_res;
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void *sc_intr_hdl;
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struct resource *sc_io_res;
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bus_space_tag_t sc_io_tag;
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bus_space_handle_t sc_io_hdl;
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uint8_t *physdata;
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uint8_t sc_rt_addr; /* root hub address */
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uint8_t sc_dv_addr; /* device address */
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uint8_t sc_conf; /* root hub config */
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uint8_t sc_hub_idata[1];
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struct avr32dci_flags sc_flags;
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};
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/* prototypes */
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usb2_error_t avr32dci_init(struct avr32dci_softc *sc);
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void avr32dci_uninit(struct avr32dci_softc *sc);
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void avr32dci_suspend(struct avr32dci_softc *sc);
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void avr32dci_resume(struct avr32dci_softc *sc);
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void avr32dci_interrupt(struct avr32dci_softc *sc);
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void avr32dci_vbus_interrupt(struct avr32dci_softc *sc, uint8_t is_on);
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#endif /* _AVR32DCI_H_ */
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