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Ensure that BAR(0) is set for the PCI slot before the ath(4) PCI registers

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are written out.

This allows EEPROM-less NICs on the AR7241 PCIe bus to be correctly
initialised.

Tested:

* AP91 (AR7240+AR9285) - the existing board support didn't break;
* AP99 (AR7241+AR9287) - this fixed the configuration of the AR9287 PCI.
This commit is contained in:
Adrian Chadd 2012-08-26 04:39:20 +00:00
parent d5c5e2ef11
commit 8454b1bf68
1 changed files with 4 additions and 0 deletions
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4
sys/mips/atheros/ar724x_pci.c
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@ -270,6 +270,10 @@ ar724x_pci_fixup(device_t dev, long flash_addr, int len)
/* Save bar(0) address - just to flush bar(0) (SoC WAR) ? */
bar0 = ar724x_pci_read_config(dev, 0, 0, 0, PCIR_BAR(0), 4);
/* Write temporary BAR0 to map the NIC into a fixed location */
ar724x_pci_write_config(dev, 0, 0, 0, PCIR_BAR(0),
AR71XX_PCI_MEM_BASE, 4);
val = ar724x_pci_read_config(dev, 0, 0, 0, PCIR_COMMAND, 2);
val |= (PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN);
ar724x_pci_write_config(dev, 0, 0, 0, PCIR_COMMAND, val, 2);