Rename hard-coded value 1 << 14 with BGE_RX_CPU_DRV_EVENT.
This bit(SW event 7 in publicly available data sheet) is used to make RX CPU handle a firmware command and the bit is automatically cleared after RX CPU completed the command. Generally firmware command takes the following steps. 1. Write BGE_SRAM_FW_CMD_MB with a command. 2. Write BGE_SRAM_FW_CMD_LEN_MB with the length of the command in bytes. 3. Write BGE_SRAM_FW_CMD_DATA_MB with actual command data. 4. Generate BGE_RX_CPU_EVENT and let firmware handle the command. 5. Wait for the ACK of the firmware command. No functional changes.
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@ -1370,10 +1370,11 @@ bge_stop_fw(struct bge_softc *sc)
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if (sc->bge_asf_mode) {
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bge_writemem_ind(sc, BGE_SRAM_FW_CMD_MB, BGE_FW_CMD_PAUSE);
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CSR_WRITE_4(sc, BGE_RX_CPU_EVENT,
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CSR_READ_4(sc, BGE_RX_CPU_EVENT) | (1 << 14));
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CSR_READ_4(sc, BGE_RX_CPU_EVENT) | BGE_RX_CPU_DRV_EVENT);
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for (i = 0; i < 100; i++ ) {
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if (!(CSR_READ_4(sc, BGE_RX_CPU_EVENT) & (1 << 14)))
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if (!(CSR_READ_4(sc, BGE_RX_CPU_EVENT) &
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BGE_RX_CPU_DRV_EVENT))
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break;
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DELAY(10);
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}
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@ -4111,7 +4112,8 @@ bge_asf_driver_up(struct bge_softc *sc)
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bge_writemem_ind(sc, BGE_SRAM_FW_CMD_LEN_MB, 4);
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bge_writemem_ind(sc, BGE_SRAM_FW_CMD_DATA_MB, 3);
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CSR_WRITE_4(sc, BGE_RX_CPU_EVENT,
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CSR_READ_4(sc, BGE_RX_CPU_EVENT) | (1 << 14));
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CSR_READ_4(sc, BGE_RX_CPU_EVENT) |
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BGE_RX_CPU_DRV_EVENT);
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}
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}
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}
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@ -1901,6 +1901,8 @@
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#define BGE_EE_DELAY 0x6848
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#define BGE_FASTBOOT_PC 0x6894
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#define BGE_RX_CPU_DRV_EVENT 0x00004000
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/*
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* NVRAM Control registers
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*/
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