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e1000: modify HW level time sync mechanisms

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Add additional configuration space access to allow HW
level time sync mechanism.

Signed-off-by: Evgeny Efimov <evgeny.efimov@intel.com>
Signed-off-by: Guinan Sun <guinanx.sun@intel.com>
Reviewed-by: Wei Zhao <wei.zhao1@intel.com>

Approved by:	imp
Obtained from:	DPDK (d53391f1fe2e0eba8818517fdf285f893d95dcc8)
MFC after:	1 week
This commit is contained in:
Guinan Sun 2020-07-06 08:12:04 +00:00 committed by Kevin Bowling
parent 6c59e1866c
commit d50f362b50
2 changed files with 20 additions and 0 deletions
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18
sys/dev/e1000/e1000_ich8lan.c
View File

@ -4963,6 +4963,7 @@ static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
u16 kum_cfg; u16 kum_cfg;
u32 ctrl, reg; u32 ctrl, reg;
s32 ret_val; s32 ret_val;
u16 pci_cfg;
DEBUGFUNC("e1000_reset_hw_ich8lan"); DEBUGFUNC("e1000_reset_hw_ich8lan");
@ -5023,11 +5024,28 @@ static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
e1000_gate_hw_phy_config_ich8lan(hw, TRUE); e1000_gate_hw_phy_config_ich8lan(hw, TRUE);
} }
ret_val = e1000_acquire_swflag_ich8lan(hw); ret_val = e1000_acquire_swflag_ich8lan(hw);
/* Read from EXTCNF_CTRL in e1000_acquire_swflag_ich8lan function
* may occur during global reset and cause system hang.
* Configuration space access creates the needed delay.
* Write to E1000_STRAP RO register E1000_PCI_VENDOR_ID_REGISTER value
* insures configuration space read is done before global reset.
*/
e1000_read_pci_cfg(hw, E1000_PCI_VENDOR_ID_REGISTER, &pci_cfg);
E1000_WRITE_REG(hw, E1000_STRAP, pci_cfg);
DEBUGOUT("Issuing a global reset to ich8lan\n"); DEBUGOUT("Issuing a global reset to ich8lan\n");
E1000_WRITE_REG(hw, E1000_CTRL, (ctrl | E1000_CTRL_RST)); E1000_WRITE_REG(hw, E1000_CTRL, (ctrl | E1000_CTRL_RST));
/* cannot issue a flush here because it hangs the hardware */ /* cannot issue a flush here because it hangs the hardware */
msec_delay(20); msec_delay(20);
/* Configuration space access improve HW level time sync mechanism.
* Write to E1000_STRAP RO register E1000_PCI_VENDOR_ID_REGISTER
* value to insure configuration space read is done
* before any access to mac register.
*/
e1000_read_pci_cfg(hw, E1000_PCI_VENDOR_ID_REGISTER, &pci_cfg);
E1000_WRITE_REG(hw, E1000_STRAP, pci_cfg);
/* Set Phy Config Counter to 50msec */ /* Set Phy Config Counter to 50msec */
if (hw->mac.type == e1000_pch2lan) { if (hw->mac.type == e1000_pch2lan) {
reg = E1000_READ_REG(hw, E1000_FEXTNVM3); reg = E1000_READ_REG(hw, E1000_FEXTNVM3);

2
sys/dev/e1000/e1000_ich8lan.h
View File

@ -327,6 +327,8 @@
#define E1000_SVCR_OFF_TIMER_SHIFT 16 #define E1000_SVCR_OFF_TIMER_SHIFT 16
#define E1000_SVT_OFF_HWM_MASK 0x0000001F #define E1000_SVT_OFF_HWM_MASK 0x0000001F
#define E1000_PCI_VENDOR_ID_REGISTER 0x00
void e1000_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw, void e1000_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
bool state); bool state);
void e1000_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw); void e1000_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw);