a UMA zone instead. This should eliminate a bit of the locking
overhead associated with with malloc and reduce the memory
consumption associated with each new state.
Reviewed by: rwatson, andre
Silence on: ipfw@
MFC after: 1 week
second; since the default hz has changed to 1000 times a second,
this resulted in unecessary work being performed.
MFC after: 2 weeks
Discussed with: phk, cperciva
General head nod: silby
ServeRAID 4 - 7 models right now. Support for older cards is possible, but
I don't have any hardware to experiment with.
Thanks to Jack Hammer at Adaptec for providing debugging hints.
Sponsored by: ImproWare AG, Switzerland
sb_state shouldn't be erased, when socket buffer is flushed by sorflush().
When sb_state was bzero'ed, a recently set SBS_CANTRCVMORE flag was cleared.
If a socket was shutdown(SHUT_RD), a subsequent read() would block on it.
Reported by: Ed Maste, Gerrit Nagelhout
Reviewed by: rwatson
o Disable ofw_console(4), sab(4) and zs(4).
sab(4) and zs(4) are disabled because the hardware controlled by
them is handled by uart(4)+puc(4) and the latter combination is
functionally complete and up to date.
ofw_console(4) is disabled because it doesn't claim the device it
controls (through OFW) and thus interferes with puc(4)+uart(4),
which has sufficient knowledge to extract the necessary information
from OFW to setup the console. Put differently, ofw_console(4) is
not a proper device driver and can only do harm. Its functionality
is completely handled by uart(4).
This commit makes uart(4) the default driver for serial ports.
MFC after: 2 weeks
engineering the pending interrupt sources from the current
state of the controller. For channel A we can always read the
interrupt pending register (RR3). For channel B we can read
the interrupt vector register (RR2) because it contains the
modified vector and thus includes the interrupt source.
Since we currently need puc(4) for the Z8530, we know that
the interrupt handler for both channels will be called and
thus that RR3 will always be read at least once, even if ch A
has no pending interrupt.
NOTE: The modified interrupt vector has no value that represent
a lack of pending interrupt for channel B. That is, the
value read when no interrupts are pending is the same as the
value for the special receive condition. Fortunately, we don't
actually have to depend on that interrupt source. This does
mean that we need to properly handle the overflow condition,
when we read received character from the chip.
o The DSR signal is represented by the SYNC bit in the external
status register (RR0). We now properly track DSR.
o It's save to enable the external/status interrupt source. We
now get interrupts when line signals (DSR, DCD or CTS) change.
Problems fixes:
o interrupt storms.
o blocked open(2).
o lack of (hardware) flow control.
o unable to report DSR.
MFC after: 5 days
providing special version of CDIOCREADSUBCHANNEL ioctl(), which assumes that
result has to be placed into kernel space not user space. In the long run
more generic solution has to be designed WRT emulating various ioctl()s
that operate on userspace buffers, but right now there is only one such
ioctl() is emulated, so that it makes little sense.
MFC after: 2 weeks
copies arguments into the kernel space and one that operates
completely in the kernel space;
o use kernel-only version of execve(2) to kill another stackgap in
linuxlator/i386.
Obtained from: DragonFlyBSD (partially)
MFC after: 2 weeks
called in "open", causing mmap() to fail.
Where possible, pass size of file to vnode_create_vobject() rather
than having it find it out the hard way via VOP_LOOKUP
Reviewed by: phk
Add minor2unit() in addition to dev2unit() and unit2minor().
If it wasn't such a hazzle we should redefine minor numbers in
the kernel without the gap for the major number, but it's not worth
the bother (yet).
