Commit Graph

230 Commits

Author SHA1 Message Date
Warner Losh
24646e120c Bring in cdefs.h from NetBSD to define ABI goo.
Obtained from:	NetBSD
2009-07-05 08:14:00 +00:00
Warner Losh
0d978536b2 Pull in machine/cdefs.h for the ABI definitions. Provide a PTR_LA,
ala sgi, and use it in preference to a bare 'la' so that it gets
translated to a 'dla' for the 64-bit pointer ABIs.
2009-07-05 08:13:19 +00:00
Warner Losh
f547073088 Use uintptr_t rather than unsigned here for 64-bit correctness. 2009-07-05 07:01:34 +00:00
Warner Losh
da96ff5dae Define __ELF_WORD_SIZE appropriately for n64. Note for N32 I believe
this is correct.  While registers are 64-bit, n32 is a 32-bit ABI and
lives in a 32-bit world (with explicit 64-bit registers, however).
Change an 8, which was 4 + 4 or sizeof(int) + SZREG to be a simple '4
+ SZREG' to reflect the actual offset of the structure in question.
2009-07-05 07:00:51 +00:00
Warner Losh
64003afe2e (1) Use uintptr_t in preference to unsigned. The latter isn't right for
64-bit case, while the former is.

(2) include a SB1 specific coherency mapping

Submitted by:	Neelkanth Nath (2)
2009-07-05 06:56:51 +00:00
Warner Losh
220d1e7fb0 Go for broke: configure this to build mips64 N64 binary. 2009-07-05 06:49:56 +00:00
Warner Losh
bca296cba8 Publish PAGE_SHIFT to assembler
# we should likely phase out PGSHIFT

Submitted by:	Neelkanth Natu
2009-07-05 06:46:54 +00:00
Warner Losh
4ecfc54d9d db_expr_t should be a intptr_t, not an int. These expressions can be
addresses or numbers, and that's a intptr_t if I ever saw one.
2009-07-05 06:44:37 +00:00
Warner Losh
6855d90580 Define COP0_SYNC for SB1 CPU.
Submitted by:	Neelkanth Natu
2009-07-05 06:43:01 +00:00
Warner Losh
2c1c8bb345 Switch to ABI agnostic ta0-ta3. Provide defs for this in the right
places.  Provide n32/n64 register name defintions.  This should have
no effect for the O32 builds that everybody else uses, but should help
make N64 builds possible (lots of other changes are needed for that).

Obtained from:	NetBSD (for the regdef.h changes)
2009-07-05 06:39:37 +00:00
Warner Losh
561a3cc1a1 Move from using the lame invalid address I chose when trying to get
Octeon going...  Turns out that you get tlb shutdowns with this...
Use PGSHIFT instead of PAGE_SHIFT.

Submitted by:	Neelkanth Natu
2009-07-04 03:22:34 +00:00
Warner Losh
f94784e818 Add sibyte device support.
Submitted by:	Neelkanth Natu
2009-07-04 03:05:48 +00:00
Oleksandr Tymoshenko
09c817ba36 - MFC 2009-07-03 04:39:18 +00:00
Warner Losh
ca72c49f42 Fix copyrights to reflect the origin of these files.
Approved by:	re@ (rwatson)
2009-06-29 16:45:50 +00:00
Oleksandr Tymoshenko
fa596cbd83 - Replace casuword and casuword32 stubs with proper implementation 2009-06-28 21:01:00 +00:00
Oleksandr Tymoshenko
00741bfc80 - Add support for handling TLS area address in kernel space.
From the userland point of view get/set operations are
    performed using sysarch(2) call.
2009-06-27 23:27:41 +00:00
Oleksandr Tymoshenko
a79d8960b1 - Make cpu_set_upcall_kse conform MIPS ABI. T9 should be
the same as PC in subroutine entry point
- Preserve interrupt mask
2009-06-27 23:01:35 +00:00
Oleksandr Tymoshenko
5576af82b5 - Add guards to ensure that these files are included only once 2009-06-26 19:54:06 +00:00
Alan Cox
5797795f5a Correct the #endif comment.
Noticed by:	jmallett
Approved by:	re (kib)
2009-06-26 16:22:24 +00:00
Robert Watson
eb956cd041 Use if_maddr_rlock()/if_maddr_runlock() rather than IF_ADDR_LOCK()/
IF_ADDR_UNLOCK() across network device drivers when accessing the
per-interface multicast address list, if_multiaddrs.  This will
allow us to change the locking strategy without affecting our driver
programming interface or binary interface.

For two wireless drivers, remove unnecessary locking, since they
don't actually access the multicast address list.

Approved by:	re (kib)
MFC after:	6 weeks
2009-06-26 11:45:06 +00:00
Alan Cox
e999111ae7 This change is the next step in implementing the cache control functionality
required by video card drivers.  Specifically, this change introduces
vm_cache_mode_t with an appropriate VM_CACHE_DEFAULT definition on all
architectures.  In addition, this changes adds a vm_cache_mode_t parameter
to kmem_alloc_contig() and vm_phys_alloc_contig().  These will be the
interfaces for allocating mapped kernel memory and physical memory,
respectively, with non-default cache modes.

In collaboration with:	jhb
2009-06-26 04:47:43 +00:00
Oleksandr Tymoshenko
77edcd641c - Invalidate cache in pmap_qenter. Fixes corruption of data
that comes through pipe (may be other bugs)
2009-06-25 02:15:04 +00:00
Oleksandr Tymoshenko
790b067725 - Do not use hardcoded uart speed
- Call mips_timer_early_init before initializing uart in order
    to make DELAY usable for ns8250 driver

Submitted by:	Neelkanth Natu
2009-06-24 22:42:52 +00:00
Jeff Roberson
50c202c592 Implement a facility for dynamic per-cpu variables.
- Modules and kernel code alike may use DPCPU_DEFINE(),
   DPCPU_GET(), DPCPU_SET(), etc. akin to the statically defined
   PCPU_*.  Requires only one extra instruction more than PCPU_* and is
   virtually the same as __thread for builtin and much faster for shared
   objects.  DPCPU variables can be initialized when defined.
 - Modules are supported by relocating the module's per-cpu linker set
   over space reserved in the kernel.  Modules may fail to load if there
   is insufficient space available.
 - Track space available for modules with a one-off extent allocator.
   Free may block for memory to allocate space for an extent.

Reviewed by:    jhb, rwatson, kan, sam, grehan, marius, marcel, stas
2009-06-23 22:42:39 +00:00
Oleksandr Tymoshenko
e3ebc7a32e - Keep interrupts mask intact by RESTORE_CPU in MipsKernGenException
trap() function re-enables interrupts if exception happened with
    interrupts enabled and therefor status register might be modified
    by interrupt filters
2009-06-19 19:02:40 +00:00
Oleksandr Tymoshenko
d7766b4586 - Flush PCI register write before delay
Spotted by: Pyun YongHyeon
2009-06-19 05:00:17 +00:00
Oleksandr Tymoshenko
6846a68073 - Mark temp variable as "earlyclobber" in assembler inline in
atomic_fetchadd_32.  Without it gcc would use it as input
    register for v and sometimes generate following code for
    function call like atomic_fetchadd_32(&(fp)->f_count, -1):

801238b4:       2402ffff        li      v0,-1
801238b8:       c2230018        ll      v1,24(s1)
801238bc:       00431021        addu    v0,v0,v1
801238c0:       e2220018        sc      v0,24(s1)
801238c4:       1040fffc        beqz    v0,801238b8 <dupfdopen+0x2e8>
801238c8:       00000000        nop

   Which is definitly wrong because if sc fails v0 is set to 0
   and previous value of -1 is overriden hence whole operation
   turns to bogus
2009-06-19 04:43:49 +00:00
Bjoern A. Zeeb
2aabdeb1f6 Add a .cvsignore file and along with that put an svn:ignore proprty
on the directory like we have for all other target architectures.

Discussed with:	imp (kind of)
2009-06-17 10:48:32 +00:00
Bjoern A. Zeeb
ed34ec5ed8 Make compile again using proper protoypes for
pcib_read/write_config DEVMETHOD.
2009-06-17 10:26:37 +00:00
Bjoern A. Zeeb
23678e67c0 Make compile again using the correct prototype for the
device shutdown method.
2009-06-17 10:23:25 +00:00
Oleksandr Tymoshenko
1a28ce2dcb - Remove debug printfs 2009-06-16 02:36:21 +00:00
Oleksandr Tymoshenko
04af8c86f5 - Handle KSEG0/KSEG1 addresses for /dev/mem as well. netstat requires it 2009-06-16 01:43:33 +00:00
Oleksandr Tymoshenko
8766ab738d - Take into account only unmasked bits in interrupt status register 2009-06-16 00:02:02 +00:00
Oleksandr Tymoshenko
ee58bf3153 - Fix prototypes to make compiler happy 2009-06-14 21:16:23 +00:00
Oleksandr Tymoshenko
d7913bf5ab - Get rid of mask_fn and fix pre_filter/post_filter functions' prototypes 2009-06-14 21:16:04 +00:00
Oleksandr Tymoshenko
1ee48ffda9 - Fix prototype and implementation of admsw_shutdown 2009-06-14 21:04:54 +00:00
Oleksandr Tymoshenko
e3652db0ce - Fix prototypes to make compiler happy 2009-06-14 20:54:46 +00:00
Warner Losh
72bd8c62f6 Minor formatting changes. Also, elimiante a couple of unused variables. 2009-06-14 07:01:22 +00:00
Warner Losh
c839424d34 Various nits to make this compile. 2009-06-14 06:53:55 +00:00
Warner Losh
24277e95bb Make compile. 2009-06-14 06:49:13 +00:00
Warner Losh
67b401589c Hack for the 'battleship' boards that have 8 ports rather than 4. 2009-06-14 06:36:50 +00:00
Warner Losh
bafe55344b Compile out unreferenced code. 2009-06-14 06:35:21 +00:00
Warner Losh
db9c08f280 Stylish nits 2009-06-14 06:35:02 +00:00
Warner Losh
00e1958bd4 Add bogus OCTEON_CORE_ID here. Really should integrate the pcpu.h stuff
that is in Cavium's base port.
2009-06-14 06:27:11 +00:00
Warner Losh
2e24c40fec bye bye. This is no longer referenced, but much code from it will
resurface for a bus-space implementation.
2009-06-14 06:14:25 +00:00
Warner Losh
78e0ef6f04 Kludge: pretend to be ISA_MIPS32 for the moment. 2009-06-14 06:12:21 +00:00
Warner Losh
2acee4de5c First pass to make compile. It doesn't completely yet, but it's a
start.
2009-06-14 06:11:51 +00:00
Warner Losh
8c29759b4a Bring back the TARGET_OCTEON kludge for a bit. We need to kill it,
but it is useful for the moment.
2009-06-14 06:11:13 +00:00
Warner Losh
55f888f68d Cavium-specific goo is no longer necessary here. Of course, I now
have to write a bus space for cavium, but that shouldn't be too hard.
2009-06-14 06:10:36 +00:00
Warner Losh
29854186d2 Move octeon specific uart goo here, per SOP for other MIPS ports. 2009-06-14 06:09:33 +00:00