Commit Graph

135 Commits

Author SHA1 Message Date
Dimitry Andric
29658c96ce Remove duplicate const specifiers in many drivers (I hope I got all of
them, please let me know if not).  Most of these are of the form:

static const struct bzzt_type {
	[...list of members...]
} const bzzt_devs[] = {
	[...list of initializers...]
};

The second const is unnecessary, as arrays cannot be modified anyway,
and if the elements are const, the whole thing is const automatically
(e.g. it is placed in .rodata).

I have verified this does not change the binary output of a full kernel
build (except for build timestamps embedded in the object files).

Reviewed by:	yongari, marius
MFC after:	1 week
2012-11-05 19:16:27 +00:00
Alexander Motin
23d9e39c1a Implement CAM_ATAIO_NEEDRESULT (fetching full set of result registers) for
ata(4) driver in ATA_CAM mode.  That slighty improves error reporting and
also should fix `smartctl -l scterc /dev/adaX` operation.

MFC after:	3 weeks
2012-10-26 20:03:08 +00:00
Alexander Motin
49a4a59a54 Add IDs for JMicron JMB360/JMB362 AHCI SATA controllers.
MFC after:	1 week
2012-08-30 15:23:59 +00:00
Eitan Adler
029b129de8 Remove variables which are initialized but never used thereafter
reported by gcc46 warning

Approved by:	cperciva
MFC after:	1 week
2012-07-07 17:20:52 +00:00
Marius Strobl
70254ea2cb - As a baind-aid, disable ATAPI DMA when using ATA_CAM for these controllers
as well as it causes the kernel to hang during boot.
  Reported and tested by: Kevin Oberman
- Use NULL instead of 0 for a pointer.

MFC after:	3 days
2012-06-14 22:19:23 +00:00
Marius Strobl
5187458fcd - First pass at const'ifying ata(4) as appropriate.
- Use DEVMETHOD_END.
- Use NULL instead of 0 for pointers

MFC after:	1 week
2012-03-21 16:59:39 +00:00
Marius Strobl
812e6f1cf5 Remove remnants of ATA_LOCKING uses in the ATA_CAM case and wrap it
along with functions, SYSCTLs and tunables that are not used with
ATA_CAM in #ifndef ATA_CAM, similar to the existing #ifdef'ed ATA_CAM
code for the other way around. This makes it easier to understand
which parts of ata(4) actually are used in the new world order and
to later on remove the !ATA_CAM bits. It also makes it obvious that
there is something fishy with the C-bus front-end as well as in the
ATP850 support, as these used ATA_LOCKING which is defunct in the
ATA_CAM case. When fixing the former, ATA_LOCKING probably needs to
be brought back in some form or other.

Reviewed by:	mav
MFC after:	1 week
2012-03-21 08:57:15 +00:00
Alexander Motin
9364490242 Fix names of some Marvell SATA chips. It looks like chips with proprietary
interface supported by mvs(4) are 88SX, while AHCI-like chips are 88SE.

PR:		kern/165271
Submitted by:	Jia-Shiun Li <jiashiun@gmail.com>
MFC after:	1 week
2012-03-02 08:49:07 +00:00
Marius Strobl
c7edae4bc2 Using ATA_CAM along with ATAPI DMA causes data corruption with ALI_NEW
and CMD controllers for reasons unknown so disable it.

PR:	164226
2012-01-27 21:52:59 +00:00
Ulrich Spörlein
9a14aa017b Convert files to UTF-8 2012-01-15 13:23:18 +00:00
Jim Harris
9bea89c1b0 Add 0x2826 device ID for C600 (Patsburg) SATA controller in RAID mode.
Reviewed by: mav
Approved by: scottl
2012-01-06 00:22:55 +00:00
Alexander Motin
dd3ebdba6f Add PCI IDs for the Intel ICH9M SATA controllers.
MFC after:	2 weeks
2011-12-14 13:12:55 +00:00
Alexander Motin
c8973d9e6c Add hw.ahci.force tunable to control whether AHCI drivers should attach
to known AHCI-capable chips (AMD/NVIDIA), configured for legacy emulation.

Enabled by default to get additional performance and functionality of AHCI
when it can't be enabled by BIOS. Can be disabled to honor BIOS settings if
needed for some reason.

MFC after:	1 month
2011-12-02 12:52:33 +00:00
Marius Strobl
741d3d922c In r225931 I've missed the only other driver using the pointer returned
by rman_get_virtual(9) to access device registers sparc64 currently cares
about.
Ideally ata(4) should just be converted to access these using bus_space(9)
read/write functions instead as there's really no reason to do it the
former way. However, this part of ata-siliconimage.c should go away in
favor of siis(4) sooner or later anyway and I don't have the hardware to
actually test the SX4 bits of ata-promise.c.
Also ideally the other architectures should also properly handle the
BUS_SPACE_MAP_LINEAR flag of bus_space_map(9) so this code wouldn't need
to be #ifdef'ed.
2011-11-01 17:57:21 +00:00
Alexander Motin
df6f430410 Do not force AHCI mode on NVIDIA MCP89 SATA controllers. Recent Apple
Mac with this chipset does not initialize AHCI mode unless it is started
from EFI loader.  However, legacy ATA mode works.

Submitted by:	jkim@ (original version)
Approved by:	re (kib)
MFC after:	1 week
2011-08-02 11:07:47 +00:00
Alexander Motin
dd60e051f7 - Use mutex to serialize index/data register pair usage, when
accessing SATA registers. Unserialized access under heavy load caused
wrong speed reporting and potentially could cause device loss.
 - To free memory and other resources (including above), allocated
during chipinit() method call on attach, add new chipdeinit() method,
called during driver detach.

Submitted by:   Andrew Boyer <aboyer@averesystems.com> (initial version)
Approved by:	re (kib)
MFC after:	1 week
2011-07-22 16:37:04 +00:00
Alexander Motin
e292b310e9 Skip BAR(5) usage for SATA registers access on ICH8M Apples, because for
some reason it causes system lock up. Linux does the same.

MFC after:	1 week
2011-06-14 20:30:15 +00:00
Jack F Vogel
73e3bb6563 Chipset support for the new Intel Panther Point PCH, thanks
to Seth Heasley for preparing the changes.
2011-05-11 20:31:27 +00:00
Alexander Motin
c7dd7de64d According to ATA specifications, when ATAPI master is the only device, it
should respond with all zeroes to any access to slave registers. Test with
PATA devices confirmed such behavior. Unluckily, Intel SATA controllers in
legacy emulation mode behave differently, not making any difference between
ATA and ATAPI devices. It causes false positive slave device detection and,
as result, command timeouts.

To workaround this problem, mask result of legacy-emulated soft-reset with
the device presence information received from the SATA-specific registers.
2011-04-21 20:56:34 +00:00
Alexander Motin
53479021ba - Fix mapping of the last two SATA ports on 6-port Intel controllers.
This improves hard-reset and hot-plug on these ports.
 - Device with ID 0x29218086 is a 2-port variant of ICH9 in legacy mode.
Skip probing for nonexistent slave devices there.
2011-04-21 11:44:16 +00:00
Marius Strobl
20359f8025 Add missing bus_dmamap_sync() calls for the work DMA map.
MFC after:	2 weeks
2011-03-06 13:08:25 +00:00
Marius Strobl
c3719ff443 Add missing bus_dmamap_sync() calls for the work DMA map.
MFC after:	2 weeks
2011-03-06 13:06:41 +00:00
Jack F Vogel
bf0477b215 Support for the new Patsburg PCH chipset:
- SMBus Controller
     - SATA Controller
     - HD Audio Controller
     - Watchdog Controller

Thanks to Seth Heasley (seth.heasley@intel.com) for providing us code.

MFC after 3 days
2011-02-01 01:05:11 +00:00
Jack F Vogel
d5267ede37 Support for the new DH89xxCC PCH chipset including:
- SATA controller
      - Watchdog timer
      - SMBus controller
2011-01-31 18:41:52 +00:00
Alexander Motin
f1bfc8aba8 ICH7 SATA controller in legacy mode can provide access to SATA registers
via AHCI-like memory resource at BAR(5). Use it if BIOS was so kind to
allocate memory for that BAR. This allows hot-plug support and connection
speed reporting.

MFC after:	2 weeks
2011-01-24 09:24:20 +00:00
Marius Strobl
1510a2b019 Several chipset drivers alter parameters relevant for the DMA tag creation,
i.e. alignment, max_address, max_iosize and segsize (only max_address is
thought to have an negative impact regarding this issue though), after
calling ata_dmainit() either directly or indirectly so these values have
no effect or at least no effect on the DMA tags and the defaults are used
for the latter instead. So change the drivers to set these parameters
up-front and ata_dmainit() to honor them.

Reviewd by:	mav
MFC after:	1 month
2010-11-28 18:53:29 +00:00
Alexander Motin
8a1d183fb7 Do hard reset before soft reset for SATA channels. Soft reset reported to be
not enough to restore device readiness in some situations.

Tested by: 	Roger Hammerstein <cheeky.m@live.com> on ServerWorks HT1000.
2010-11-27 07:03:31 +00:00
Alexander Motin
1f6aa21d47 Record that there is no devices if SATA reset found none. 2010-11-18 10:34:18 +00:00
Alexander Motin
ee597c8246 Some VIA SATA controllers provide access to non-standard SATA registers via
PCI config space. Use them to implement hot-plug and link speed reporting.
Tested on ASRock PV530 board with VX900 chipset.
2010-11-18 08:03:40 +00:00
Alexander Motin
2cbfd42740 Add IDs for VIA VX900 chipset SATA controller.
MFC after:	1 week
2010-11-17 16:17:35 +00:00
Alexander Motin
82d2b37bc0 Remove stale line, accidentally slipped into r214016.
MFC after:	3 days
2010-11-02 09:31:24 +00:00
Alexander Motin
bda55b6adb Set of legacy mode SATA enchancements:
- Implement proper combined mode decoding for Intel controllers to properly
identify SATA and PATA channels and associate ATA channels with SATA ports.
This fixes wrong reporting and in some cases hard resets to wrong SATA ports.
- Improve SATA registers support to handle hot-plug events and potentially
interface errors. For ICH5/6300ESB chipsets these registers accessible via
PCI config space. For later ones they may be accessible via PCI BAR(5).
- For controllers not generating interrupts on hot-plug events, implement
periodic status polling. Use it to detect hot-plug on Intel and VIA
controllers. Same probably could also be used for Serverworks and SIS.
2010-10-18 11:30:13 +00:00
Alexander Motin
ba8834a379 Revert r132291.
Restore setting PIO/WDMA timings for VIA UDMA133 controllers.
Linux disables only AST register writing there, but no all timings.
2010-09-30 16:09:52 +00:00
Alexander Motin
433d4558c1 Add missing le32toh(), same as recently done in ata-siliconimage.c. 2010-09-24 07:14:14 +00:00
Jayachandran C.
831826341b Add missing byteswap, works on big endian systems now (tested on Netlogic
XLS MIPS processor).

Submitted by:	Sreekanth M. S. <kanthms at netlogicmicro dot com>
Reviewed by:	mav
2010-09-23 05:17:36 +00:00
Nathan Whitehorn
c14e163ad1 Fix a problem where device detection would work unreliably on Serverworks
K2 SATA controllers. The chip's status register must be read first, and
as a long, for other registers to be correctly updated after a command, and
this includes the command sequence in device detection as well as the
previously handled case after interrupts. While here, clean up some
previous hacks related to this controller.

Reported by:	many
Reviewed by:	mav
MFC after:	3 weeks
2010-09-09 13:17:30 +00:00
Alexander Motin
a6c48c7c72 Add fix for SiI3114 and SiI3512 chips bug, which caused sending R_ERR in
response to DMA activate FIS under certain circumstances. This is
recommended fix from chip datasheet. If triggered, this bug most likely
cause write command timeout.

MFC after:	2 weeks
2010-09-02 12:32:29 +00:00
Alexander Motin
a250a687f7 SATA1.x SiliconImage controllers on power-on reset TFD Status register into
value 0xff. On hot-plug this value confuses ata_generic_reset() device
presence detection logic. As soon as we already know drive presence from
SATA hard reset, hint ata_generic_reset() to wait for device signature
until success or full timeout.
2010-09-02 11:18:43 +00:00
Alexander Motin
901c71c704 Increase device reset timeout from 10 to 15 seconds, same as in ahci(4).
Some devices found need about 10-12 seconds to spinup.
2010-09-01 06:43:41 +00:00
Alexander Motin
bfc8500c34 Add Intel Cougar Point PCH SATA Controller DeviceIDs. Correct some existing
entries for Intel Ibex Peak (5 Series/3400 Series) PCH SATA controllers.

Submitted by:	jfv@
MFC after:	1 week
2010-08-28 07:10:51 +00:00
Alexander Motin
aecfe194a9 If ata_sata_phy_reset() failed and ata_generic_reset() is not called, mark
channel as having no devices connected. This improves hot-unplug operation
on legacy-emulating SATA controllers.
2010-07-10 15:36:27 +00:00
Alexander Motin
9a9bce34f1 Make hw.ata.ata_dma_check_80pin tunable affect not only device side, but
also controller side cable checks. Make respective sysctl writable.

PR:		kern/143462
2010-07-10 13:46:14 +00:00
Nathan Whitehorn
7248ea35ca Following r209299, level interrupts are low by default on PPC, so remove
the hack here to reprogram the interrupt for K2 SATA devices.
2010-06-18 14:17:45 +00:00
Nathan Whitehorn
351129c7bb Some revisions of the Serverworks K2 SATA controller have a data
corruption bug where if an ATA command is issued before DMA is started,
data will become available to the controller before it knows what to do
with it. This results in either data corruption or a controller crash.

This patch remedies the problem by adopting the workaround employed
by Linux and Darwin: starting the DMA engine prior to sending the ATA
command.

Observer on:	Xserve G5
Reviewed by:	mav
MFC after:	1 week
2010-06-06 14:09:48 +00:00
Nathan Whitehorn
33520e90b2 Correct the comment. We now use level low instead of edge high for this
interrupt.
2010-06-05 16:27:15 +00:00
Nathan Whitehorn
ff6f4d01f1 Partially revert r208162 while waiting for review on a more comprehensive
fix. On Apple OpenPICs, the low/high bit of the interrupt sense is only
respected for interrupt 0. We currently erroneously program all OpenPIC
interrupts level high instead of level low by default, which only matters
for some G5 systems where the SATA controllers use IRQ 0.

This change is a quick fix that will be reverted once the effect of
changing the default interrupt sense on embedded systems is known.

MFC after:	3 days
2010-06-05 16:25:25 +00:00
Alexander Motin
c25d9e1d96 Fix use after free on error.
Found with:   Coverity Prevent(tm)
CID:          4722
2010-06-05 08:44:40 +00:00
Alexander Motin
6ee9deb145 Fix PCH chipset IDs. They are 0x3bxx, not 0x3axx.
Pointy hat to:	me
2010-06-04 07:35:59 +00:00
Nathan Whitehorn
4dea0435b5 Relocate interrupt sense setting for K2 SATA from the ATA driver to the
OFW PCI layer and read the sense directly from the device tree instead
of guessing.

MFC after:	1 week
2010-05-16 17:55:09 +00:00
Alexander Motin
b9f59cca0d For early ALI chips do not announce I/O sizes that require unsupported
48bit DMA commands.
2010-04-14 15:29:32 +00:00