Commit Graph

24108 Commits

Author SHA1 Message Date
John Baldwin
2cfd0c4638 - Add some registers defined in PCI 3.0 including new AER bits.
- Add constants for the rest of the fields in the PCI-express device
  capability and control registers.
- Tweak some of the recently added PCI-e capability constants (always
  use hex for offsets in config space, and include a shortened
  version of the relevant register in the name of field constants).

MFC after:	1 week
2012-09-13 19:05:24 +00:00
Adrian Chadd
9b967f5d12 Don't use AR_PHY_MODE to setup half/quarter rate.
I'm not sure where in the deep, distant past I found the AR_PHY_MODE
registers for half/quarter rate mode, but unfortunately that doesn't
seem to work "right" for non-AR9280 chips.

Specifically:

* don't touch AR_PHY_MODE
* set the PLL bits when configuring half/quarter rate

I've verified this on the AR9280 (5ghz fast clock) and the AR5416.

The AR9280 works in both half/quarter rate; the AR5416 unfortunately
only currently works at half rate.  It fails to calibrate on quarter rate.
2012-09-13 18:24:13 +00:00
Eitan Adler
2bfb8a83f6 Define missing DEBUGOUT# macros. DEBUGOUT[45] are not yet used but are
being defined pre-emptively to avoid future build breakage

PR:		kern/168967
Submitted by:	fuzhli <fuzl@arraynetworks.com.cn>
Approved by:	cperciva
MFC after:	1 week
2012-09-13 14:40:24 +00:00
Konstantin Belousov
c5e3d0ab11 Rename the IVY_RNG option to RDRAND_RNG.
Based on submission by:	Arthur Mesh <arthurmesh@gmail.com>
MFC after:	2 weeks
2012-09-13 10:12:16 +00:00
Navdeep Parhar
8a599c0859 Install interrupt handlers early, during attach, for the reason
explained in r239913 by jhb.

MFC after:	1 week
2012-09-13 09:18:13 +00:00
Navdeep Parhar
57c60f98b8 Use native FreeBSD facilities everywhere except the shared code in common/
MFC after:	1 week
2012-09-13 09:10:10 +00:00
Adrian Chadd
03a51ef8f4 Enable fractional 5G mode on half/quarter rate channels.
Obtained from:	Linux ath9k
2012-09-13 07:25:41 +00:00
Adrian Chadd
77ffc4c1fc Flip on half/quarter rate support.
No, this isn't HT/5 and HT/10 support.  This is the 11a half/quarter
rate support primarily used by the 4.9GHz and GSM band regulatory
domains.

This is definitely a work in progress.

TODO:

* everything in the last commit;
* lots more interoperability testing with the AR5212 half/quarter rate
  support for the relevant chips;
* Do some interop testing on half/quarter rate support between _all_
  the 11n chips - AR5416, AR9160, AR9280 (and AR9285/AR9287 when 2GHz
  half/quarter rate support is coded up.)
2012-09-13 07:24:14 +00:00
Adrian Chadd
ce801478d2 Introduce an AR5416 flavour of the IFS and mac usec/timing configuration
used when running the chips in half/quarter rate.

This sets up some default parameters which are then overridden by the
driver (which manually configures things like slot timing at interface
start time.)

Although this is a copy-and-modify from the AR5212 HAL, I did peek
at the reference HAL and the ath9k driver to see what they did.
Ath9k in particular doesn't hard-code this - instead, their version
of ar5416InitUserSettings() does all of the relevant math.

TODO:

* do the math, not hard code things!
* fix the mac clock calculation for the AR9287; since it runs the
  MAC clock at a higher rate, requiring all the duration calculations
  to change;
* Do a whole lot more validation for half/quarter rates.

Obtained from:	Qualcomm Atheros, Linux ath9k
2012-09-13 07:22:40 +00:00
Adrian Chadd
41b53a9aaf Call the ar5212SetCoverageClass() function for now.
Some of the math is a little wrong thanks to clocks in 11a mode running
at 44MHz when in fast clock mode (rather than 40MHz, which the chips
before AR9280 ran 11a in).  That'll have to be addressed in a future commit.
2012-09-13 07:19:53 +00:00
Adrian Chadd
c19a7918f3 Add register defintions for the AR5416 TX/RX latency fields.
Obtained from:	Qualcomm Atheros
2012-09-13 07:17:58 +00:00
Adrian Chadd
1690edb32c Compensate for half/quarter rate differences in MAC clock speed.
This fixes the incorrect slot (and likely ACK/RTS timeout) values
which I see when enabling half/quarter rate support on the AR9280.

The resulting math matches the expected calculated default values.
2012-09-13 07:17:29 +00:00
Navdeep Parhar
8a7ba352b0 Update interface to firmware 1.6.2 and include the firmware in the driver.
Obtained from:	Chelsio
MFC after:	1 week
2012-09-13 06:32:52 +00:00
Peter Grehan
60ff334285 No need to leak these into the includer's namespace.
Submitted by:	Bryan Venteicher bryanv at daemoninthecloset org
2012-09-13 00:42:56 +00:00
Peter Grehan
c44ef550e1 Relax requirement of certain mb()s
Submitted by:	Bryan Venteicher bryanv at daemoninthecloset org
2012-09-13 00:36:46 +00:00
Hans Petter Selasky
beefefd4b0 Fix TX FIFO sizes. Correct FIFO handling in Host mode. 2012-09-12 19:15:29 +00:00
Alexander Motin
189d85cc15 Fix AHCI 1.2 version checks. This should be mostly cosmetic.
Submitted by:	Dmitry Luhtionov <dmitryluhtionov@gmail.com>
MFC after:	1 week
2012-09-12 09:20:37 +00:00
Kevin Lo
92665d2b55 Restart the USB transfer if the error is not USB_ERR_CANCELLED. 2012-09-12 07:59:28 +00:00
Hans Petter Selasky
d4b6c03ea9 Reduce DWC OTG polling rate by using the SOF interrupt. 2012-09-12 07:34:09 +00:00
Hans Petter Selasky
537aca954f Fix missing parts of DWC OTG host mode support. The host mode support
of the DWC OTG is very simple in PIO mode, and we need to re-transmit
data when NAK is received among other things. We probably will need
to implement some kind of rate limitation on the NAK-ing.
2012-09-11 22:08:19 +00:00
Andriy Gapon
31482433f4 revert r240344: cpu_devices[] is used in other functions and must be kept
Reported by:	gjb, glebius
Pointyhat to:	avg
MFC after:	1 day
X-MFC note:	fake MFC, reminder to never MFC r240344
2012-09-11 17:21:25 +00:00
Scott Long
a46570c76d Remove a prefetch() directive that, after careful testing, does more harm
than good.

Submitted by:	Fabien Thomas
Reviewed by:	jfv
2012-09-11 16:59:04 +00:00
Andriy Gapon
ccb92b3c78 acpi_cpu: free result of device_get_children
MFC after:	1 week
2012-09-11 06:26:20 +00:00
Adrian Chadd
5d9b19f731 Clear the correct descriptor when going through the chained together
gather DMA descriptor list.

Pointy hat to: adrian@, for even USING bf->bf_desc here instead of 'ds'.
2012-09-11 04:11:42 +00:00
John Baldwin
a89828a2b0 Remove some more NetBSD compat shims and other unused bits from these
drivers:
- Remove scsi_low_pisa.*, they were unused.
- Remove <compat/netbsd/physio_proc.h> and calls to the stubs in that
  header.  They were empty nops.
- Retire sl_xname and use device_get_nameunit() and device_printf() with
  the underlying device_t instead.
- Remove unused {ct,ncv,nsp,stg}print() functions.
- Remove empty SOFT_INTR_REQUIRED() macro and the unused sl_irq member.
2012-09-10 18:49:49 +00:00
Hans Petter Selasky
e828eaabf4 Poll VBUS status every second, hence the AT91 GPIO library doesn't support
registering interrupt handlers yet for GPIO events.
2012-09-10 13:50:34 +00:00
Hans Petter Selasky
460febc7be Fix for IRQ hang in DWC OTG host mode. 2012-09-10 12:23:56 +00:00
Hans Petter Selasky
92a80a4cef Cleanup interrupt handling in Host Mode. 2012-09-10 08:23:56 +00:00
Alexander Motin
df980c683c At least from A70M FCH chipsets AMD started to use their real vendor ID
(1022) in HPET. But according to report they still haven't fixed problem
with level-triggered interrupts.
Make workaround used for earlier chipsets apply to this new ID also.

PR:		amd64/171355
MFC after:	3 days
2012-09-09 20:00:00 +00:00
Hans Petter Selasky
58ecbe49f5 Implement missing USB suspend and resume support for DWC OTG driver. 2012-09-09 17:23:57 +00:00
Hans Petter Selasky
268ae63a2a Add support for DWC OTG. 2012-09-09 14:53:34 +00:00
Hans Petter Selasky
9cfd07315e Add support for host mode to the DWC OTG controller driver.
The DWC OTG host mode support should still be considered
experimental. Isochronous support for DWC OTG is not
fully implemented. Some code added derives from
Aleksandr Rybalko's dotg.c driver.
2012-09-09 14:41:34 +00:00
Adrian Chadd
21840808c8 Make sure the aggregate fields are properly cleared - both in the
ath_buf and when forming a non-aggregate frame.

The non-11n setds function is called when TXing aggregate frames (and
yes, I should fix this!) and the non-11n TX aggregation code doesn't clear
the delimiter field.  I figure it's nicer to do that.
2012-09-09 05:06:16 +00:00
Adrian Chadd
a71362cec6 Remove TDMA #define entries from if_ath.c; they now exist in if_ath_tdma.h. 2012-09-09 04:53:10 +00:00
Adrian Chadd
76af1a93c9 Correctly mask out the RTS/CTS flags when forming aggregates.
This had the side effect of clearing HAL_TXDESC_CLRDMASK for a bunch of
frames, meaning they'd end up being potentially filtered if there were
an error.  This is fine in the previous world as they'd just be
software retried but now that I'm working on filtered frames, these
descriptors would be endlessly retried until another valid frame would
come along that had CLRDMASK set.
2012-09-08 02:56:09 +00:00
Matt Jacob
10bf42c215 Remove useless extra test.
Pointed out by:	Sascha of DragonFly BSD
MFC after:	2 weeks
2012-09-07 22:45:31 +00:00
John Baldwin
ecbb462c38 Use callout(9) instead of timeout(9) to manage timers. 2012-09-07 19:42:36 +00:00
Xin LI
a8bc743735 It seems that what the code really meant is that when a write is completed,
do a BUS_DMASYNC_POSTWRITE over the DMA map.  The way it currently is would
only do POSTREAD for read transactions.

Submitted by:	Sascha Wildner
MFC after:	1 month
2012-09-07 19:00:27 +00:00
John Baldwin
51ba7b6f3e Remove remaining 4.x compat shims. No resulting changes (verified by
md5).
2012-09-07 18:41:19 +00:00
Fabien Thomas
35db642499 Complete and merge the list between Sandy/Ivy bridge of events
that can run on specific PMC.

MFC after:	1 month
2012-09-07 14:45:59 +00:00
Adrian Chadd
2a9f83af64 Ensure that single-frame aggregate session frames are retransmitted
with the correct configuration.

Occasionally an aggregate TX would fail and the first frame would be
retransmitted as a non-AMPDU frame.  Since bfs_aggr=1 and bfs_nframes > 1
(from the previous AMPDU attempt), the aggr completion function would be
called and be very confused about what's going on.

Noticed by:	Kim <w8hdkim@gmail.com>
PR:		kern/171394
2012-09-07 00:24:27 +00:00
John Baldwin
b9b256e49a Remove NetBSD compat shims for drivers originally shared with NetBSD/pc98.
NetBSD/pc98 was never merged into the main NetBSD tree and is no longer
developed.  Adding locking to these drivers would have made the compat
shims hard to impossible to maintain, so remove the shims to ease
future changes.

These changes were verified by md5.  Some additional shims can be removed
that do affect the compiled results that I will probably do in another
round.

Approved by:	nyan (tentatively)
2012-09-06 18:53:33 +00:00
Fabien Thomas
1e862e5ad0 Add Intel Ivy Bridge support to hwpmc(9).
Update offcore RSP token for Sandy Bridge.
Note: No uncore support.

Will works on Family 6 Model 3a.

MFC after: 1 month
Tested by: bapt, grehan
2012-09-06 13:54:01 +00:00
Kevin Lo
3aa5b33a42 Add missing braces
Obtained from:	DragonFly
2012-09-06 02:07:58 +00:00
Gavin Atkinson
77c0749cb2 Add #defines for the bits in the PCI Express SLOT registers. Names
have been chosen based on the bit names in the PCI Express Base
Specification 3.0, and to match the predominant style of the existing
bit definitions.

MFC after:	1 week
2012-09-05 19:01:39 +00:00
John Baldwin
1832280a9e - Explicitly call twe_done() to poll the hardware when looping in
twe_start() to simulate the behavior on 4.x where the driver dropped
  spl to allow interrupts to run to free up space in the command
  queue.  Be careful to only poll if we are going to make at least
  one more attempt to queue the current command.  Also, when polling,
  be careful to not call twe_startio() to queue more commands to avoid
  recursion.
- Move the buffer for formatting AEN messages into the softc instead of
  using a single driver-wide static buffer.

Requested by:	scottl (1)
Tested by:	Mike Tancsa @ Sentex
2012-09-05 14:31:58 +00:00
Konstantin Belousov
ef9461ba0e Add support for new Intel on-CPU Bull Mountain random number
generator, found on IvyBridge and supposedly later CPUs, accessible
with RDRAND instruction.

From the Intel whitepapers and articles about Bull Mountain, it seems
that we do not need to perform post-processing of RDRAND results, like
AES-encryption of the data with random IV and keys, which was done for
Padlock. Intel claims that sanitization is performed in hardware.

Make both Padlock and Bull Mountain random generators support code
covered by kernel config options, for the benefit of people who prefer
minimal kernels. Also add the tunables to disable hardware generator
even if detected.

Reviewed by:	markm, secteam (simon)
Tested by:	bapt, Michael Moll <kvedulv@kvedulv.de>
MFC after:	3 weeks
2012-09-05 13:18:51 +00:00
Mike Silbersack
66437e8374 Only stop the BXE controller if it was first started. Stopping
an uninitialized controller can cause IPMI bus errors on some
systems.

Reviewed by:	yongari
Obtained from:	McAfee, Inc.
MFC after:	2 weeks
2012-09-05 06:51:28 +00:00
Gavin Atkinson
5163813777 Support another uchcom(4) device.
MFC after:	1 week
2012-09-04 23:13:24 +00:00
Xin LI
dac366886e Update arcmsr(4) to vendor version 1.20.00.25.
Many thanks to Areca for continuing to support FreeBSD.

Submitted by:	Ching-Lung Huang <ching2048 areca com tw>
MFC after:	2 weeks
2012-09-04 05:15:54 +00:00