be able to claim I know how the UART code works."
* Just return 115200 as the current baud rate. I should cache it in the
device struct and return that but I'm lazy right now.
* don't error out on other ioctl settings for now, just silently ignore them.
* remove some code that was copied from the 8250 driver that isn't needed
any longer.
Tested:
* AR9331, Carambola-2 board.
handle packets up to 1536 bytes)
This fixes the need to frag that could happen when using vlans on top of
if_arge (which is a common case for the use the switch ports as individual
NICs).
Previously to this commit any vlan setup with if_arge as parent would have
the MTU of the parent interface reduced by the size of dot1q header
(4 bytes).
Tested on TP-Link 1043ND (where the WAN port is just a switch port setup to
tag packets in a different VLAN than the LAN ports).
Reported and tested by: Harm Weites (harm at weites.com)
In particular, don't check the value of the bus_dma map against NULL
to determine if either bus_dmamem_alloc() or bus_dmamap_load() succeeded.
Instead, assume that bus_dmamap_load() succeeeded (and thus that
bus_dmamap_unload() should be called) if the bus address for a resource
is non-zero, and assume that bus_dmamem_alloc() succeeded (and thus
that bus_dmamem_free() should be called) if the virtual address for a
resource is not NULL.
In many cases these bugs could result in leaks when a driver was detached.
Reviewed by: yongari
MFC after: 2 weeks
the GPIO pin is connected to a push button (or other devices).
Instead keep the boot loader settings.
Calling ar71xx_gpio_pin_configure() with DEFAULT_CAPS was probably a
mistake and was causing all the pins to be set as outputs.
at that time, but AFAIK it is only used on routerboards.
Enabling GPIO_FUNC_SPI_CS[1|2]_EN will claim the use of gpio pins 0 and 1
respectivelly for use as SPI CS pins.
When really needed, this can still be enabled on kernel hints using the
function_set and function_clear knobs.
chips have more.
So for now, let's allow more. We should teach the apb code to just
reject interrupts that lie outside what the chip can do at runtime.
later. If the interrupts are ACKed even if they're not masked, we get
the interrupts again later. Grr.
* The AR724x and later chips want the interrupt bits cleared by writing the
relevant bit to it, NOT by writing all but the current interrupt to it.
Tested:
* AR9344, DB120 reference board
TODO:
* Test ar724x and later chips to ensure no regressions have occured.
'eeprommac'.
The existing driver would just make arge units past 0 take the primary
MAC and increment it by the unit number, without correct address wrapping.
That has to be fixed at a later date.
Tested:
* Atheros DB120 reference obard
console, it calls the grab functions. These functions should turn off
the RX interrupts, and any others that interfere. This makes mountroot
prompt work again. If there's more generalized need other than
prompting, many of these routines should be expanded to do those new
things.
Reviewed by: bde (with reservations)
shifts into the sign bit. Instead use (1U << 31) which gets the
expected result.
This fix is not ideal as it assumes a 32 bit int, but does fix the issue
for most cases.
A similar change was made in OpenBSD.
Discussed with: -arch, rdivacky
Reviewed by: cperciva
return BUS_PROBE_NOWILDCARD from their probe routines to avoid claiming
wildcard devices on their parent bus. Do a sweep through the MIPS tree.
MFC after: 2 weeks
The MDIO bus frequency is configured as a divisor off of the MDIO bus
reference clock. For the AR9344 and later, the MDIO bus frequency can
be faster than normal (ie, up to 100MHz) and thus a static divisor may
not be very applicable.
So, for those boards that may require an actual frequency to be selected
regardless of what crazy stuff the vendor throws in uboot, one can now
set the MDIO bus frequency. It uses the MDIO frequency and the target
frequency to choose a divisor that doesn't exceed the target frequency.
By default it will choose:
* DIV_28 on everything; except
* DIV_58 on the AR9344 to be conservative.
Whilst I'm here, add some comments about the defaults being not quite
right. For the other internal switch devices (like the AR933x, AR724x)
the divisor can be higher - it's internal and the reference MDIO clock
is much lower than 100MHz.
The divisor tables and loop code is inspired from Linux/OpenWRT. It's very
simple; I didn't feel that reimplementing it would yield a substantially
different solution.
Tested:
* AR9331 (mips24k)
* AR9344 (mips74k)
Obtained from: Linux/OpenWRT
up and running.
* The MAC FIFO configurations needed updating;
* Reset the MDIO block at the same time the MAC block is reset;
* The default divisor needs changing as the DB120 runs at a higher
base MDIO bus clock compared to other chips.
The long-term fix is to allow the system to have a target MDIO bus
clock rate and then calculate the most suitable divider to meet
that. This will likely need implementing before stable external
PHY or switch support can be committed.
Tested:
* AR9344 (mips74k)
* AR9331 (mips24k)
Without correct barriers, this code just plain doesn't work on the
mips74k cores (specifically the AR9344.)
In particular, the MDIO register accesses need this barriering or MII bus
access results in out-of-order garbage.
Tested:
* AR9344 (mips74k)
* AR9331 (mips24k)
This is required for correct, stable operation on the MIPS74k SoCs
that are dual-issue, superscalar pipelines.
Tested:
* AR9344 SoC (MIPS74k)
* AR9331 SoC (MIPS24k)
* Add the MDIO clock probe during clock initialisation;
* Update the ethernet PLL configuration function to use the correct
values;
* Add a GMAC block configuration to pull the configuration out of hints;
* Add an ethernet switch reconfiguration method.
Tested:
* AR9344 SoC (DB120)
.. however, this has been tested with extra patches in my tree (to fix
the ethernet/MDIO support, SPI support, ethernet switch support)
and thus it isn't enough to bring the full board support up.
* Initialise the MDIO clock to default to the reference clock;
* Add some code to allow the hints mechanism to allow setup of the GMAC
config block.
* Document how the switch is wired up internally.
Tested:
* AR9331 SoC (Carambola 2)
* Print out the platform frequency the same as the other frequencies.
* Print out the MDIO frequency.
* Optionally do GMAC and ethernet switch setup if required.
Tested:
* AR9344
switch reset/initialise functions.
The AR934x and QC955x SoCs both have a configurable MDIO base clock.
The others have the MDIO clock use the same clock as the system
reference clock, whatever that may be.
Tested:
* AR9344 SoC
TODO:
* mips24k - AR933x would be fine for now, just to ensure that things
are sane.
control block.
The GMAC configuration block allows for some configuration of how
the GMAC0 (ie, arge0) port is connected to the on-board switch
(if indeed there is one.) It both can be pushed into the on-board
switch; it could also be torn out and exposed via an external
MII (and that operational mode is also controllable.)
Obtained from: Linux/OpenWRT
add some packet(s) to tx ring and arge_stop() is called before receive the
sent packet interrupt from hardware. Fix arge_stop() to unload the in use
dma tags and free the associated mbuf.
PR: 178319, 163670
Approved by: adrian (mentor)
(re)start the interface when it is down. This change fix a race with
BOOTP where the response packet is lost because the interface is being
reset by a netmask change right after send the packet.
PR: 178318
Approved by: adrian (mentor)
form xx:xx:xx:xx:xx:xx complete with ":" characters taking of 18 bytes
instead of 6 integers. Expose a "readascii" tuneable to handle this case.
Remove restriction on eepromac assignement for the first dev instance only.
Add eepromac address for DIR-825 to hints file.
Add readascii hint for DIR-825
Reviewed by: adrian@
This code reads the PLL configuration registers and correctly programs
things so the UART and such can come up.
There's MIPS74k platform issues that need fixing; but this at least brings
things up enough to echo stuff out the serial port and allow for interactive
debugging with ddb.
Tested:
* AR71xx SoCs
* AR933x SoC
* AR9344 board (DB120)
Obtained from: Qualcomm Atheros; Linux/OpenWRT
For all pre-AR933x chips, the frequency is just the APB frequency.
For the AR933x, the UART frequency is different but we just hacked around
it.
For the AR934x, there's a different PLL setting for these, so they have
to be broken out.
