Refactor how we interface with the root HUB. This cuts around 1200 lines of
code totally and saves one thread per USB bus.
Submitted by: Hans Petter Selasky
- make usb2_power_mask_t 16-bit
- remove "usb2_config_sub" structure from "usb2_config". To compensate for this
"usb2_config" has a new field called "usb_mode" which select for which mode
the current xfer entry is active. Options are: a) Device mode only b) Host
mode only (default-by-zero) c) Both modes. This change was scripted using
the following sed script: "s/\.mh\././g".
- the standard packet size table in "usb_transfer.c" is now a function, hence
the code for the function uses less memory than the table itself.
Submitted by: Hans Petter Selasky
- bugfixes after the memory usage reduction patch
- Use "udev->pipes_max" instead of USB_EP_MAX
- Use correct "bmRequestType" for getting the config descriptor.
Submitted by: Hans Petter Selasky
- memory usage reduction by only allocating the required USB pipes and USB
interfaces.
- cleanup some USB parsing functions to be more flexible.
Submitted by: Hans Petter Selasky
- Fix style for A3N and for a comment
Submitted by: Akira Funahashi <funa@funa.org>
Tested by: Marcin Nowak <marcin.nowak@simplusnet.pl>,
Diego Sardina <diego.sardina@gmx.com>
PR: kern/128634
the ATA status register with a 4-byte read request. This updates it, and
subsequent 1-byte reads will return the correct result.
This commit adds a hack to do this, which is currently ifdef'd powerpc,
although Linux and Darwin do this unconditionally on all platforms.
provided, for example, on the PowerPC 970 (G5), as well as on related CPUs
like the POWER3 and POWER4.
This also adds support for various built-in hardware found on Apple G5
hardware (e.g. the IBM CPC925 northbridge).
Reviewed by: grehan
The DIROUT bit difference between the 19 and 22 is annoying. We can
set both bits on both parts without ill effect. Use this trick to
simplify the code.
The DELAYS in the MII bus bit-bang code for the DL100xx parts aren't
needed. Eliminate them.
packet data. However, the AX88190A moves this on-chip and reduces it
to the more traditional 16k from 16k-32k. The AX88790 follows the
'190A. Probe memory above 32k to see which flavor of the '190 we have
and use the extra memory if we have it.
Eliminate the kludgy read eeprom for the ID code. It really is just a
memory read at location 0x400, so just use that instead. Makes the
code easier to understand as well as eliminates some magic numbers.
ed cards. There's a number of minor nits in a lot of the PHYs on the
PC Cards that use the Axis AX88190 or DLink DL10019 and DL10022 chips.
Forcing the autonegotiation doesn't seem to cause problems on the
cards that have sane PHYs, but makes several cards I have work without
further workarounds.
I'm not 100% sure that kicking the PHY and resetting them is the right
thing to do on the media change callback. Other NICs seem to need
this and do similar things.
only for mic-type inputs. This gives better chances to use it.
Change default configuration for some AD1986A codec based ASUS boards,
use it also for ASUS P5PL2 board. This makes front mic preamplifier working.
Tested by: Vadim Frolov <frolov@frolov.ck.ua>
o Don't run through the register initialization in the read mac routine
for the AX88x90. It duplicates other stuff that we do.
o Eliminate the 10ms delay after we reset the AX88x90. We already wait for
the appropriate bits to indicate reset is done.
a device specific DMA tag. On amd64 it could exhaust all of bounce
pages when bus_dma_tag_create(9) is called at malo_pci_attach() then as
result in next turn it returns ENOMEM. This fix a attach fail on amd64.
Pointed by: yongari
Tested by: dchagin
MFC after: 3 days
It seems that RTL8168D and RTL8102EL requires additional settle
time to complete RL_PHYAR register write. Accessing RL_PHYAR
register right after the write causes errors for subsequent PHY
register accesses.
Tested by: george at luckytele dot com,
Steve Wills < STEVE at stevenwills dot com >
don't have one of the clock cycles (the turn cycle) that the AX88x90
chips have. Make this conditional. But this seems totally crazy and
can't possibly be right. Commit the fix for the moment until I can
explore this mystery more deeply.
On the plus side, the DL10022-based cards I have (D-Link DEF-670TXD
and SMC8040TX) work after this fix.
Add ch_suspend/ch_resume methods for PCI controllers and implement them
for AHCI. Refactor AHCI channel initialization according to it.
Fix Port Multipliers operation. It is far from perfect yet, but works now.
Tested with JMicron JMB363 AHCI + SiI 3726 PMP pair.
Previous version was also tested with SiI 4726 PMP.
Hardware sponsored by: Vitsch Electronics / VEHosting.nl
o call ieee80211_encap in ieee80211_start so frames passed down to drivers
are already encapsulated
o remove ieee80211_encap calls in drivers
o fixup wi so it recreates the 802.3 head it requires from the 802.11
header contents
o move fast-frame aggregation from ath to net80211 (conditional on
IEEE80211_SUPPORT_SUPERG):
- aggregation is now done in ieee80211_start; it is enabled when the
packets/sec exceeds ieee80211_ffppsmin (net.wlan.ffppsmin) and frames
are held on a staging queue according to ieee80211_ffagemax
(net.wlan.ffagemax) to wait for a frame to combine with
- drivers must call back to age/flush the staging queue (ath does this
on tx done, at swba, and on rx according to the state of the tx queues
and/or the contents of the staging queue)
- remove fast-frame-related data structures from ath
- add ieee80211_ff_node_init and ieee80211_ff_node_cleanup to handle
per-node fast-frames state (we reuse 11n tx ampdu state)
o change ieee80211_encap calling convention to include an explicit vap
so frames coming through a WDS vap are recognized w/o setting M_WDS
With these changes any device able to tx/rx 3Kbyte+ frames can use fast-frames.
Reviewed by: thompsa, rpaulo, avatar, imp, sephe
