* convert phy_getinfo() to take a "gmode" flag, rather than the siba
TGSHIGH flags and then check for 2GHz. This should ensure that
gmode is set correctly even on DUALPHY NICs.
* move the siba_powerup() call and the TGSHIGH decoding into a
call to bwn_is_bus_siba(), and return an error if it's called
on anything else. We don't yet do anything else, but when we do..
Tested:
* BCM4322, 11a STA
This is all for the bhnd(4) work in progress. It's enough to probe/attach
all the bhnd internals, but we're missing OTP support and some cleanup
code. And, well, all the rest of the bhnd(4) migration.
So no, this won't give you BCM43225 support. Sorry!
That pops up in the rev 5xx / 6xx microcode on the later cores
(4312, 4322.) I'm not sure why this is happening yet and I'll
dig into it, but Linux b43 does the same thing.
* Add the new TX/RX frame formats;
* Use the right TX/RX format based on the frame info;
* Disable the 5xx firmware check, since now it should
somewhat work (but note, we don't yet use it unless
you manually add ucode11/initvals11 from the 5.x driver
to bwn-kmod-firmware;
* Misc: update some comments/debugging now I know what's
actually going on.
Tested:
* BCM4321MC, STA mode, both 4xx and 666 firmware, DMA mode
TODO:
* The newer firmware ends up logging "warn: firmware state (0)";
not sure yet what's going on there. But, yes, it still works.
I'm committing this via a BCM4321MC, 11a station, firmware
rev 666.
Obtained from: Linux b43 (TX/RX descriptor format for 5xx)
* always allocate maximum size txhdr entries
* set the right rx header offset/framesize based on firmware
This still isn't what's completely required for fw 598 support; there's
more to come.
Tested:
* Apple BCM94321MC 11abgn NIC, 11a STA mode, firmware version 4xx.
Obtained from: DragonflyBSD (txhdr entry sizing), fw 598 RX header size (linux b43)
This is an updated version of D6140.
Tested:
* BCM4321 11abgn, STA mode (11a)
Submitted by: avos
Differential Revision: https://reviews.freebsd.org/D6140
* DUALPHY in TGSHIGH tells us there's a phy that is dualband, rather than
two separate PHYs/MACs (which we almost but don't quite yet support.)
Use it.
* Add the BCM4322 PCI ID to the list of devices we don't override.
This means the 2g/5g flags are preserved, and thus we get 5GHz
operation (with N-PHY, of course.)
Tested:
* BCM4311, STA mode (11bg)
* BCM4312, STA mode (11bg)
* BCM4321, STA mode (11abg)
Sponsored by: Palm Springs
I've submitted an alternative proposal to -core about just importing
the (converted) GPL PHY code in an alternate directory under sys/gnu/
so I don't have to rewrite it all to be BSD licenced.
N-PHY and later require a lot more plcp specific setup for the PHY
to know what to transmit. I've been spoilt by the atheros, intel
and realtek parts where you don't have to hand-assemble the PLCP
but .. well, apparently Broadcom require a lot more work.
This, and PHY-N itself, was the last major missing bit to get 11a
OFDM transmit to work. Without this, CCK transmit worked but
OFDM transmit would always fail (with stat.phy_err set to 0x80.)
I have no idea what 0x80 is, and I went mad reading the broadcom
vendor driver to try and figure it out.
Tested:
* BCM4312 (PHY-LP)
* BCM4321 (PHY-N), 11a, 11bg.
Set phy-full-init always to 1 for now; PHY-N supports being able to do
partial init for things like fast channel changes but I'm going to
ignore it all.
This is a big commit with a whole lot of little changes, all in
preparation for PHY-N and rev 5xx firmware.
* add in a write method that does an explicit flush
* change the txpwr recalc type to return an enum, versus just an int.
* add in PHY-N RX frame format bits, for decoding RX RSSI and such
* add in the header space calculation for rev 5xx firmware.
* add in a whole bunch of new types that the newer and 5g phy code
needs. Notably, broadcom has a split 5GHz band concept -
5G-Low, 5G(-Mid) and 5G-High. I kept encountering this at my
day job and wondered whether it was just some marketing thing.
Nope, turns out it isn't; it's an actual PHY thing.
* Add a "am I a siba bus device" method, that returns true.
The aim is to convert all the siba/bhnd specific bits in if_bwn
over to be wrapped in this check, so when landon does a BHND
drive through he knows which bits need updating.
Now, this the /complete/ set of changes for rev 5xx firmware.
Notably, the TX descriptor handling isn't at all done yet and the
format has changed. So don' try blindly flipping this on just yet!
* Log the per-completion status out if requested
* If we get a PHY failure, the retrycnt is set to 0 and ack=0, so
the logic was incorrect. So, for ack=0, ensure we don't log
a retrycnt of 0 (or rate control breaks) or a negative retrycnt
(or rate control also breaks.)
Tested:
* BCM4321 (11abgn N-PHY), BCM4312 (LP-PHY)
* Ensure we set 20MHz wide channels (hard-coded) for PHY-N.
* Change the core rese tto take a flag saying "gmode" vesus uint32_t
flags. This is important for BCMA support where the "gmode" bit
is different.
* Refactor out the mac-phy clock reset routine (usde by PHY-N).
Tested:
* BCM4321 (PHY-N), BCM4312 (PHY-LP)
TODO:
* Checkpoint test on PHY-G hardware, just to check.
This isn't compiled in yet; so some code here duplicates what
is in the existing code. I'll migrate it all out in subsequent
commits.
Obtained from: b43 (definitions), bcm-v4 specifications website
This will eventually live in sys/dev/bhnd/, but I won't use that until
we migrate the whole driver over.
So, this'll live here for now.
Obtained from: Linux b43 (definitions)
bwn_sqrt() is in the PHY-LP code but is also needed by the upcoming
PHY-N support.
The other two routines are used by the PHY-N code.
The next commit will introduce it into the compile and pull bwn_sqrt()
out of the PHY-LP source.
* Add the siba bus phy/mac/bandwidth clock definitions (TGSLOW*)
* Add the PHY-N register gateway (BWN_PHY_N())
* Add the PHY-N TX phystat1 register - we need to actually fill out
more of the PHY encoding information when we assemble a frame.
* Various ancillary stuff
Nothing uses this yet, but I do have CCK/OFDM somewhat working
in 2GHz mode on a PHY-N device.
Obtained from: b43 (definitions)
This adds support for the NVRAM handling and the basic SPROM
hardware used on siba(4) and bcma(4) devices, including:
* SPROM directly attached to the PCI core, accessible via PCI configuration
space.
* SPROM attached to later ChipCommon cores.
* SPROM variables vended from the parent SoC bus (e.g. via a directly-attached
flash device).
Additional improvements to the NVRAM/SPROM interface will
be required, but this changeset stands alone as working
checkpoint.
Submitted by: Landon Fuller <landonf@landonf.org>
Reviewed by: Michael Zhilin <mizkha@gmail.com> (Broadcom MIPS support)
Differential Revision: https://reviews.freebsd.org/D6196
