Commit Graph

700 Commits

Author SHA1 Message Date
Justin Hibbits
181ca73b1a Small performance optimization. Clobber only cr0, rather than the entire CR.
Discussed with:	rdivacky,nwhitehorn
MFC after:	3 weeks
2014-04-11 06:17:44 +00:00
Justin Hibbits
a1e7448e2c Correct the SRR1 mask, it's 10-15 not 10-11.
X-MFC-with:	r263464,r263752
2014-04-06 06:18:43 +00:00
Tijl Coosemans
0a4c54d606 Rename __wchar_t so it no longer conflicts with __wchar_t from clang 3.4
-fms-extensions.

MFC after:	2 weeks
2014-04-01 14:46:11 +00:00
Warner Losh
ef53f64d9e Define PSL_SRR1_MASK for BOOK-E too so MPC85XX compiles again. 2014-03-25 22:49:33 +00:00
Justin Hibbits
196321d6b0 Mask out SRR1 bits that aren't exported to the MSR.
This appears to fix a strange condition with X on 32-bit PowerBooks I observed,
caused by one of these bits getting set in the mcontext, but not set in the
thread, which may be a symptom of another problem, more difficult to diagnose.
Since these bits aren't exported anyway, this change makes it more explicit that
the bits aren't MSR-related in SRR1.

MFC after:	3 weeks
2014-03-21 04:45:57 +00:00
Ed Maste
0fcefb433d Update NetBSD Foundation copyrights to 2-clause BSD
The NetBSD Foundation states "Third parties are encouraged to change the
license on any files which have a 4-clause license contributed to the
NetBSD Foundation to a 2-clause license."

This change removes clauses 3 and 4 from copyright / license blocks that
list The NetBSD Foundation as the only copyright holder.

Sponsored by:	The FreeBSD Foundation
2014-03-18 01:40:25 +00:00
Justin Hibbits
169dd953b0 Add hwpmc(4) support for the PowerPC 970 class processors, direct events.
This also fixes asserts on removal of the module for the mpc74xx.

The PowerPC 970 processors have two different types of events: direct events
and indirect events.  Thus far only direct events are supported.  I included
some documentation in the driver on how indirect events work, but support is
for the future.

MFC after:	1 month
2014-02-01 02:03:50 +00:00
Justin Hibbits
e1c161e74c Unbreak non-SMP builds. This was broken by r259284. Also, reorganize the
code introduced in that revision a bit.

Reviewed by:	nwhitehorn
MFC after:	3 weeks
2014-01-31 03:55:34 +00:00
Andreas Tobler
feb86bbe4f Described in the man page but not implemented. Here it comes,
atomic_swap_32/64. The latter only for powerpc64.

MFC after:	1 month
2014-01-13 22:21:29 +00:00
Nathan Whitehorn
dcd08302e5 Retire machine/fdt.h as a header used by MI code, as its function is now
obsolete. This involves the following pieces:
- Remove it entirely on PowerPC, where it is not used by MD code either
- Remove all references to machine/fdt.h in non-architecture-specific code
  (aside from uart_cpu_fdt.c, shared by ARM and MIPS, and so is somewhat
  non-arch-specific).
- Fix code relying on header pollution from machine/fdt.h includes
- Legacy fdtbus.c (still used on x86 FDT systems) now passes resource
  requests to its parent (nexus). This allows x86 FDT devices to allocate
  both memory and IO requests and removes the last notionally MI use of
  fdtbus_bs_tag.
- On those architectures that retain a machine/fdt.h, unused bits like
  FDT_MAP_IRQ and FDT_INTR_MAX have been removed.
2014-01-05 18:46:58 +00:00
Justin Hibbits
1c8eb4c44b Set the PMC trapframe macros appropriately
MFC after:	2 weeks
2013-12-22 00:04:50 +00:00
Justin Hibbits
9a2edf0198 Add suspend/resume state saving for OpenPIC on PowerMac. It's likely this
can be used on the others (cpcht and psim), but that has not been tested.
2013-12-21 04:31:54 +00:00
Justin Hibbits
46cf9b63fd Rebase the PMC indices at 1, since PMC_SOFT is at 0.
MFC after:	1 week
2013-12-14 19:01:24 +00:00
Justin Hibbits
4702d987cd Add PMU-based CPU frequency scaling. This method is used on most Titanium
PowerBooks.

MFC after:	1 month
2013-12-13 02:37:35 +00:00
Andreas Tobler
05e1c598cc Increase PHYS_AVAIL_SZ because on pSeries machines we can have many logical
regions which represent the total amount of memory. The size of these regions
is not the physical size of the chip but it is a logical one and it is given
by the OpenFirmware, it is selectable at boot time and varies between 16MB and
256MB in my case. There is an 'automatic' option which would select the size as
64MB in case you have around 16GB of RAM.
To make sure we can allocate RAM with the automatic option bump this value
of PHYS_AVAIL_SZ to 256.
2013-12-05 21:34:33 +00:00
Nathan Whitehorn
fa6b4c32ba Remove fdtbus_bs_tag definition, which is now obsolete. The remainder of
this file is also slated for future demolition.
2013-12-02 17:45:43 +00:00
Nathan Whitehorn
c1cb22d755 Rearchitect platform memory map parsing to make it less
Open Firmware-centric:
- Keep the static list of regions in platform.c instead of ofw_machdep.c
- Move various merging and sorting operations to platform.c as well
- Move apple_hacks code out of ofw_machdep.c and into platform_powermac.c,
  where it belongs
- Move CHRP-specific dynamic-reconfiguration memory parsing into
  platform_chrp.c instead of pretending it is shared code
2013-12-01 19:43:15 +00:00
Andreas Tobler
f367ffdecc Save and restore the trap vectors when doing OF calls on pSeries machines.
It turned out that on pSeries machines the call into OF modified the trap
vectors and this made further behaviour unpredictable.

With this commit I'm now able to boot multi user on a network booted
environment on my IntelliStation 285. This is a POWER5+ machine.

Discussed with:		nwhitehorn
MFC after:	1 week
2013-11-23 18:58:17 +00:00
Nathan Whitehorn
e537388b84 Unify handling of illegal instruction faults between AIM and Book-E. This
allows FPU emulation on AIM as well as providing support for the mfpvr
and lwsync instructions from userland on e500 cores. lwsync, in particular,
is required for many C++ programs to work correctly.

MFC after:	1 week
2013-11-17 15:12:03 +00:00
Nathan Whitehorn
debe445512 Split the function of the PCB_FPU flags into two: PCB_FPU now indicates that
the actual FPU is enabled, while PCB_FPREGS indicates that the FPU state
structure in the PCB is valid. This separation reflects the situation on
FPU-less systems in which the FP state is used by the emulator but we don't
actually want to try to turn on the non-existant FPU.

Use this flag to save and restore FP regs properly on both AIM and Book-E.
As a side effect, this sets up hard-FP and Altivec on Book-E CPUs with such
abilities except for a trap handler to call enable_fpu()/enable_altivec().
2013-11-17 14:44:22 +00:00
Nathan Whitehorn
b8b46489f8 Remove a pointless #ifdef AIM. This is just PPC64 specific, including
64-bit Book-E.
2013-11-17 02:26:09 +00:00
Nathan Whitehorn
46c4ae50bb There is no reason Book-E needs to save XER and CTR on context switches.
They aren't Book-E specific registers to begin with and, even if they were,
are defined volatile by the ABI.
2013-11-17 02:05:20 +00:00
Justin Hibbits
1bea62add7 Fix typo.
Submitted by:	loos
2013-11-13 01:51:40 +00:00
Justin Hibbits
99003fc6f6 Increase the stack size for ppc64 from 4 pages to 8.
I found a stack overflow when a coredump was taken onto a ZFS volume with
heavy network activity.  2 DSI traps, plus one DECR trap, along with several
function calls in the stack, overflowed the 4 pages.  8 page stack fixes this.

Discussed with: nwhitehorn
MFC after:	1 week
2013-11-13 01:37:52 +00:00
Nathan Whitehorn
bdac436008 Follow up r223485, which made AIM use the ABI thread pointer instead of
PCPU fields for curthread, by doing the same to Book-E. This closes
some potential races switching between CPUs. As a side effect, it turns out
the AIM and Book-E swtch.S implementations were the same to within a few
registers, so move that to powerpc/powerpc.

MFC after: 3 months
2013-11-11 17:37:50 +00:00
Alan Cox
c70af4875e As of r257209, all architectures have defined VM_KMEM_SIZE_SCALE. In other
words, every architecture is now auto-sizing the kmem arena.  This revision
changes kmeminit() so that the definition of VM_KMEM_SIZE_SCALE becomes
mandatory and the definition of VM_KMEM_SIZE becomes optional.

Replace or eliminate all existing definitions of VM_KMEM_SIZE.  With
auto-sizing enabled, VM_KMEM_SIZE effectively became an alternate spelling
for VM_KMEM_SIZE_MIN on most architectures.  Use VM_KMEM_SIZE_MIN for
clarity.

Change kmeminit() so that the effect of defining VM_KMEM_SIZE is similar to
that of setting the tunable vm.kmem_size.  Whereas the macros
VM_KMEM_SIZE_{MAX,MIN,SCALE} have had the same effect as the tunables
vm.kmem_size_{max,min,scale}, the effects of VM_KMEM_SIZE and vm.kmem_size
have been distinct.  In particular, whereas VM_KMEM_SIZE was overridden by
VM_KMEM_SIZE_{MAX,MIN,SCALE} and vm.kmem_size_{max,min,scale}, vm.kmem_size
was not.  Remedy this inconsistency.  Now, VM_KMEM_SIZE can be used to set
the size of the kmem arena at compile-time without that value being
overridden by auto-sizing.

Update the nearby comments to reflect the kmem submap being replaced by the
kmem arena.  Stop duplicating the auto-sizing formula in every machine-
dependent vmparam.h and place it in kmeminit() where auto-sizing takes
place.

Reviewed by:	kib (an earlier version)
Sponsored by:	EMC / Isilon Storage Division
2013-11-08 16:25:00 +00:00
Nathan Whitehorn
a7bb5efa45 Turn on VM_KMEM_SIZE_SCALE on 32-bit as well as 64-bit PowerPC.
Requested by:	alc
MFC after:	1 month
2013-10-27 14:03:51 +00:00
Nathan Whitehorn
33724f17d2 Interrelated improvements to early boot mappings:
- Remove explicit requirement that the SOC registers be found except as an
  optimization (although the MPC85XX LAW drivers still require they be found
  externally, which should change).
- Remove magic CCSRBAR_VA value.
- Allow bus_machdep.c's early-boot code to handle non 1:1 mappings and
  systems not in real-mode or global 1:1 maps in early boot.
- Allow pmap_mapdev() on Book-E to reissue previous addresses if the
  area is already mapped. Additionally have it check all mappings, not
  just the CCSR area.

This allows the console on e500 systems to actually work on systems where
the boot loader was not kind enough to set up a 1:1 mapping before starting
the kernel.
2013-10-26 18:18:14 +00:00
Nathan Whitehorn
597ab3a714 The old trap.h (then trap_aim.h) actually had trap ID codes for Book-E CPUs.
Use it universally. Book-E traps may also need revisiting due to the
introduction of fixed-offset traps and the deprecation of IVORs in POWER
ISA 2.06, but that's very much an issue for another day.
2013-10-26 14:54:43 +00:00
Nathan Whitehorn
d4602c7200 Remove some #ifdef and duplication in the MSR bit definitions. This adds
some security features to the Book-E kernel as well.
2013-10-25 14:37:15 +00:00
Nathan Whitehorn
544234026d Allow PIC drivers to translate firmware sense codes for themselves. This
is designed to replace the tables in dev/fdt/fdt_ARCH.c, but will not
happen quite yet.
2013-10-24 15:37:32 +00:00
Nathan Whitehorn
a5ff1d66de Implement GET_STACK_USAGE() on PowerPC. This implementation is identical
to that on x86 and sparc64.

Approved by:	re (kib)
2013-10-02 20:40:21 +00:00
Nathan Whitehorn
9f70672718 Rework handling of ofw_quiesce(), making it the responsibility of the
platform modules. Whether to call this function or not is highly machine
dependent: on some systems, it is required, while on others it breaks
everything. Platform modules are in a better position to figure this
out. This is required for POWER hypervisor SCSI to work correctly. There
are no functional changes on Powermac systems.

Approved by:	re (kib)
2013-09-27 13:12:47 +00:00
Nathan Whitehorn
5d548e66ff Add POWER7+ and POWER8 to the CPU ID table.
Approved by:	re (kib)
2013-09-17 17:29:56 +00:00
Nathan Whitehorn
c84bb047d4 Raise artificial limits on number of CPUs and number of interrupts.
Approved by:	re (kib)
2013-09-09 12:52:34 +00:00
Nathan Whitehorn
0658fe8ce1 Add hook called when every new processor is brought online -- including the
BSP -- so that platform modules have a chance to add the new CPU to any
internal bookkeeping.

Approved by:	re (kib)
2013-09-09 12:49:19 +00:00
Nathan Whitehorn
c2f2553784 Use the canonical bits for wired, etc. in the PTE. This is important for
interactions with certain kinds of hypervisors that look into the PTEs
more closely than they should.

Approved by:	re (kib)
2013-09-09 12:44:48 +00:00
Gleb Smirnoff
2ee9b44cae Fix build with gcc. Move sf_buf_alloc()/sf_buf_free() declarations
to MD headers.
2013-09-06 17:44:13 +00:00
Nathan Whitehorn
653a5825b8 Also align the 32-bit PowerPC stacks. 2013-09-05 23:28:50 +00:00
Nathan Whitehorn
a5715964b1 Align stacks of kernel threads correctly at 16-byte boundaries rather than
making sure they are all misaligned at +8 bytes. This fixes clang builds
of powerpc64 kernels (aside from a required increase in KSTACK_PAGES which
will come later).

This commit from FreeBSD/powerpc64 with a clang-built kernel.

MFC after:	2 weeks
2013-09-05 23:00:24 +00:00
Warner Losh
ce7c952a8e Newer versions of gcc define __INT64_C and __UINT64_C, so avoid
redefining them if gcc provides them.
2013-09-03 22:04:55 +00:00
Justin Hibbits
b2fb58a11d Refactor PowerPC hwpmc(4) driver into generic and specific. More refactoring
will likely be done as more drivers are added, since AIM-compatible processors
have similar PMC configuration logic.
2013-09-03 00:34:18 +00:00
Justin Hibbits
450f197050 Remove duplicate definition of SPR MMCR0.
MFC after:	3 days
2013-08-03 18:05:12 +00:00
Andriy Gapon
a29cc9a34b Revert r253748,253749
This WIP should not have been committed yet.

Pointyhat to:	avg
2013-07-28 18:44:17 +00:00
Andriy Gapon
366d8bfb7b put contents of cpu.h under _KERNEL
no userland-serviceable parts inside

MFC after:	20 days
2013-07-28 18:32:27 +00:00
Konstantin Belousov
70a7dd5d5b Fix issues with zeroing and fetching the counters, on x86 and ppc64.
Issues were noted by Bruce Evans and are present on all architectures.

On i386, a counter fetch should use atomic read of 64bit value,
otherwise carry from the increment on other CPU could be lost for the
given fetch, making error of 2^32.  If 64bit read (cmpxchg8b) is not
available on the machine, it cannot be SMP and it is enough to disable
preemption around read to avoid the split read.

On x86 the counter increment is not atomic on purpose, which makes it
possible for the store of the incremented result to override just
zeroed per-cpu slot.  The effect would be a counter going off by
arbitrary value after zeroing.  Perform the counter zeroing on the
same processor which does the increments, making the operations
mutually exclusive.  On i386, same as for the fetching, if the
cmpxchg8b is not available, machine is not SMP and we disable
preemption for zeroing.

PowerPC64 is treated the same as amd64.

For other architectures, the changes made to allow the compilation to
succeed, without fixing the issues with zeroing or fetching.  It
should be possible to handle them by using the 64bit loads and stores
atomic WRT preemption (assuming the architectures also converted from
using critical sections to proper asm).  If architecture does not
provide the facility, using global (spin) mutex would be non-optimal
but working solution.

Noted by:  bde
Sponsored by:	The FreeBSD Foundation
2013-07-01 02:48:27 +00:00
Justin Hibbits
05bd8e50ac Pad the PCPU MD struct, to satisfy an assert added with the projects/counters
branch import.

PR:		ports/179173,ports/179164
2013-06-04 00:40:26 +00:00
Marcel Moolenaar
972aa49664 Fix the PowerPC Book-E register definitions used by the remote GDB
protocol.

Obtained from:	Juniper Networks, Inc.
2013-05-21 18:00:47 +00:00
Attilio Rao
941646f5ec Rename VM_NDOMAIN into MAXMEMDOM and move it into machine/param.h in
order to match the MAXCPU concept.  The change should also be useful
for consolidation and consistency.

Sponsored by:	EMC / Isilon storage division
Obtained from:	jeff
Reviewed by:	alc
2013-05-07 22:46:24 +00:00
Gleb Smirnoff
85d592adf9 Since UMA_ZONE_PCPU zones put a constraint on sizeof(struct pcpu), declared
as CTASSERT in MI pcpu.h, stop including all possible mutually exclusive
PCPU_MD_FIELDS fields into LINT kernels, due to brekaing
aforementioned CTASSERT.
2013-04-10 16:09:45 +00:00