-DUSE_NANOSLEEP. Also, seperate the code for _THREAD_SAFE so that it uses
the simpler threaded nanosleep() call in libc_r.. We don't go to the same
extremes for emulating traditional sleep semantics (ie: eating any SIGALRM
that might happen) which things like apache seem to depend on.
shared function.
- use p->p_sleepend to try and get more accurate "time remaining" results
when the time has been adjusted.
- verify writeability of return address so that we can fail before sleeping
if the address for the result is bogus.
time for things like nanosleep. These sleep in terms of "ticks" and
calculate the elapsed time relative to the expected wakeup time and do
not return good results when the system time is adjusted.
interrupt mask hackery wasn't happening when being modloaded via the
if_ppp lkm. It seems that the lkm system doesn't particularly like having
two sets of load/unload/etc routines. :-] This really should be fixed
by having a seperate if_ppp and ppp_tty lkm, but that requires that ppp_tty
is loaded after if_ppp, and needs to be able to link with symbols in
if_ppp. This gets messy, it is a better task for the in-kernel linker.
(if_ppp is generic, ppp_tty is a tty-specific bottom end for if_ppp, it's
not _too_ hard to have another "provider" (such as a hdlc sync card)
connected to if_ppp)
the *_imask down in the isa machine dependent layers requires code changes
to all pci drivers, but the interrupt registration mechanism is in flux
at the moment. These can go away when the interface is cleaned and settled.
remove warning about ICU_LEN > 32, it's not likely to happen like this,
and besides, ICU_LEN is not the ideal indicator of "number of interrupts".
Reviewed by: bde, se
that lkm's can use them for fiddling the masks without being dependent on
which mode the kernel is compiled in (SMP or UP). This is particularly
for ppp_tty.c which has some domain crossing between the net and tty
subsystems. The values are not used in the spl code, they are for
reference only (ie: the compiled code uses immediate values rather than
an indirect 32 bit address and 32 bit data fetch).
top of the hardware interrupt handlers. Apparently this is slightly
faster with the bit scanning instruction that looks these up - this set of
changes reverts the original change.
Reviewed by: bde
rather than inlines. These are compiled with -fomit-frame-pointer and
work out pretty close to the original routines, but it might be a fraction
slower. The reason for doing this is to prevent the SWI_* and HWI_* values
from being compiled into drivers and lkms etc which is one of the things
that prevents the same lkm from being used on both SMP and UP kernels.
This gives us a lot more scope for experimenting with the splxxx
implementaton for SMP parallelism etc.
Reviewed by: bde
CPU code-named `M2'.
- Use the result of cpuid instruction instead of DIR to identify
6x86MX cpu. DIR0 and DIR1 are not documented in the data sheet, and
cpuid instruction is enabled at reset time.
- Add a function, init_6x86MX() to initialize 6x86MX cpu. It supports
CPU_SUSP_HLT and CPU_IORT options. It always sets NC1 (640K - 1M is
not cached.), and enables L1 cache in write-back mode.
- Fix typo in the comment in identblue().
Hopefully I've done the proper magic to merge changes between 1.17 and
1.17.2.1 into the main trunk. Description of those changes follows:
Brought in changes sent to me in late 1995 by Rich Murphey.
I cleaned up a few things and am currently running these under
2.2-970205-GAMMA.
The changes deal with software debouncing apparently necessary on
todays faster hardware, and also some problems with the use of the -Select
line for the TW-523 sync. This driver allows use of +PaperEnd as an
alternative.
