282 Commits

Author SHA1 Message Date
Alan Cox
fe105d45a2 Add a new sysctl for reporting all of the supported page sizes.
Reviewed by:	jhb
MFC after:	3 weeks
2009-09-18 17:04:57 +00:00
Poul-Henning Kamp
a254d1f16d Get rid of the _NO_NAMESPACE_POLLUTION kludge by creating an
architecture specific include file containing the _ALIGN*
stuff which <sys/socket.h> needs.
2009-09-08 20:45:40 +00:00
Oleksandr Tymoshenko
cbd59a4f65 - MFC from head@196987 2009-09-08 19:15:29 +00:00
Warner Losh
778355f6c1 (u_int) is the wrong type here. Use unsigned long instead, even
though that's only less wrong...

# This gets the kernel building again to the point it was at before
# the last IFC for the OCTEON1 kernel config.
2009-08-14 16:15:18 +00:00
Warner Losh
323ba97c65 Use unsigned long instead of unsigned for the integer casts here. The
former works for both ILP32 and LP64 programming models, while the
latter fails LP64.

# uintpr_t is better, but iirc, we can't pollute the name space to use it
# I likely need to audit all my uintptr_t changes for that issue...
2009-08-13 19:47:13 +00:00
Attilio Rao
dc6fbf6545 * Completely Remove the option STOP_NMI from the kernel. This option
has proven to have a good effect when entering KDB by using a NMI,
but it completely violates all the good rules about interrupts
disabled while holding a spinlock in other occasions.  This can be the
cause of deadlocks on events where a normal IPI_STOP is expected.
* Adds an new IPI called IPI_STOP_HARD on all the supported architectures.
This IPI is responsible for sending a stop message among CPUs using a
privileged channel when disponible. In other cases it just does match a
normal IPI_STOP.
Right now the IPI_STOP_HARD functionality uses a NMI on ia32 and amd64
architectures, while on the other has a normal IPI_STOP effect. It is
responsibility of maintainers to eventually implement an hard stop
when necessary and possible.
* Use the new IPI facility in order to implement a new userend SMP kernel
function called stop_cpus_hard(). That is specular to stop_cpu() but
it does use the privileged channel for the stopping facility.
* Let KDB use the newly introduced function stop_cpus_hard() and leave
stop_cpus() for all the other cases
* Disable interrupts on CPU0 when starting the process of APs suspension.
* Style cleanup and comments adding

This patch should fix the reboot/shutdown deadlocks many users are
constantly reporting on mailing lists.

Please don't forget to update your config file with the STOP_NMI
option removal

Reviewed by:	jhb
Tested by:	pho, bz, rink
Approved by:	re (kib)
2009-08-13 17:09:45 +00:00
Oleksandr Tymoshenko
5bbfa759e2 - Make i/d cache size field 32-bit to prevent overflow
Submited by: Neelkanth Natu
2009-08-10 01:49:59 +00:00
Oleksandr Tymoshenko
11e9b8bad1 - MFC @196061 2009-08-04 18:22:58 +00:00
Alan Cox
3153e878dd Add support to the virtual memory system for configuring machine-
dependent memory attributes:

Rename vm_cache_mode_t to vm_memattr_t.  The new name reflects the
fact that there are machine-dependent memory attributes that have
nothing to do with controlling the cache's behavior.

Introduce vm_object_set_memattr() for setting the default memory
attributes that will be given to an object's pages.

Introduce and use pmap_page_{get,set}_memattr() for getting and
setting a page's machine-dependent memory attributes.  Add full
support for these functions on amd64 and i386 and stubs for them on
the other architectures.  The function pmap_page_set_memattr() is also
responsible for any other machine-dependent aspects of changing a
page's memory attributes, such as flushing the cache or updating the
direct map.  The uses include kmem_alloc_contig(), vm_page_alloc(),
and the device pager:

  kmem_alloc_contig() can now be used to allocate kernel memory with
  non-default memory attributes on amd64 and i386.

  vm_page_alloc() and the device pager will set the memory attributes
  for the real or fictitious page according to the object's default
  memory attributes.

Update the various pmap functions on amd64 and i386 that map pages to
incorporate each page's memory attributes in the mapping.

Notes: (1) Inherent to this design are safety features that prevent
the specification of inconsistent memory attributes by different
mappings on amd64 and i386.  In addition, the device pager provides a
warning when a device driver creates a fictitious page with memory
attributes that are inconsistent with the real page that the
fictitious page is an alias for. (2) Storing the machine-dependent
memory attributes for amd64 and i386 as a dedicated "int" in "struct
md_page" represents a compromise between space efficiency and the ease
of MFCing these changes to RELENG_7.

In collaboration with: jhb

Approved by:	re (kib)
2009-07-12 23:31:20 +00:00
Warner Losh
df92abe375 fix prototype for MipsEmulateBranch. 2009-07-10 19:07:07 +00:00
Warner Losh
4d8c18e0d7 Better definitions for a few types for n32/n64. 2009-07-10 19:06:43 +00:00
Warner Losh
52efe5c569 Fixed aligned macros...
# I'm not sure bde will like this, but I want to commit it for others to review
# as well. :)
2009-07-10 19:06:15 +00:00
Oleksandr Tymoshenko
258430ffd1 - Port busdma code from FreeBSD/arm. This is more mature version
that takes into account all limitation to DMA memory (boundaries,
    alignment) and implements bounce pages.
- Add BUS_DMASYNC_POSTREAD case to bus_dmamap_sync_buf
2009-07-08 22:28:36 +00:00
Warner Losh
5ac0137013 Fix atomic_store_64 prototype for 64-bit systems. 2009-07-08 06:01:37 +00:00
Warner Losh
b04ad5dd49 The MCOUNT macro isn't going to work in 64-bit mode. Add a note to
this effect.
2009-07-06 02:27:03 +00:00
Warner Losh
2967976763 Provide a macro for PTR_ADDU as well. We may need to implement this
differently for N32...  Use PTR_ADDU in DO_AST macro.
2009-07-06 02:22:51 +00:00
Warner Losh
54d05c03e5 Change the addu here to daddu.
addu paranoina prodded by: jmallet@
2009-07-06 02:22:06 +00:00
Warner Losh
3eecc82e89 addu and subu are special. We need to use daddu and dsubu here to get
proper behavior.

Submitted by:	jmallet@
2009-07-05 21:16:26 +00:00
Sam Leffler
8c393fd1f0 Cleanup ALIGNED_POINTER:
o add to platforms where it was missing (arm, i386, powerpc, sparc64, sun4v)
o define as "1" on amd64 and i386 where there is no restriction
o make the type returned consistent with ALIGN
o remove _ALIGNED_POINTER
o make associated comments consistent

Reviewed by:	bde, imp, marcel
Approved by:	re (kensmith)
2009-07-05 17:45:48 +00:00
Warner Losh
bd34d48210 The SB1 has cohernet memory, so add it.
Also, Maxmem is better as a long.

Submitted by:	Neelkanth Natu
2009-07-05 15:20:16 +00:00
Warner Losh
46d854bbdb The SB1 needs a special value for the cache field of the pte.
Submitted by:	Neelkanth Natu
2009-07-05 15:19:28 +00:00
Warner Losh
72322b2318 compute the areas to save registers in for 64-bit access correctly. 2009-07-05 15:18:06 +00:00
Warner Losh
f8b89abb9d First cut at 64-bit types. not 100% sure these are all correct for
N32 ABI.
2009-07-05 15:17:11 +00:00
Warner Losh
8de20ddba8 Trim unreferenced goo. SDRAM likely should be next, but it is still
referenced.
2009-07-05 15:16:27 +00:00
Warner Losh
61a1eed0b4 First cut at atomics for 64-bit machines and SMP machines.
# Note: Cavium provided a port that has atomics similar to these, but
# that does a syncw; sync; atomic; sync; syncw where we just do the classic
# mips 'atomic' operation (eg ll; frob; sc).  It is unclear to me why
# the extra is needed.  Since my initial target is one core, I'll defer
# investigation until I bring up multiple cores.  syncw is an octeon specific
# instruction.
2009-07-05 15:13:24 +00:00
Warner Losh
24646e120c Bring in cdefs.h from NetBSD to define ABI goo.
Obtained from:	NetBSD
2009-07-05 08:14:00 +00:00
Warner Losh
0d978536b2 Pull in machine/cdefs.h for the ABI definitions. Provide a PTR_LA,
ala sgi, and use it in preference to a bare 'la' so that it gets
translated to a 'dla' for the 64-bit pointer ABIs.
2009-07-05 08:13:19 +00:00
Warner Losh
f547073088 Use uintptr_t rather than unsigned here for 64-bit correctness. 2009-07-05 07:01:34 +00:00
Warner Losh
da96ff5dae Define __ELF_WORD_SIZE appropriately for n64. Note for N32 I believe
this is correct.  While registers are 64-bit, n32 is a 32-bit ABI and
lives in a 32-bit world (with explicit 64-bit registers, however).
Change an 8, which was 4 + 4 or sizeof(int) + SZREG to be a simple '4
+ SZREG' to reflect the actual offset of the structure in question.
2009-07-05 07:00:51 +00:00
Warner Losh
64003afe2e (1) Use uintptr_t in preference to unsigned. The latter isn't right for
64-bit case, while the former is.

(2) include a SB1 specific coherency mapping

Submitted by:	Neelkanth Nath (2)
2009-07-05 06:56:51 +00:00
Warner Losh
4ecfc54d9d db_expr_t should be a intptr_t, not an int. These expressions can be
addresses or numbers, and that's a intptr_t if I ever saw one.
2009-07-05 06:44:37 +00:00
Warner Losh
6855d90580 Define COP0_SYNC for SB1 CPU.
Submitted by:	Neelkanth Natu
2009-07-05 06:43:01 +00:00
Warner Losh
2c1c8bb345 Switch to ABI agnostic ta0-ta3. Provide defs for this in the right
places.  Provide n32/n64 register name defintions.  This should have
no effect for the O32 builds that everybody else uses, but should help
make N64 builds possible (lots of other changes are needed for that).

Obtained from:	NetBSD (for the regdef.h changes)
2009-07-05 06:39:37 +00:00
Oleksandr Tymoshenko
09c817ba36 - MFC 2009-07-03 04:39:18 +00:00
Oleksandr Tymoshenko
00741bfc80 - Add support for handling TLS area address in kernel space.
From the userland point of view get/set operations are
    performed using sysarch(2) call.
2009-06-27 23:27:41 +00:00
Oleksandr Tymoshenko
5576af82b5 - Add guards to ensure that these files are included only once 2009-06-26 19:54:06 +00:00
Alan Cox
5797795f5a Correct the #endif comment.
Noticed by:	jmallett
Approved by:	re (kib)
2009-06-26 16:22:24 +00:00
Alan Cox
e999111ae7 This change is the next step in implementing the cache control functionality
required by video card drivers.  Specifically, this change introduces
vm_cache_mode_t with an appropriate VM_CACHE_DEFAULT definition on all
architectures.  In addition, this changes adds a vm_cache_mode_t parameter
to kmem_alloc_contig() and vm_phys_alloc_contig().  These will be the
interfaces for allocating mapped kernel memory and physical memory,
respectively, with non-default cache modes.

In collaboration with:	jhb
2009-06-26 04:47:43 +00:00
Oleksandr Tymoshenko
6846a68073 - Mark temp variable as "earlyclobber" in assembler inline in
atomic_fetchadd_32.  Without it gcc would use it as input
    register for v and sometimes generate following code for
    function call like atomic_fetchadd_32(&(fp)->f_count, -1):

801238b4:       2402ffff        li      v0,-1
801238b8:       c2230018        ll      v1,24(s1)
801238bc:       00431021        addu    v0,v0,v1
801238c0:       e2220018        sc      v0,24(s1)
801238c4:       1040fffc        beqz    v0,801238b8 <dupfdopen+0x2e8>
801238c8:       00000000        nop

   Which is definitly wrong because if sc fails v0 is set to 0
   and previous value of -1 is overriden hence whole operation
   turns to bogus
2009-06-19 04:43:49 +00:00
Warner Losh
2e24c40fec bye bye. This is no longer referenced, but much code from it will
resurface for a bus-space implementation.
2009-06-14 06:14:25 +00:00
Warner Losh
55f888f68d Cavium-specific goo is no longer necessary here. Of course, I now
have to write a bus space for cavium, but that shouldn't be too hard.
2009-06-14 06:10:36 +00:00
Warner Losh
558955d6a8 Move this to a more approrpiate plae. 2009-06-14 06:01:46 +00:00
Warner Losh
f7edf22465 Bring this in from the cavium port. 2009-06-14 05:29:13 +00:00
Oleksandr Tymoshenko
5948288d97 - Use restoreintr instead of enableint while accessing pcpu in DO_AST 2009-06-05 08:37:11 +00:00
Oleksandr Tymoshenko
16a7c7be6d - Replace CPU_NOFPU and SOFTFLOAT options with CPU_FPU. By default
we assume that there is no FPU, because majority of SoC does
   not have it.
2009-05-26 22:40:12 +00:00
Oleksandr Tymoshenko
7dafc31d3e - Add type cast for atomic_cmpset_acq_ptr arguments 2009-05-26 16:35:05 +00:00
Oleksandr Tymoshenko
be6bd37bab - Remove now unused NetBSDism intr.h 2009-05-26 06:01:17 +00:00
Oleksandr Tymoshenko
9270c7be8b - Add MIPS_IS_KSEG0_ADDR, MIPS_IS_KSEG1_ADDR and MIPS_IS_VALID_PTR
macroses thet check if address belongs to KSEG0, KSEG1 or both
    of them respectively.
2009-05-16 02:39:13 +00:00
Oleksandr Tymoshenko
e7153b2583 Merge from HEAD 2009-05-06 22:40:01 +00:00
Alan Cox
7b89d46e0f A variety of changes:
Reimplement "kernel_pmap" in the standard way.

Eliminate unused variables.  (These are mostly variables that were
discarded by the machine-independent layer after FreeBSD 4.x.)

Properly handle a vm_page_alloc() failure in pmap_init().

Eliminate dead or legacy (FreeBSD 4.x) code.

Eliminate unnecessary page queues locking.

Eliminate some excess white space.

Correct the synchronization of pmap_page_exists_quick().

Tested by: gonzo
2009-05-02 06:12:38 +00:00