this is is crucial at least for the latter.
What happens is that attaching uart(4) to scc(4) causes the SAB 82532 to
"receive" something and trigger a SER_INT_RXREADY interrupt, given that
at least fast/filter interrupts are already enabled. Prior to r253161,
uart_bus_ihand() was set up at this point and handled that condition,
i. e. read the RX FIFO and issued a Receive Message Complete.
Now, uart_bus_ihand() and uart_intr() are setup after attaching uart(4),
leaving the SER_INT_RXREADY interrupt triggered during the latter to
be handled by the iclear method. However, with that method not implement,
this in turn causes SAB 82532 to not issue any further SER_INT_RXREADY
interrupts until the RX FIFO is full again. Thus, 15 received bytes go
to nowhere, given that "the other half" of the RX FIFO is used for status
information. Hence, implementing sab82532_bfe_iclear() fixes things again.
Potentially, the same problem exists for QUICC.
- Remove unnecessary __RMAN_RESOURCE_VISIBLE.
- Remove a superfluous header.
- Use KOBJMETHOD_END.
- Mark unused arguments as such.
- Remove variables unused after initialization.
Reviewed by: marcel (earlier version)
The QUICC engine is found on various Freescale parts including MPC85xx, and
provides multiple generic time-division serial channel resources, which are in
turn muxed/demuxed by the Serial Communications Controller (SCC).
Along with core QUICC/SCC functionality a uart(4)-compliant device driver is
provided which allows for serial ports over QUICC/SCC.
Approved by: cognet (mentor)
Obtained from: Juniper
MFp4: e500
