Michael submitted code to activate the audio muxes.
fsmp:
extended those changes for different boards.
auto-detection of board types.
auto-detection of tuner types.
auto-detection of stereo option.
Michael submitted code to activate the audio muxes.
fsmp:
extended those changes for different boards.
auto-detection of board types.
auto-detection of tuner types.
auto-detection of stereo option
Fixed a bug in fxp_mdi_write - a hex number was missing a preceding 0x
and this was causing the routine to not wait for a PHY write to complete.
Added support for link0, link1, and link2 flags to toggle auto-
negotiation, 10/100, and half/full duplex:
link0 disable auto-negotiation
When set, these flags then have meaning:
-link1 10Mbps
link1 100Mbps
-link2 half duplex
link2 full duplex
...needs a manual page.
Stick 4 more, twin channel only, instructions behind
.if ( TWIN_CHANNEL)
aic7xxx_asm.c:
Add the -O options which allows the specification of which options
to include in a program listing. This makes it possible to easily
determine the address of any instruction in the program across
different hardware/option configurations. Updated usage() as well.
I broke the cable tuning with my 'TEST_A' code. Remove TEST_A define
till I finish this change for both tuning modes. Note that this
will effectively break the new TVTUNER_SETFREQ/TVTUNER_GETFREQ ioctl()s.
These aren't used by anyone but me yet (attempt to provide full resolution
fine tuning for "fringe" stations) so it should be no problem
written:
1) Full duplex mode is now supported (and works!)
2) The 10Mbps-only PCI Pro/10 should now work (untested, however)
Thanks to Justin Gibbs for providing a PCI bus analyzer trace while the
Intel Windows driver was configuring the board...this made it possible
to figure out the mystery bit that I wasn't setting in the PHY for full
duplex to work.
devtotty(). devtotty() must check its arg carefully since the arg is
supplied as ioctl data. This should fix PR3004.
Renamed devtotty() to snpdevtotty().
New sequencer assembler for the aic7xxx adapters. This assembler
performs some amount of register type checking, allows bit
manipulation of symbolic constants, and generates "patch tables"
for conditionalized downloading of portions of the program.
This makes it easier to take full advantage of the different
features of the aic7xxx cards without imposing run time penalies
or being bound to the small memory footprints of the low end
cards for features like target mode.
aic7xxx.reg:
New, assembler parsed, register definitions fo the aic7xxx cards.
This was done primarily in anticipation of 7810 support which
will have a different register layout, but should be able to use
the same assembler. The kernel aic7xxx driver consumes a generated
file in the compile directory to get the definitions of the register
locations.
aic7xxx.seq:
Convert to the slighly different syntax of the new assembler.
Conditionalize SCB_PAGING, ultra, and twin features which shaves
quite a bit of space once the program is downloaded.
Add code to leave the selection hardware enabled during reconnects
that win bus arbitration. This ensures that we will rearbitrate
as soon as the bus goes free instead of delaying for a bit.
When we expect the bus to go free, perform all of the cleanup
associated with that event "up front" and enter a loop awaiting
bus free. If we see a REQ first, complain, but attempt to
continue. This will hopefully address, or at least help diagnose,
the "target didn't send identify" messages that have been reported.
Spelling corrections obtained from NetBSD.
. properly declare the variable in in a .h file, as opposed to
using a private extern declaration in userconfig.c;
. move the definition of EISA_SLOTS and therefore the inclusion of
opt_eisa.h into eisaconf.c.
probing anytime soon, make EISA_SLOTS a fully supported option. It's
required for the HP NetServer LC series machines.
Next stop: make dset(8) aware of it as well.
valid signals, else return EINVAL for ioctl VT_SETMODE.
this fixes a problem that anybody with vty access can panic the system.
2.2-Candidate (and 2.1.0 I believe)
Reviewed-by: sos
time that we really want to do this is when a bus reset causes the sequencer
to be reset and the kernel driver now handles this case.
Remove some reordering in the select2 routine that wasn't necessary.
It was an experimental fix for a race condition I fixed elsewhere, and
confused the code flow.
Don't bother looping on a parity error in the mesgout loop since we can't
see parity errors on out phases.
Clean up the mesgin_identify code. In the old days, we "snooped" for tag
messages and used this as an indicator of whether or not the target was
using tagged transactions. This forced the sequencer to ack the identify
before determining if a valid SCB matched the target meaning that an abort
message to handle this case might not be seen before the target entered a
data phase. Since we can determin the "tagged-ness" of a target by looking
it up in the array of busy targets (recently introduced), we can determine
this up front simplifying the search code as well as ensuring we can follow
the SCSI specs method for rejecting a reselection.
When an SCB is placed on the free list, set its SCB_TAG to SCB_LIST_NULL.
This makes it much easier for the kernel driver to find active SCBs on the
card during error recovery.
negotiation messages may be tagged, we were overrunning the old buffer.
The variable that was getting squashed is updated before the message goes
out, causing corrupted SDTR or WDTR messages. Depending on the phases
traversed before message out, this could cause the wrong offset to be
negotiated allowing data overruns to occur. The problem is easier to
detect with wide targets on the chain since the allowed offset is smaller.
Also removed the unnecessary clearing of SPIORDY during the message out
phase. We don't rely on SPIORDY any more.
When setting the HCNT registers, do so in ascending order.
When performing tagged queueing in non-paging mode, also check the
disconnected bit in the SCB as extra sanity during a reconection.
Make the labels in the DMA routine more sane.
When doing a DMA, if we see the DMADONE condition come true, we can
simply turn of the DMA enable bits in DFCNTRL without testing the FIFO
state as HDONE is true when DMADONE is true and this emplies the FIFO is
empty.
These changes clear up the data overrun error messages and seem to prevent
the "timed out in data-in phase" problems.
changes, so don't expect to be able to run the kernel as-is (very well)
without the appropriate Lite/2 userland changes.
The system boots and can mount UFS filesystems.
Untested: ext2fs, msdosfs, NFS
Known problems: Incorrect Berkeley ID strings in some files.
Mount_std mounts will not work until the getfsent
library routine is changed.
Reviewed by: various people
Submitted by: Jeffery Hsu <hsu@freebsd.org>
free.
When we clear SCSIRATE, also clear the FAST20 bit in SXFRCTL0. This also
allowed me to clean up some of the ULTRA code.
ULTRAENB->FAST20 to follow the convention in the Adaptec data books.
Fix the data-overrun code to set both stcnt and hcnt otherwise, the transfer
will just hang until we get a timeout.
Add implicit support for the NOOP message. I've never heard of the driver
issueing a reject for one, but its silly to reject NOOP and who knows how a
device might react.
In the dma routine, check SDONE before cleaing SDMAEN. The data books mention
SDONE possibly being cleared when SDMAEN is reset. Clients of dma now need
to check if SINDEX is cleared to know if a phasemis occured.
Fix some comments to be correct.
This parameter is intended to allow new kernels to work with old LKM binaries,
provided the revision ID is incremented whenever the PCI LKM interface is
changed. The revision ID does not at all protect against changes in data
structures accesses by the driver.
Disabled the DMA byte counters - I had it this way originally and this is
the recommended setting.
Set crscdt to CRS only (0) since this is what it should be for an MII PHY.
Also fixed some comments.
host DMAs. The additional test to ensure that the DMA has stopped is also
unnecessary since we've already waited for the DMA to complete.
Update my copyright for the new year.
with <= 100 usec between each character arrival time. This didn't happen
until rev.1.75 of clock.c because DELAY(100) used to delay for closer to
80 usec than 100 usec, and the minimum time between character arrivals is
87.8 usec at the maximum supported speed of 115200 bps 8N1.
Clear DCD timestamp flag on close (the input timestamp flag is already
cleared).
key "print scrn".
It used to stop at the first non-open vty, now it skips the non-open
ones and thereby enable one to cycle around all open vty by pressing
"print scrn".
- don't uselessly initialize the fifo "DMA" bit at attach time.
- initialize the fifo "DMA" bit at open time. Without this, the device
interrupts for every character received, reducing input performance
to that of an 8250.
- don't uselessly initialize the fifo trigger level to 8 (scaled to
256) at attach time.
- don't scale the fifo trigger level to 512 bytes. The driver's pseudo-
dma buffer has size 256, so it can't handle bursts of size 512 or 256.
It should be able to handle the second lowest ftl (2 scaled to 64).
- don't reset the fifos in siostop(). Reset triggers a hardware bug
involving wedging of the output interrupt bit This workaround
unfortunately requires ESP support to be configured.
Expand the boundaries of a pause disabled region to close of possible race
condition.
Revert a portion of the DMA code to fix false overruns.
Add a missing "add_scb_to_free_list" so we don't leak SCBs.
SDONE, not HDONE.
In the data phase dma handler, mask off just the enable bits instead of
clearing the whole register. Clearing the direction bit could be bad.
Also don't stop a DMA until MREQPEND goes false. Doing this may cause
an ABORT on the PCI bus although I have yet to see this happen.
Add definitions for MREQPEND and the BRDCTL register. The BRDCTL register
is used to handle high byte termination and automatic termination testing.
