Commit Graph

292 Commits

Author SHA1 Message Date
Emmanuel Vadot
36dcd6a499 Allwinner usb phy: Rework resource allocation
The usbphy node for allwinner have two kind of resources, one for the
phy_ctrl and one per phy. Instead of blindy allocating resources, alloc
the phy_ctrl and pmu ones separately.
Also add a configuration struct for all different phy that hold the difference
between them (number of phys, unknow needed register write etc ...).

While here remove A83T code as upstream and FreeBSD dts don't have
nodes for USB.

This (plus 323640) re-enable OHCI on Pine64 on the bottom USB port.
The top USB port is routed to the OHCI0/EHCI0 which is by default in OTG mode.
While the phy code can handle the re-route to standard OHCI/EHCI we still need
a driver for musb to probe and configure it in host mode.

EHCI is still buggy on Pine64 (hang the board) so do not enable it for now.

Tested On:	Bananapi (A20), BananapiM2 (A31S), OrangePi One (H3) Pine64 (A64)
2017-09-16 15:58:20 +00:00
Emmanuel Vadot
489cba7d58 A64 CCUNG: Correct gate and reset for OHCI0/1
Reported by:	jmcneill
Pointy Hat:	manu
2017-09-16 15:50:31 +00:00
Emmanuel Vadot
082f09757c Allwinner: a10_gpio Fix panic on multiple lock
r323392 introduce gpio_pin_get/gpio_pin_set for a10_gpio driver.
When called via gpio method they must aquire the device lock while
when they are called via gpio_pin_configure the lock is already aquire.

Introduce a10_gpio_pin_{s,g}et_locked and call them in pin_gpio_configure
instead.

Tested On: BananaPi (A20)

Reported by:	Richard Puga richard@puga.net
2017-09-16 14:08:20 +00:00
Ian Lepore
e1275c6805 Add gpio methods to read/write/configure up to 32 pins simultaneously.
Sometimes it is necessary to combine several gpio pins into an ad-hoc bus
and manipulate the pins as a group. In such cases manipulating the pins
individualy is not an option, because the value on the "bus" assumes
potentially-invalid intermediate values as each pin is changed in turn. Note
that the "bus" may be something as simple as a bi-color LED where changing
colors requires changing both gpio pins at once, or something as complex as
a bitbanged multiplexed address/data bus connected to a microcontroller.

In addition to the absolute requirement of simultaneously changing the
output values of driven pins, a desirable feature of these new methods is to
provide a higher-performance mechanism for reading and writing multiple
pins, especially from userland where pin-at-a-time access incurs a noticible
syscall time penalty.

These new interfaces are NOT intended to abstract away all the ugly details
of how gpio is implemented on any given platform. In fact, to use these
properly you absolutely must know something about how the gpio hardware is
organized. Typically there are "banks" of gpio pins controlled by registers
which group several pins together. A bank may be as small as 2 pins or as
big as "all the pins on the device, hundreds of them." In the latter case, a
driver might support this interface by allowing access to any 32 adjacent
pins within the overall collection. Or, more likely, any 32 adjacent pins
starting at any multiple of 32. Whatever the hardware restrictions may be,
you would need to understand them to use this interface.

In additional to defining the interfaces, two example implementations are
included here, for imx5/6, and allwinner. These represent the two primary
types of gpio hardware drivers. imx6 has multiple gpio devices, each
implementing a single bank of 32 pins. Allwinner implements a single large
gpio number space from 1-n pins, and the driver internally translates that
linear number space to a bank+pin scheme based on how the pins are grouped
into control registers. The allwinner implementation imposes the restriction
that the first_pin argument to the new functions must always be pin 0 of a
bank.

Differential Revision:	https://reviews.freebsd.org/D11810
2017-09-10 18:08:25 +00:00
Ian Lepore
094e5e7e12 Switch to iicdev_readfrom/writeto() to do xfers with proper bus ownership.
Tested by:	manu@
2017-08-03 18:43:54 +00:00
Emmanuel Vadot
48ee531892 arm64: Add Allwinner H5 SoC
Allwinner H5 is an H3 (arm32) with Cortex A53 cores.
Add support for it and enable it in GENERIC kernel config

Tested on: OrangePi PC2
2017-08-02 20:19:19 +00:00
Emmanuel Vadot
904581f050 allwiner: modclk: Do not try to enable parent clock if it doesn't exist 2017-08-02 20:17:04 +00:00
Emmanuel Vadot
df8257d71d Allwinner A64: fix typo
'pll_ddr0' is the dram parent, not 'pll_ddr'
2017-07-27 17:51:51 +00:00
Emmanuel Vadot
8460de6783 Allwinner EHCI: Do not fail if we cannot get a phy
If we cannot get a phy, do not detach the driver, some boards have phy
always enabled and not exposed.
While here do not release the clocks if we fails as we release them
in a10_ehci_detach.

Tested-on:	OrangePi-One
2017-07-18 19:50:02 +00:00
Emmanuel Vadot
50bb2d50e8 if_awg: Add "allwinner,sun50i-a64-emac" compatible string.
This enable ethernet on Pine64 with latest DTS.
2017-07-09 12:35:19 +00:00
Emmanuel Vadot
31a8b4896f allwinner: Add A64 ccung support
Upstream DTS for A64 SoC doesn't provide a /clocks node as Linux switched
to ccu-ng
This commit adds the necessary bits to boot on pine64 with latest DTS from
upstream.
USB is not working for now and some node aren't present in the DTS (like the
PMU, Power Management Unit).

Tested on: Pine64
2017-07-03 19:30:03 +00:00
Emmanuel Vadot
7f61394200 Allwinner: Add support for H2 Plus SoC
H2+ SoC is a stripped down version of H3 without gigabit ethernet and 4K HDMI.
Also add sun8i-h2-plus-orangepi-zero.dts to the build as we run on this board.
2017-06-24 16:41:26 +00:00
Emmanuel Vadot
acd690d524 allwinner: Configure pins for DTS >= Linux 4.11
Starting with DTS from Linux 4.11, the pins list, function, drive and pull
are no longer prefixed with "allwinner,".
Allow the pinctrl driver to handle both case.
2017-06-19 06:30:04 +00:00
Andrew Turner
a29b35dd5e Start to rename files with common or generic names to be SoC specific. The
build system doesn't handle two files with the same name.
2017-06-04 09:11:14 +00:00
Ganbold Tsagaankhuu
5657848913 Use hwreset_get_by_ofw_idx() function instead, since there is
no reset-names dts property defined for IR in case of H3 SoC.
That way IR works on H3 SoC based board.
Tested on Orangepi mini 2 board.
2017-04-19 05:59:00 +00:00
Ganbold Tsagaankhuu
64af9561d6 Remove function declaration that doesn't exist. 2017-04-18 06:58:04 +00:00
Ganbold Tsagaankhuu
c8c3a33403 Fix and add comments to match selected frequency sample.
Add debug printfs when bootverbose is used.
No functional changes.
2017-03-25 10:39:24 +00:00
Marius Strobl
55dae242e6 Add and use a MMC_DECLARE_BRIDGE macro for declaring mmc(4) bridges
as kernel drivers and their dependency onto mmc(4); this allows for
incrementing the mmc(4) module version but also for entire omission
of these bridge declarations for mmccam(4) in a single place, i. e.
in dev/mmc/bridge.h.
2017-03-07 22:42:44 +00:00
Marius Strobl
b440e965da o Another round fixes for mmc(4), mmcsd(4) and sdhci(4) regarding
comments, marking unused parameters as such, style(9), whitespace,
  etc.
o In the mmc(4) bridges and sdhci(4) (bus) front-ends:
  - Remove redundant assignments of the default bus_generic_print_child
    device method (I've whipped these out of the tree as part of r227843
    once, but they keep coming back ...),
  - use DEVMETHOD_END,
  - use NULL instead of 0 for pointers.
o Trim/adjust includes.
2017-03-06 23:47:59 +00:00
Emmanuel Vadot
fd8516cc05 allwinner: A31: Add ccung driver
This adds clocks support for the aw_ccung on the A31 SoC.
Newer DTS files require this.
All the clocks except two CSI are defined and exported on the clock domain.
2017-02-28 15:44:21 +00:00
Emmanuel Vadot
b78b8251c9 allwinner: nkmp: Add MUX capability
Some NKMP clocks have a mux options.
Add the capability to aw_clk_nkmp.
2017-02-28 15:11:33 +00:00
Emmanuel Vadot
511d4e58f3 allwinner: NKMP clock: add update bit
The PLL_DDR clock have an update bit which need to be set after changing
the value, add the possibility to define one for NKMP clocks.

This allow us to add the missing clocks.
We now have the full list of clocks created under the clock domain.
2017-02-28 11:38:11 +00:00
Emmanuel Vadot
7a5603c04a allwinner: NM clock: Add value for fixed factor.
The register func for aw_clk_nm didn't copy the value needed for the fixed
factor, resulting in all fixed factor not working on NM clocks.
2017-02-28 11:05:45 +00:00
Emmanuel Vadot
25d9f6e859 allwinner: Correct some clocks name for H3 CCU. 2017-02-27 17:12:17 +00:00
Emmanuel Vadot
a5ae21c50d allwinner: Order clocks by offset rather than by type for H3 ccu.
Also add a few more supported gates and add comments for which clocks
are missing.
2017-02-27 11:10:36 +00:00
Emmanuel Vadot
d7e3f295fa allwinner: Add support for lock and fractional mode on NM clock
Some PLL have a fractional mode and a lock bit.
Add support for it on the NM clock and export the clocks in the clkdom.
2017-02-27 08:58:27 +00:00
Emmanuel Vadot
f5d1d20574 Add clkng driver for Allwinner SoC
Since Linux 4.9-4.10 DTS doesn't have clocks under /clocks but only a ccu node.
Currently only H3 is supported with almost the same state as HEAD.
(video pll aren't supported for now but we don't support video).
This driver and clocks will also be used for other SoC (A64, A31, H5, H2 etc ...)

Reviewed by:	jmcneill
Differential Revision:	https://reviews.freebsd.org/D9517
2017-02-26 16:00:20 +00:00
Emmanuel Vadot
58256cf76e Rename timer.c to a10_timer.c
Requested by: andrew
2017-02-07 19:28:32 +00:00
Michal Meloun
93a065e749 Remake support for SMP kernel on UP cpu:
- Use new option SMP_ON_UP instead of (mis)using specific CPU type.
   By this, any SMP kernel can be compiled with SMP_ON_UP support.
 - Enable runtime detection of CPU multiprocessor extensions only
   if SMP_ON_UP option is used. In other cases (pure SMP or UP),
   statically compile only required variant.
 - Don't leak multiprocessor instructions to UP kernel.
 - Correctly handle data cache write back to point of unification.
   DCCMVAU is supported on all armv7 cpus.
 - For SMP_ON_UP kernels, detect proper TTB flags on runtime.

Differential Revision: https://reviews.freebsd.org/D9133
2017-02-02 06:14:44 +00:00
Emmanuel Vadot
cf72965fbf Allwinner: Add A33 support
Add basic support for A33/R16 that is enough to boot a kernel.
This adds the platform code, padconf data and the new clocks strings.

MFC after:	2 weeks
2017-01-04 03:35:39 +00:00
Emmanuel Vadot
338af8a097 Allwinner clk: factor M for mod clock is 4 bits, not 5
MFC after:	1 week
2016-12-22 15:01:06 +00:00
Jared McNeill
06785ff66a Split the DesignWare HDMI-specific code from imx6_hdmi.c into a separate
file and add a generic DT binding that takes advantage of the extres
framework for setting up clocks.

Reviewed by:		gonzo
Differential Revision:	https://reviews.freebsd.org/D8826
2016-12-20 01:34:29 +00:00
Emmanuel Vadot
1e64280173 Honor the CLK_SET_DRYRUN for the *set_freq function for allwinner clocks.
Reviewed by:	jmcneill
MFC after:	1 month
Differential Revision:	https://reviews.freebsd.org/D8821
2016-12-16 21:58:48 +00:00
Andrew Turner
6c925b9c81 All armv6 platforms have the same implementation of platform_lastaddr.
Replace them with a default handler that returns devmap_lastaddr.

Reviewed by:	mmel
Sponsored by:	ABT Systems Ltd
Differential Revision:	https://reviews.freebsd.org/D8806
2016-12-16 10:31:13 +00:00
Emmanuel Vadot
74b66ae149 Fix building arm64 kernel after r310117
Pointy hat: me

MFC after:	3 days
2016-12-15 17:26:16 +00:00
Emmanuel Vadot
15b2342cf3 Add information about interrupts in the Allwinner padconf files and
correct some pin numbering.

While here switch to my freebsd mail address in the copyright.

MFC after:	3 days
2016-12-15 15:52:13 +00:00
Emmanuel Vadot
2b0f0faeb6 Add new compatible string "allwinner,sun7i-a20-mmc".
New upstream DTS is using this now for A20 SoC.

MFC after:	3 days
2016-12-14 15:00:24 +00:00
Andrew Turner
ba9f40ca3b Use the platform_*_t typedefs to help check the platform function types are
correct.

Sponsored by:	ABT Systems Ltd
2016-12-13 13:46:09 +00:00
Andrew Turner
59249a516a Add the missing void to function signatures in much of the arm code.
Sponsored by:	ABT Systems Ltd
2016-12-13 13:43:22 +00:00
Emmanuel Vadot
def44246f2 PLL3 have a fractional mode where an explicit frequency (297Mhz or 270)
can be selected for it. If the desired frequency is one of those two, use
this mode instead of the integer one.
When calculating the PLL3 freq for the dotclock, check if it is a multiple
of the fracional frequencies.

MFC after:	2 weeks
2016-11-26 10:36:48 +00:00
Emmanuel Vadot
49ba3f32c8 Enable the SCL and SDA i2c line for DDC.
This is an undocumented register that we need to set if we do not want to
rely on u-boot or other bootloader.
2016-11-24 01:24:26 +00:00
Emmanuel Vadot
183a6b3de6 Test that the emac device is enabled in probe function
MFC after:	3 days
2016-11-23 18:07:44 +00:00
Emmanuel Vadot
5e2be2f660 Do not attempt to disable/release clock if it had not been enabled.
While here fix a style(9) issue.

MFC after:	1 week
2016-11-23 01:44:28 +00:00
Jared McNeill
0a30b4b2a5 On H3, initialize alarm and shutdown trip points and do temperature
conversion as it is done in the BSP.
2016-11-19 14:56:22 +00:00
Jared McNeill
ce4e4d612b On command error, reset only DMA and FIFO engines instead of the entire
controller. Fixes eMMC device detection on OrangePi Plus 2e (and likely
others).
2016-11-15 23:48:30 +00:00
Jared McNeill
02b2e3c5fb Allow the MMC frequency to be set up to 52MHz for MMC high speed timings. 2016-11-15 23:46:01 +00:00
Emmanuel Vadot
51503e707b Upstream DTS provides PLL3 and PLL7 nodes (and their x2 form),
so remove them from our DTS and adapt the code to handle them correctly.
This fix HDMI video on A20.
2016-11-15 07:08:33 +00:00
Andrew Turner
222102cfca Move including fdt_pinctrl.h after openfirm.h to get th edefinition of
phandle_t and remove the need for including fdt_common.h.

Sponsored by:	ABT Systems Ltd
2016-11-14 11:52:22 +00:00
Andrew Turner
df7675353e Stop including fdt_common.h from the arm code when it's unneeded.
Sponsored by:	ABT Systems Ltd
2016-11-14 11:41:22 +00:00
Andrew Turner
87acb7f815 Use the modern spelling of ofw_bus_node_is_compatible in sys/arm.
Sponsored by:	ABT Systems Ltd
2016-11-11 15:13:30 +00:00