This adds bhnd(4) bus-level support for querying backplane interrupt vector
routing, and delegating machine/bridge-specific interrupt handling to the
concrete bhnd(4) driver implementation.
On bhndb(4) bridged PCI devices, we provide the PCI/MSI interrupt directly
to attached cores.
On MIPS devices, we report a backplane interrupt count of 0, effectively
disabling the bus-level interrupt assignment. This allows mips/broadcom
to temporarily continue using hard-coded MIPS IRQs until bhnd_mips PIC
support is implemented.
Reviewed by: mizhka
Approved by: adrian (mentor, implicit)
Broadcom Intensi-fi chipsets provided a common set of IP cores; on PCI/PCIe
devices, the USB11 host controller is left floating.
Approved by: adrian (mentor, implicit)
Adds support for probing and initializing bhndb(4) bridge state using
the bhnd_erom API, ensuring that full bridge configuration is available
*prior* to actually attaching and enumerating the bhnd(4) child device,
allowing us to safely allocate bus-level agent/device resources during
bhnd(4) bus enumeration.
- Add a bhnd_erom_probe() method usable by bhndb(4). This is an analogue
to the existing bhnd_erom_probe_static() method, and allows the bhndb
bridge to discover the best available erom parser class prior to newbus
probing of its children.
- Add support for supplying identification hints when probing erom
devices. This is required on early EXTIF-only chipsets, where chip
identification registers are not available.
- Migrate bhndb over to the new bhnd_erom API, using bhnd_core_info
records rather than bridged bhnd(4) device_t references to determine
the bridged chipsets' capability/bridge configuration.
- The bhndb parent (e.g. if_bwn) is now required to supply a hardware
priority table to the bridge. The default table is currently sufficient
for our supported devices.
- Drop the two-pass attach approach we used for compatibility with bhndb(4) in
the bhnd(4) bus drivers, and instead perform bus enumeration immediately,
and allocate bridged per-child bus-level resources during that enumeration.
Approved by: adrian (mentor)
Differential Revision: https://reviews.freebsd.org/D7768
- Added a generic bhnd_nvram_parser API, with support for the TLV format
used on WGT634U devices, the standard BCM NVRAM format used on most
modern devices, and the "board text file" format used on some hardware
to supply external NVRAM data at runtime (e.g. via an EFI variable).
- Extended the bhnd_bus_if and bhnd_nvram_if interfaces to support both
string-based and primitive data type variable access, required for
common behavior across both SPROM and NVRAM data sources.
- Extended the existing SPROM implementation to support the new
string-based NVRAM APIs.
- Added an abstract bhnd_nvram driver, implementing the bhnd_nvram_if
atop the bhnd_nvram_parser API.
- Added a CFE-based bhnd_nvram driver to provide read-only access to
NVRAM data on MIPS SoCs, pending implementation of a flash-aware
bhnd_nvram driver.
Approved by: adrian (mentor)
Differential Revision: https://reviews.freebsd.org/D7489
This trips me up whenever I'm fooling around with partially supported
NICs that fail to fully attach or initialise - the firmware gets loaded
and references, but something fails - and the firmware references
aren't cleaned up.
After perusing the PHY-LP code (don't ask why; honest) I discovered that
it /has/ 5GHz support - but it's not ever used. I found one NIC - a
BCM4312 w/ pci id 0x4315 - which advertised dual-band PHY-LP support.
Turns out it works.
Whilst here, move up the support bit logging code so I can use it
to debug this.
Tested:
* BCM4312 (pci id 0x4315); 5GHz STA operation
* convert phy_getinfo() to take a "gmode" flag, rather than the siba
TGSHIGH flags and then check for 2GHz. This should ensure that
gmode is set correctly even on DUALPHY NICs.
* move the siba_powerup() call and the TGSHIGH decoding into a
call to bwn_is_bus_siba(), and return an error if it's called
on anything else. We don't yet do anything else, but when we do..
Tested:
* BCM4322, 11a STA
This is all for the bhnd(4) work in progress. It's enough to probe/attach
all the bhnd internals, but we're missing OTP support and some cleanup
code. And, well, all the rest of the bhnd(4) migration.
So no, this won't give you BCM43225 support. Sorry!
That pops up in the rev 5xx / 6xx microcode on the later cores
(4312, 4322.) I'm not sure why this is happening yet and I'll
dig into it, but Linux b43 does the same thing.
* Add the new TX/RX frame formats;
* Use the right TX/RX format based on the frame info;
* Disable the 5xx firmware check, since now it should
somewhat work (but note, we don't yet use it unless
you manually add ucode11/initvals11 from the 5.x driver
to bwn-kmod-firmware;
* Misc: update some comments/debugging now I know what's
actually going on.
Tested:
* BCM4321MC, STA mode, both 4xx and 666 firmware, DMA mode
TODO:
* The newer firmware ends up logging "warn: firmware state (0)";
not sure yet what's going on there. But, yes, it still works.
I'm committing this via a BCM4321MC, 11a station, firmware
rev 666.
Obtained from: Linux b43 (TX/RX descriptor format for 5xx)
* always allocate maximum size txhdr entries
* set the right rx header offset/framesize based on firmware
This still isn't what's completely required for fw 598 support; there's
more to come.
Tested:
* Apple BCM94321MC 11abgn NIC, 11a STA mode, firmware version 4xx.
Obtained from: DragonflyBSD (txhdr entry sizing), fw 598 RX header size (linux b43)
This is an updated version of D6140.
Tested:
* BCM4321 11abgn, STA mode (11a)
Submitted by: avos
Differential Revision: https://reviews.freebsd.org/D6140
* DUALPHY in TGSHIGH tells us there's a phy that is dualband, rather than
two separate PHYs/MACs (which we almost but don't quite yet support.)
Use it.
* Add the BCM4322 PCI ID to the list of devices we don't override.
This means the 2g/5g flags are preserved, and thus we get 5GHz
operation (with N-PHY, of course.)
Tested:
* BCM4311, STA mode (11bg)
* BCM4312, STA mode (11bg)
* BCM4321, STA mode (11abg)
Sponsored by: Palm Springs
I've submitted an alternative proposal to -core about just importing
the (converted) GPL PHY code in an alternate directory under sys/gnu/
so I don't have to rewrite it all to be BSD licenced.
N-PHY and later require a lot more plcp specific setup for the PHY
to know what to transmit. I've been spoilt by the atheros, intel
and realtek parts where you don't have to hand-assemble the PLCP
but .. well, apparently Broadcom require a lot more work.
This, and PHY-N itself, was the last major missing bit to get 11a
OFDM transmit to work. Without this, CCK transmit worked but
OFDM transmit would always fail (with stat.phy_err set to 0x80.)
I have no idea what 0x80 is, and I went mad reading the broadcom
vendor driver to try and figure it out.
Tested:
* BCM4312 (PHY-LP)
* BCM4321 (PHY-N), 11a, 11bg.
Set phy-full-init always to 1 for now; PHY-N supports being able to do
partial init for things like fast channel changes but I'm going to
ignore it all.
This is a big commit with a whole lot of little changes, all in
preparation for PHY-N and rev 5xx firmware.
* add in a write method that does an explicit flush
* change the txpwr recalc type to return an enum, versus just an int.
* add in PHY-N RX frame format bits, for decoding RX RSSI and such
* add in the header space calculation for rev 5xx firmware.
* add in a whole bunch of new types that the newer and 5g phy code
needs. Notably, broadcom has a split 5GHz band concept -
5G-Low, 5G(-Mid) and 5G-High. I kept encountering this at my
day job and wondered whether it was just some marketing thing.
Nope, turns out it isn't; it's an actual PHY thing.
* Add a "am I a siba bus device" method, that returns true.
The aim is to convert all the siba/bhnd specific bits in if_bwn
over to be wrapped in this check, so when landon does a BHND
drive through he knows which bits need updating.
Now, this the /complete/ set of changes for rev 5xx firmware.
Notably, the TX descriptor handling isn't at all done yet and the
format has changed. So don' try blindly flipping this on just yet!
* Log the per-completion status out if requested
* If we get a PHY failure, the retrycnt is set to 0 and ack=0, so
the logic was incorrect. So, for ack=0, ensure we don't log
a retrycnt of 0 (or rate control breaks) or a negative retrycnt
(or rate control also breaks.)
Tested:
* BCM4321 (11abgn N-PHY), BCM4312 (LP-PHY)
* Ensure we set 20MHz wide channels (hard-coded) for PHY-N.
* Change the core rese tto take a flag saying "gmode" vesus uint32_t
flags. This is important for BCMA support where the "gmode" bit
is different.
* Refactor out the mac-phy clock reset routine (usde by PHY-N).
Tested:
* BCM4321 (PHY-N), BCM4312 (PHY-LP)
TODO:
* Checkpoint test on PHY-G hardware, just to check.
