Commit Graph

210 Commits

Author SHA1 Message Date
Aleksandr Rybalko
40bcb1d1fd Remove duplicated GEOM_PART_* options.
PR:		170931
Approved by:	adrian
2012-08-23 22:23:56 +00:00
Alexander Motin
dc0aa406db MFprojects/zfsd:
Generalize and unify ses device description.
2012-05-24 11:20:51 +00:00
Adrian Chadd
2d269a1628 Enable the AR8316 switch on the routerstation pro board.
The configuration is:

* RGMII, both ports
* arge0 - connected to PHY4 as a dedicated port (CPU port)
* arge1 - connected to the switch ports

I've verified this on my routerstation pro board.
2012-05-19 20:11:18 +00:00
Adrian Chadd
c7551b8b46 Remove duplicate config bits.
Submitted by:	juli
2012-05-12 19:43:22 +00:00
Adrian Chadd
0d96099845 Revert this - I disabled it whilst hwpmc is/was broken. 2012-05-12 17:42:22 +00:00
Adrian Chadd
1111c8313a Flip on WN1043ND switch PHY support.
* Add the i2c bitbang bus;
* Add the etherswitch/rtl8366rb drivers;
* "fix" the USB GPIO configuration so USB actually works.

Submitted by:	Stefan Bethke <stb@lassitu.de>
2012-05-12 17:41:42 +00:00
Adrian Chadd
9d9690e93b Now that there's a hint for it, add a "I'm an AR7240 switch!" hint. 2012-05-12 05:27:14 +00:00
Adrian Chadd
f7c03fa47d Add in the AP93 configuration file.
The AP93 has:

* AR7240 - mips24k processor with integrated 10/100 switch and
  various other peripherals;
* AR9283 - 2x2 2.4GHz 802.11n (with calibration data in flash);
* 64MB RAM;
* 16MB SPI flash.

The switch code detects as an AR8216 at the present moment, which isn't
_entirely_ strictly true.  However, the MII/MDIO routing in AP93.hints
works - the arge0 MAC connects to PHY4 in the switch, but via the
switch internal MDIO bus.  The switch connects to arge0's MDIO bus,
but only to export the switch registers.

Thanks to stb and ray for the switch work, and ray for helping determine
what the correct switch hints should be for this thing.
2012-05-12 04:52:59 +00:00
Adrian Chadd
411477c533 Add switch support to AP96. 2012-05-11 21:13:43 +00:00
Juli Mallett
0c8da0be6e Add basic SMP support for GXemul. Ideally we would have some way to override
some of the IPI mechanisms used by the common MIPS SMP code so we could use
the multicast IPI facilities, on GXemul as well as on several real hardware
platforms, and the ability to have multiple hard IPI types.
2012-05-07 04:36:48 +00:00
Juli Mallett
bd6c6f4249 Add a trivial driver for the GXemul Ethernet device. Probably quite buggy and
certainly non-optimal, but enough for basic networking use.

Requested by:	rwatson
2012-05-07 04:15:46 +00:00
Juli Mallett
ffbec96825 Add a driver for the GXemul test machine's disk controller and disk devices.
Prefer it to using an md device in the GXEMUL kernel configuration.

Requested by:	rwatson, theraven
2012-05-06 08:28:08 +00:00
Adrian Chadd
b846389100 In the new world order, multiphy is now when the phymask is 0x0.
This makes the TP-WN1043ND (ar913x based) work again.
2012-05-03 07:48:19 +00:00
Robert Watson
fe62958717 mips/mips64eb became mips/mips64 while I wasn't looking (whoops), so update
GXEMUL kernel config for the new world order.

Spotted by:	bz
MFC after:	3 weeks
2012-05-02 12:15:34 +00:00
Robert Watson
79ee9286f2 Merge a rudimentary gxemul "oldtestmips" port. This consists almost
entirely of one machdep file lifted from the MALTA port, as well as
a low-level console and tty driver for the gxemul debugging console
device (the emulators stdio).  As with many low-level embedded and
hypervisor console devices, it is polled only, so we drive TTY I/O
from a callout; we are perhaps a bit too aware of the MIPS physical
maps in order to attach the console before newbus comes to life.

The sample kernel configuration depends on an MD-based root file
system, which is not provided.  However, any 64-bit, big-endian
userspace image (such as one generated for MALTA) should work.

This will hopefully be supplemented by additional device drivers for
gxemul-specific hardware simulations from Juli Mallett.  We have
found oldtestmips quite useful for testing and improving aspects of
the MIPS port, so it's worth supporting better in FreeBSD.

Requested by:	theraven, jmallett
Sponsored by:	DARPA, AFRL
MFC after:	3 weeks
2012-05-02 08:10:15 +00:00
Adrian Chadd
ceec92152b Disable the pll_1000 hint for now, the upcoming work enables it and it
breaks without the switch PHY code.
2012-05-02 07:41:26 +00:00
Adrian Chadd
7a1e9887de * Force the ethernet MII configuration to be RGMII
* Populate the "pll_1000" field, which will soon be used to override the
  PLL configuration from the default value.

Obtained from:	Linux OpenWRT
2012-05-02 06:19:26 +00:00
Adrian Chadd
e4b7508aad Convert AP96 to use the mdioproxy and ARGE_MDIO option.
arge1 still works (it's the standalone PHY) but arge0 and the other switch
ports don't work.  They're enumerated though, demonstrating that the
mdiobus abstraction is correctly working.
2012-05-01 06:21:02 +00:00
Adrian Chadd
468d6f48b3 Add in the AP96 phy configuration from openwrt.
* arge0 doesn't (yet) work via the switch PHY ports; I'm not sure why.
* arge1 maps to the WAN port. That works.

TODO:

* The PLL register needs a different (non-default) value for Gigabit
  Ethernet.  The board setup code needs to be extended a bit to allow
  for non-default pll_1000 values - right now, those values come out
  of hard-coded values in the per-chip set_pll_ge() routines.

Obtained from:	Linux / OpenWRT
2012-04-15 22:59:56 +00:00
Adrian Chadd
c4b28bdc27 Flesh out the rest of the AP96 board/config. 2012-04-13 20:23:32 +00:00
Adrian Chadd
d591b27dbc * Enable ATH_EEPROM_FIRMWARE, now that it's a compile time option
* Tidy up things a bit.
2012-04-13 18:01:53 +00:00
Adrian Chadd
2c61ba4db2 These are uboot, so mark them as such or booting from flash will not work. 2012-04-13 08:56:23 +00:00
Adrian Chadd
3a8a3eebfd Introduce configuration files for AP94 and AP96.
This uses the new firmware(9) method for squirreling away the EEPROM
contents from SPI flash so ath(4) can get to them later.

It won't work out of the box just yet - you have to add this to
if_ath_pci.c:

#define ATH_EEPROM_FIRMWARE

.. until I've added it as a configuration option and updated things.
2012-04-13 08:52:25 +00:00
Juli Mallett
84db023ec1 Assume a big-endian default on MIPS and drop the "eb" suffix from MACHINE_ARCH.
This makes our naming scheme more closely match other systems and the
expectations of much third-party software.  MIPS builds which are little-endian
should require and exhibit no changes.  Big-endian TARGET_ARCHes must be
changed:
	From:		To:
	mipseb		mips
	mipsn32eb	mipsn32
	mips64eb	mips64

An entry has been added to UPDATING and some foot-shooting protection (complete
with warnings which should become errors in the near future) to the top-level
base system Makefile.
2012-03-29 02:54:35 +00:00
Jayachandran C.
4b3aada9d4 Resource allocation for XLP SoC SDHCI slots
The on-chip SD slots do not have PCI BARs corresponding to them, so
this has to be handled in the custom SoC memory allocation.

Provide memory resource for rids corresponding to BAR 0 and 1 in
the custom allocation code.
2012-03-27 15:43:32 +00:00
Jayachandran C.
2652f84c92 NOR flash driver for XLP.
The NOR interface on the SoC appears on the top level PCI bus. Add
a simple driver for this.
2012-03-27 15:16:38 +00:00
Jayachandran C.
35011d20cb xlpge : driver for XLP network accelerator
Features:
- network driver for the four 10G interfaces and two management ports
  on XLP 8xx.
- Support 4xx and 3xx variants of the processor.
- Source code and firmware building for the 16 mips32r2 micro-code engines
  in the Network Accelerator.
- Basic initialization code for Packet ordering Engine.

Submitted by:	Prabhath Raman (prabhath at netlogicmicro com)
		[refactored and fixed up for style by jchandra]
2012-03-27 14:05:12 +00:00
Jayachandran C.
9b4d140639 Opencrypto driver for XLP Security and RSA/ECC blocks
Support for the Security and RSA blocks on XLP SoC. Even though
the XLP supports many more algorithms, only the ones supported
in OCF have been added.

Submitted by:	Venkatesh J. V. (venkatesh at netlogicmicro com)
2012-03-27 11:43:46 +00:00
Jayachandran C.
8f57f9e0d7 I2C support for XLP, add hints for I2C devices and update PCI resource
allocation code.
2012-03-27 11:17:04 +00:00
Ed Schouten
92396a3174 Remove pty(4) from our kernel configurations.
As of FreeBSD 8, this driver should not be used. Applications that use
posix_openpt(2) and openpty(3) use the pts(4) that is built into the
kernel unconditionally. If it turns out high profile depend on the
pty(4) module anyway, I'd rather get those fixed. So please report any
issues to me.

The pty(4) module is still available as a kernel module of course, so a
simple `kldload pty' can be used to run old-style pseudo-terminals.
2012-03-21 08:38:42 +00:00
Juli Mallett
f8e47016ec Don't build kernel.tramp on Octeon. Probably building it should be opt-in
not opt-out, but I don't know enough about which ports need it to get the
defaults right.
2012-03-13 06:22:49 +00:00
Juli Mallett
4ea65e2064 Remove TARGET_BIG_ENDIAN which should have been removed previously. 2012-03-12 21:26:09 +00:00
Juli Mallett
379663d70b o) Use ABI, not ISA_* options, to determine whether to compile bits if libkern
required for the ABI the kernel is being built for.
   XXX This is implemented in a kind-of nasty way that involves including source
       files, but it's still an improvement.
o) Retire ISA_* options since they're unused and were always wrong.
2012-03-12 21:25:32 +00:00
Adrian Chadd
6ff44ffc53 Configuration changes/updates!
* enable ALQ and net80211/ath ALQ logging by default, to make it possible
  to get debug register traces.
* Update some comments
* Enable HWPMC for testing.
2012-03-12 20:32:23 +00:00
Adrian Chadd
f0dc1b857c Begin modifying the PB92 config file to actually generate a flashable,
bootable image.

The kernel has to fit inside an 896KiB area in a 4MB SPI flash.
So a bunch of stuff can't be included (and more is to come), including
(unfortunately) IPv6.

TODO:

* GPIO modules need to be created
* Shrink the image a bit more by removing some of the CAM layer debugging
  strings.
2012-03-12 01:15:58 +00:00
Juli Mallett
e889b2b09e We've supported 64-bit PTEs for some time. 2012-03-11 22:17:01 +00:00
Juli Mallett
9ea99cd3b5 "Did you still want the not yet? I think we just arrived at yet."
Submitted by:	thompsa
2012-03-09 09:32:20 +00:00
Juli Mallett
f6f8319094 Enable COMPAT_FREEBSD32 for the Octeon kernel config by default. 2012-03-09 07:53:44 +00:00
Attilio Rao
9c170fd168 Disable the option VFS_ALLOW_NONMPSAFE by default on all the supported
platforms.
This will make every attempt to mount a non-mpsafe filesystem to the
kernel forbidden, unless it is expressely compiled with
VFS_ALLOW_NONMPSAFE option.

This patch is part of the effort of killing non-MPSAFE filesystems
from the tree.

No MFC is expected for this patch.
2012-03-06 20:01:25 +00:00
Juli Mallett
7b7463a5d2 If an Atheros device is attached to an Octeon, it's going to be by PCI. 2012-03-02 21:44:39 +00:00
Adrian Chadd
46efd63a5b Build some more things (random, bridge/gif/gre, gpio, USB) as modules as well
so some embedded platform builds can use these instead of a fully monolithic
kernel.
2012-01-15 19:43:56 +00:00
Adrian Chadd
8f5aa976d7 This isn't required any longer - it turns out the flash
has ~ 1.7MB of space for a kernel.  There's thus plenty of
space for a full, non-module kernel.
2012-01-05 07:19:05 +00:00
Adrian Chadd
b018dade46 Use geom_uncompress now, rather than geom_uzip.
This results in a much smaller rootfs image and it easily
fits in the 8MB flash.
2012-01-05 03:38:34 +00:00
Adrian Chadd
a92de4a5f6 This particular work around isn't required any longer, now that the
11n radio backends are also added into the RF linker set.

This saves around 7k from the kernel binary.
2011-12-31 23:41:19 +00:00
Adrian Chadd
b2e6077c31 Oops - this was referencing a local file, which I've done away with. 2011-12-31 15:56:00 +00:00
Adrian Chadd
38192bfc9f Add a configuration file for the Atheros PB47 reference board.
This is an AR71xx based board with 8MB flash, 64MB RAM, a
Mini-PCI+ slot (see below) and a single 10/100/1000baseT
ethernet port.  It also has two USB ports.

This is an easier board than most to add as it doesn't have a
switch PHY on-board.  This made it (mostly) trivial to craft a
working configuration.

Things to note:

* This, like most other reference boards, use uboot rather then
  redboot.  It means that you typically have to manually flash
  both the kernel and rootfs partitions.

* Since there's currently no (nice) way to extract out the
  ethernet MAC and RAM from the uboot environment, the RAM
  will default to 32mb and the MAC will be something very
  incorrect.   I'll try to fix this up in a subsequent commit
  or two, even if it's just some hard-coded nonsense in
  ar71xx_machdep.c for now.

* The board is designed for a specific model of mini-PCI+
  NIC which never made it into production.  Normal mini-PCI
  NICs will work fine; if you happen to have the NIC in question
  then it will work fine with this board.
2011-12-30 09:48:35 +00:00
Adrian Chadd
687021dd92 Add a couple of missing wlan modules. 2011-12-30 09:39:24 +00:00
Adrian Chadd
425fc5768b Flesh out the RSPRO GPIO config, including the RF LED. 2011-12-29 06:07:24 +00:00
Adrian Chadd
530028c9d6 Break out the AR71XX config file into _BASE and board specific
bits.

The ROUERSTATION and RSPRO variants contain:

* the board specific bits (eg the RTC for RSPRO, later on it'll
  include the GPIO/LED definitions);
* the boot specific bits (eg, on-board flash, usb flash, etc).

For now the AR71XX_BASE file contains the common board config,
drivers and net80211/ath wireless drivers.

I'll follow this up with config files for the other boards I
have (eg the Ubiquiti LSSR71, as well as some Mikrotik boards
that use the AR71XX and atheros reference boards) which will
be quite easy to do now.
2011-12-29 05:51:48 +00:00
Adrian Chadd
3f9bdcef12 * Add in the gpio/gpioled drivers into AR91XX_BASE.
* Add in a default GPIO section for AR91XX_BASE.hints, which doesn't
  define the GPIO function masks or any GPIO pines.
* Add in the GPIO line definitions for LEDs and GPIO pins for the
  TP-WR1043nd.

I've verified the LEDs work fine using gpioset.
2011-12-15 01:05:38 +00:00