Marius Strobl
a4eba4a555
For cheetah-class CPUs ensure that the dt512_0 is set to hold 8k pages
...
for all three contexts and configure the dt512_1 to hold 4MB pages for
them (e.g. for direct mappings).
This might allow for additional optimization by using the faulting
page sizes provided by AA_DMMU_TAG_ACCESS_EXT for bypassing the page
size walker for the dt512 in the superpage support code.
Submitted by: nwhitehorn (initial patch)
2008-09-08 21:24:25 +00:00
Marius Strobl
6557990017
cosmetic changes and style fixes
2008-08-13 20:30:28 +00:00
Kip Macy
a9928b2f58
unbreak sparc64 loader build
...
re-add accidentally deleted asi value
remove sun4v only header include
Approved by: rwatson (mentor)
Reviewed by: jmg
2006-10-09 05:59:04 +00:00
Kip Macy
25e328499c
kernel clean up to make the sun4v kernel build
...
Reviewed by: jmg
Approved by: rwatson (mentor)
2006-10-09 04:45:19 +00:00
Marius Strobl
93ff2bd5f8
Add convenience macros for the bits in ASI_ESTATE_ERROR_EN_REG (used
...
for ECC handling) and the additional uses of the ASIs 0x77 and 0x7f
as well as their bits (used for a CPU bug workaround).
MFC after: 3 days
2006-03-29 00:08:48 +00:00
Thomas Moestl
63ebf186a7
Add ASI definitions of UltraSPARC-III (Cu) processors, and add some
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previously missing US-I and II ones.
2002-07-16 16:22:25 +00:00
Jake Burkholder
3a3b7ddc5a
Add asis for the upa config reg, which contains the hardware cpu id, and
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for the interrupt send register, which is used for dispatching ipis.
2002-01-08 04:29:50 +00:00
Thomas Moestl
7478d2e8b2
Header file updates needed for the cache code: add/correct some ASI
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definitions and add PAGE_*_MIN and -_MAX macros.
2001-11-09 19:37:52 +00:00
Jake Burkholder
e19e5d8968
The definition for ASI_IMMU_TAG_TARGET_REG was wrong. Sort.
2001-09-03 22:02:15 +00:00
Jake Burkholder
2b31cfd3a0
Add a definition for the load store unit control register.
2001-08-20 23:31:41 +00:00
Jake Burkholder
c13c9cbf4f
Add asis for interrupt registers.
2001-08-10 04:17:29 +00:00
David E. O'Brien
73a4930297
The author isn't a [UC] Regents. Correct the copyright language.
2001-08-09 02:09:34 +00:00
Thomas Moestl
e64b70af32
Add floating point context switching code for sparc64.
...
Reviewed by: jake
2001-08-04 18:55:15 +00:00
Jake Burkholder
89bf8575ee
Flesh out the sparc64 port considerably. This contains:
...
- mostly complete kernel pmap support, and tested but currently turned
off userland pmap support
- low level assembly language trap, context switching and support code
- fully implemented atomic.h and supporting cpufunc.h
- some support for kernel debugging with ddb
- various header tweaks and filling out of machine dependent structures
2001-07-31 06:05:05 +00:00
