882a54f65f
- changes in support of the VLAN filter fix to 126850 - removal of a bunch of legacy code that was cruft, if not possibly harmful. - removal of POLLING from this driver, with multiqueue and MSIX it just makes no sense here. - Fix an LRO bug that I've been working on internally, intermittent panics under stress, the problem was releasing the RX ring lock before the LRO flushing. - Following the above fix I now enable LRO by default - For performance reasons increase the default number of RX queues to 4. - Add AIM - "Adaptive Interrupt Moderation", a fancy way of saying that the EITR value is dynamically changed based on the size of packets in the last interrupt interval. - Much goodness to try, enjoy!!
469 lines
15 KiB
C
469 lines
15 KiB
C
/******************************************************************************
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Copyright (c) 2001-2008, Intel Corporation
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice,
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this list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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3. Neither the name of the Intel Corporation nor the names of its
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contributors may be used to endorse or promote products derived from
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this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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POSSIBILITY OF SUCH DAMAGE.
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******************************************************************************/
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/*$FreeBSD$*/
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#ifndef _IGB_H_DEFINED_
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#define _IGB_H_DEFINED_
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/* Tunables */
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/*
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* IGB_TXD: Maximum number of Transmit Descriptors
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*
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* This value is the number of transmit descriptors allocated by the driver.
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* Increasing this value allows the driver to queue more transmits. Each
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* descriptor is 16 bytes.
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* Since TDLEN should be multiple of 128bytes, the number of transmit
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* desscriptors should meet the following condition.
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* (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0
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*/
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#define IGB_MIN_TXD 80
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#define IGB_DEFAULT_TXD 256
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#define IGB_MAX_TXD 4096
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/*
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* IGB_RXD: Maximum number of Transmit Descriptors
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*
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* This value is the number of receive descriptors allocated by the driver.
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* Increasing this value allows the driver to buffer more incoming packets.
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* Each descriptor is 16 bytes. A receive buffer is also allocated for each
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* descriptor. The maximum MTU size is 16110.
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* Since TDLEN should be multiple of 128bytes, the number of transmit
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* desscriptors should meet the following condition.
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* (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0
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*/
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#define IGB_MIN_RXD 80
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#define IGB_DEFAULT_RXD 256
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#define IGB_MAX_RXD 4096
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/*
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* IGB_TIDV - Transmit Interrupt Delay Value
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* Valid Range: 0-65535 (0=off)
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* Default Value: 64
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* This value delays the generation of transmit interrupts in units of
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* 1.024 microseconds. Transmit interrupt reduction can improve CPU
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* efficiency if properly tuned for specific network traffic. If the
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* system is reporting dropped transmits, this value may be set too high
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* causing the driver to run out of available transmit descriptors.
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*/
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#define IGB_TIDV 64
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/*
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* IGB_TADV - Transmit Absolute Interrupt Delay Value
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* Valid Range: 0-65535 (0=off)
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* Default Value: 64
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* This value, in units of 1.024 microseconds, limits the delay in which a
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* transmit interrupt is generated. Useful only if IGB_TIDV is non-zero,
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* this value ensures that an interrupt is generated after the initial
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* packet is sent on the wire within the set amount of time. Proper tuning,
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* along with IGB_TIDV, may improve traffic throughput in specific
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* network conditions.
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*/
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#define IGB_TADV 64
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/*
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* IGB_RDTR - Receive Interrupt Delay Timer (Packet Timer)
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* Valid Range: 0-65535 (0=off)
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* Default Value: 0
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* This value delays the generation of receive interrupts in units of 1.024
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* microseconds. Receive interrupt reduction can improve CPU efficiency if
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* properly tuned for specific network traffic. Increasing this value adds
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* extra latency to frame reception and can end up decreasing the throughput
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* of TCP traffic. If the system is reporting dropped receives, this value
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* may be set too high, causing the driver to run out of available receive
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* descriptors.
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*
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* CAUTION: When setting IGB_RDTR to a value other than 0, adapters
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* may hang (stop transmitting) under certain network conditions.
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* If this occurs a WATCHDOG message is logged in the system
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* event log. In addition, the controller is automatically reset,
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* restoring the network connection. To eliminate the potential
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* for the hang ensure that IGB_RDTR is set to 0.
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*/
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#define IGB_RDTR 0
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/*
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* Receive Interrupt Absolute Delay Timer (Not valid for 82542/82543/82544)
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* Valid Range: 0-65535 (0=off)
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* Default Value: 64
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* This value, in units of 1.024 microseconds, limits the delay in which a
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* receive interrupt is generated. Useful only if IGB_RDTR is non-zero,
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* this value ensures that an interrupt is generated after the initial
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* packet is received within the set amount of time. Proper tuning,
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* along with IGB_RDTR, may improve traffic throughput in specific network
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* conditions.
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*/
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#define IGB_RADV 64
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/*
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* This parameter controls the duration of transmit watchdog timer.
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*/
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#define IGB_TX_TIMEOUT 5 /* set to 5 seconds */
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/*
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* This parameter controls when the driver calls the routine to reclaim
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* transmit descriptors.
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*/
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#define IGB_TX_CLEANUP_THRESHOLD (adapter->num_tx_desc / 8)
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#define IGB_TX_OP_THRESHOLD (adapter->num_tx_desc / 32)
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/*
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* This parameter controls whether or not autonegotation is enabled.
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* 0 - Disable autonegotiation
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* 1 - Enable autonegotiation
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*/
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#define DO_AUTO_NEG 1
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/*
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* This parameter control whether or not the driver will wait for
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* autonegotiation to complete.
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* 1 - Wait for autonegotiation to complete
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* 0 - Don't wait for autonegotiation to complete
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*/
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#define WAIT_FOR_AUTO_NEG_DEFAULT 0
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/* Tunables -- End */
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#define AUTONEG_ADV_DEFAULT (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \
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ADVERTISE_100_HALF | ADVERTISE_100_FULL | \
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ADVERTISE_1000_FULL)
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#define AUTO_ALL_MODES 0
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/* PHY master/slave setting */
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#define IGB_MASTER_SLAVE e1000_ms_hw_default
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/*
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* Micellaneous constants
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*/
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#define IGB_VENDOR_ID 0x8086
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#define IGB_JUMBO_PBA 0x00000028
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#define IGB_DEFAULT_PBA 0x00000030
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#define IGB_SMARTSPEED_DOWNSHIFT 3
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#define IGB_SMARTSPEED_MAX 15
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#define IGB_MAX_INTR 10
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#define IGB_RX_PTHRESH 16
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#define IGB_RX_HTHRESH 8
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#define IGB_RX_WTHRESH 1
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#define MAX_NUM_MULTICAST_ADDRESSES 128
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#define PCI_ANY_ID (~0U)
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#define ETHER_ALIGN 2
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#define IGB_TX_BUFFER_SIZE ((uint32_t) 1514)
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#define IGB_FC_PAUSE_TIME 0x0680
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#define IGB_EEPROM_APME 0x400;
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#define MAX_INTS_PER_SEC 8000
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#define DEFAULT_ITR 1000000000/(MAX_INTS_PER_SEC * 256)
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/* Code compatilbility between 6 and 7 */
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#ifndef ETHER_BPF_MTAP
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#define ETHER_BPF_MTAP BPF_MTAP
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#endif
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/*
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* TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be
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* multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary. This will
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* also optimize cache line size effect. H/W supports up to cache line size 128.
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*/
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#define IGB_DBA_ALIGN 128
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#define SPEED_MODE_BIT (1<<21) /* On PCI-E MACs only */
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/* PCI Config defines */
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#define IGB_MSIX_BAR 3
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/*
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** This is the total number of MSIX vectors you wish
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** to use, it also controls the size of resources.
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** The 82575 has a total of 10, 82576 has 25. Set this
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** to the real amount you need to streamline data storage.
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*/
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#define IGB_MSIX_VEC 6 /* MSIX vectors configured */
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/* Defines for printing debug information */
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#define DEBUG_INIT 0
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#define DEBUG_IOCTL 0
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#define DEBUG_HW 0
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#define INIT_DEBUGOUT(S) if (DEBUG_INIT) printf(S "\n")
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#define INIT_DEBUGOUT1(S, A) if (DEBUG_INIT) printf(S "\n", A)
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#define INIT_DEBUGOUT2(S, A, B) if (DEBUG_INIT) printf(S "\n", A, B)
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#define IOCTL_DEBUGOUT(S) if (DEBUG_IOCTL) printf(S "\n")
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#define IOCTL_DEBUGOUT1(S, A) if (DEBUG_IOCTL) printf(S "\n", A)
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#define IOCTL_DEBUGOUT2(S, A, B) if (DEBUG_IOCTL) printf(S "\n", A, B)
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#define HW_DEBUGOUT(S) if (DEBUG_HW) printf(S "\n")
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#define HW_DEBUGOUT1(S, A) if (DEBUG_HW) printf(S "\n", A)
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#define HW_DEBUGOUT2(S, A, B) if (DEBUG_HW) printf(S "\n", A, B)
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#define IGB_MAX_SCATTER 64
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#define IGB_TSO_SIZE (65535 + sizeof(struct ether_vlan_header))
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#define IGB_TSO_SEG_SIZE 4096 /* Max dma segment size */
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#define ETH_ZLEN 60
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#define ETH_ADDR_LEN 6
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#define CSUM_OFFLOAD 7 /* Offload bits in mbuf flag */
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/*
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* Interrupt Moderation parameters
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*/
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#define IGB_LOW_LATENCY 128
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#define IGB_AVE_LATENCY 450
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#define IGB_BULK_LATENCY 1200
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#define IGB_LINK_ITR 2000
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#ifdef IGB_TIMESYNC
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/* Precision Time Sync (IEEE 1588) defines */
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#define ETHERTYPE_IEEE1588 0x88F7
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#define PICOSECS_PER_TICK 20833
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#define TSYNC_PORT 319 /* UDP port for the protocol */
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/* TIMESYNC IOCTL defines */
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#define IGB_TIMESYNC_READTS _IOWR('i', 127, struct igb_tsync_read)
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#define IGB_TIMESTAMP 5 /* A unique return value */
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/* Used in the READTS IOCTL */
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struct igb_tsync_read {
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int read_current_time;
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struct timespec system_time;
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u64 network_time;
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u64 rx_stamp;
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u64 tx_stamp;
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u16 seqid;
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unsigned char srcid[6];
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int rx_valid;
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int tx_valid;
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};
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#endif /* IGB_TIMESYNC */
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struct adapter; /* forward reference */
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struct igb_int_delay_info {
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struct adapter *adapter; /* Back-pointer to the adapter struct */
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int offset; /* Register offset to read/write */
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int value; /* Current value in usecs */
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};
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/*
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* Bus dma allocation structure used by
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* e1000_dma_malloc and e1000_dma_free.
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*/
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struct igb_dma_alloc {
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bus_addr_t dma_paddr;
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caddr_t dma_vaddr;
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bus_dma_tag_t dma_tag;
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bus_dmamap_t dma_map;
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bus_dma_segment_t dma_seg;
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int dma_nseg;
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};
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/*
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* Transmit ring: one per tx queue
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*/
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struct tx_ring {
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struct adapter *adapter;
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u32 me;
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u32 msix; /* This ring's MSIX vector */
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u32 eims; /* This ring's EIMS bit */
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struct mtx tx_mtx;
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char mtx_name[16];
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struct igb_dma_alloc txdma; /* bus_dma glue for tx desc */
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struct e1000_tx_desc *tx_base;
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struct task tx_task; /* cleanup tasklet */
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u32 next_avail_desc;
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u32 next_to_clean;
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volatile u16 tx_avail;
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struct igb_buffer *tx_buffers;
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bus_dma_tag_t txtag; /* dma tag for tx */
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u32 watchdog_timer;
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u64 no_desc_avail;
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u64 tx_irq;
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u64 tx_packets;
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};
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/*
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* Receive ring: one per rx queue
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*/
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struct rx_ring {
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struct adapter *adapter;
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u32 me;
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u32 msix; /* This ring's MSIX vector */
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u32 eims; /* This ring's EIMS bit */
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struct igb_dma_alloc rxdma; /* bus_dma glue for tx desc */
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union e1000_adv_rx_desc *rx_base;
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struct lro_ctrl lro;
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struct task rx_task; /* cleanup tasklet */
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struct mtx rx_mtx;
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char mtx_name[16];
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u32 last_cleaned;
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u32 next_to_check;
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struct igb_buffer *rx_buffers;
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bus_dma_tag_t rxtag; /* dma tag for tx */
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bus_dmamap_t rx_spare_map;
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/*
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* First/last mbuf pointers, for
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* collecting multisegment RX packets.
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*/
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struct mbuf *fmp;
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struct mbuf *lmp;
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u32 bytes;
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u32 eitr_setting;
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/* Soft stats */
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u64 rx_irq;
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u64 rx_packets;
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u64 rx_bytes;
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};
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struct adapter {
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struct ifnet *ifp;
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struct e1000_hw hw;
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/* FreeBSD operating-system-specific structures. */
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struct e1000_osdep osdep;
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struct device *dev;
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struct resource *pci_mem;
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struct resource *msix_mem;
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struct resource *res[IGB_MSIX_VEC];
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void *tag[IGB_MSIX_VEC];
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int rid[IGB_MSIX_VEC];
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u32 eims_mask;
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int linkvec;
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int link_mask;
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int link_irq;
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struct ifmedia media;
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struct callout timer;
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int msix; /* total vectors allocated */
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int if_flags;
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int max_frame_size;
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int min_frame_size;
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struct mtx core_mtx;
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int igb_insert_vlan_header;
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struct task link_task;
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struct task rxtx_task;
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struct taskqueue *tq; /* private task queue */
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eventhandler_tag vlan_attach;
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eventhandler_tag vlan_detach;
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/* Management and WOL features */
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int wol;
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int has_manage;
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/* Info about the board itself */
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u8 link_active;
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u16 link_speed;
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u16 link_duplex;
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u32 smartspeed;
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/*
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* Transmit rings
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*/
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struct tx_ring *tx_rings;
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u16 num_tx_desc;
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u16 num_tx_queues;
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u32 txd_cmd;
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/*
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* Receive rings
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*/
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struct rx_ring *rx_rings;
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u16 num_rx_desc;
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u16 num_rx_queues;
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int rx_process_limit;
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u32 rx_buffer_len;
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/* Misc stats maintained by the driver */
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unsigned long dropped_pkts;
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unsigned long mbuf_alloc_failed;
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unsigned long mbuf_cluster_failed;
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unsigned long no_tx_map_avail;
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unsigned long no_tx_dma_setup;
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unsigned long watchdog_events;
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unsigned long rx_overruns;
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boolean_t in_detach;
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#ifdef IGB_TIMESYNC
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u64 last_stamp;
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u64 last_sec;
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u32 last_ns;
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#endif
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struct e1000_hw_stats stats;
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};
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/* ******************************************************************************
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* vendor_info_array
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*
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* This array contains the list of Subvendor/Subdevice IDs on which the driver
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* should load.
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*
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* ******************************************************************************/
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typedef struct _igb_vendor_info_t {
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unsigned int vendor_id;
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unsigned int device_id;
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unsigned int subvendor_id;
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unsigned int subdevice_id;
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unsigned int index;
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} igb_vendor_info_t;
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struct igb_buffer {
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int next_eop; /* Index of the desc to watch */
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struct mbuf *m_head;
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bus_dmamap_t map; /* bus_dma map for packet */
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};
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#define IGB_CORE_LOCK_INIT(_sc, _name) \
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mtx_init(&(_sc)->core_mtx, _name, "IGB Core Lock", MTX_DEF)
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#define IGB_CORE_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->core_mtx)
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#define IGB_TX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->tx_mtx)
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#define IGB_RX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->rx_mtx)
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#define IGB_CORE_LOCK(_sc) mtx_lock(&(_sc)->core_mtx)
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#define IGB_TX_LOCK(_sc) mtx_lock(&(_sc)->tx_mtx)
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#define IGB_RX_LOCK(_sc) mtx_lock(&(_sc)->rx_mtx)
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#define IGB_CORE_UNLOCK(_sc) mtx_unlock(&(_sc)->core_mtx)
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#define IGB_TX_UNLOCK(_sc) mtx_unlock(&(_sc)->tx_mtx)
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#define IGB_RX_UNLOCK(_sc) mtx_unlock(&(_sc)->rx_mtx)
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#define IGB_CORE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->core_mtx, MA_OWNED)
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#define IGB_TX_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->tx_mtx, MA_OWNED)
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#endif /* _IGB_H_DEFINED_ */
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