207 lines
6.6 KiB
Markdown
207 lines
6.6 KiB
Markdown
;; AMD Athlon Scheduling
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;; Copyright (C) 2002 Free Software Foundation, Inc.
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;;
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;; This file is part of GNU CC.
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;;
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;; GNU CC is free software; you can redistribute it and/or modify
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;; it under the terms of the GNU General Public License as published by
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;; the Free Software Foundation; either version 2, or (at your option)
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;; any later version.
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;;
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;; GNU CC is distributed in the hope that it will be useful,
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;; but WITHOUT ANY WARRANTY; without even the implied warranty of
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;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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;; GNU General Public License for more details.
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;;
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;; You should have received a copy of the GNU General Public License
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;; along with GNU CC; see the file COPYING. If not, write to
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;; the Free Software Foundation, 59 Temple Place - Suite 330,
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;; Boston, MA 02111-1307, USA. */
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(define_attr "athlon_decode" "direct,vector"
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(cond [(eq_attr "type" "call,imul,idiv,other,multi,fcmov,fpspc,str,pop,cld,fcmov")
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(const_string "vector")
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(and (eq_attr "type" "push")
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(match_operand 1 "memory_operand" ""))
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(const_string "vector")
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(and (eq_attr "type" "fmov")
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(and (eq_attr "memory" "load,store")
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(eq_attr "mode" "XF")))
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(const_string "vector")]
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(const_string "direct")))
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;; The Athlon does contain three pipelined FP units, three integer units and
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;; three address generation units.
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;;
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;; The predecode logic is determining boundaries of instructions in the 64
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;; byte cache line. So the cache line straddling problem of K6 might be issue
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;; here as well, but it is not noted in the documentation.
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;;
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;; Three DirectPath instructions decoders and only one VectorPath decoder
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;; is available. They can decode three DirectPath instructions or one VectorPath
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;; instruction per cycle.
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;; Decoded macro instructions are then passed to 72 entry instruction control
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;; unit, that passes
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;; it to the specialized integer (18 entry) and fp (36 entry) schedulers.
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;;
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;; The load/store queue unit is not attached to the schedulers but
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;; communicates with all the execution units separately instead.
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(define_function_unit "athlon_vectordec" 1 0
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(and (eq_attr "cpu" "athlon")
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(eq_attr "athlon_decode" "vector"))
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1 1)
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(define_function_unit "athlon_directdec" 3 0
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(and (eq_attr "cpu" "athlon")
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(eq_attr "athlon_decode" "direct"))
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1 1)
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(define_function_unit "athlon_vectordec" 1 0
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(and (eq_attr "cpu" "athlon")
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(eq_attr "athlon_decode" "direct"))
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1 1 [(eq_attr "athlon_decode" "vector")])
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(define_function_unit "athlon_ieu" 3 0
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(and (eq_attr "cpu" "athlon")
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(eq_attr "type" "alu1,negnot,alu,icmp,test,imov,imovx,lea,incdec,ishift,ishift1,rotate,rotate1,ibr,call,callv,icmov,cld,pop,setcc,push,pop"))
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1 1)
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(define_function_unit "athlon_ieu" 3 0
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(and (eq_attr "cpu" "athlon")
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(eq_attr "type" "str"))
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15 15)
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(define_function_unit "athlon_ieu" 3 0
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(and (eq_attr "cpu" "athlon")
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(eq_attr "type" "imul"))
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5 0)
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(define_function_unit "athlon_ieu" 3 0
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(and (eq_attr "cpu" "athlon")
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(eq_attr "type" "idiv"))
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42 0)
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(define_function_unit "athlon_muldiv" 1 0
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(and (eq_attr "cpu" "athlon")
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(eq_attr "type" "imul"))
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5 0)
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(define_function_unit "athlon_muldiv" 1 0
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(and (eq_attr "cpu" "athlon")
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(eq_attr "type" "idiv"))
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42 42)
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(define_attr "athlon_fpunits" "none,store,mul,add,muladd,any"
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(cond [(eq_attr "type" "fop,fcmp,fistp")
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(const_string "add")
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(eq_attr "type" "fmul,fdiv,fpspc,fsgn,fcmov")
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(const_string "mul")
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(and (eq_attr "type" "fmov") (eq_attr "memory" "store,both"))
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(const_string "store")
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(and (eq_attr "type" "fmov") (eq_attr "memory" "load"))
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(const_string "any")
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(and (eq_attr "type" "fmov")
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(ior (match_operand:SI 1 "register_operand" "")
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(match_operand 1 "immediate_operand" "")))
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(const_string "store")
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(eq_attr "type" "fmov")
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(const_string "muladd")]
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(const_string "none")))
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;; We use latencies 1 for definitions. This is OK to model colisions
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;; in execution units. The real latencies are modeled in the "fp" pipeline.
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;; fsin, fcos: 96-192
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;; fsincos: 107-211
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;; fsqrt: 19 for SFmode, 27 for DFmode, 35 for XFmode.
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(define_function_unit "athlon_fp" 3 0
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(and (eq_attr "cpu" "athlon")
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(eq_attr "type" "fpspc"))
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100 1)
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;; 16 cycles for SFmode, 20 for DFmode and 24 for XFmode.
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(define_function_unit "athlon_fp" 3 0
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(and (eq_attr "cpu" "athlon")
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(eq_attr "type" "fdiv"))
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24 1)
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(define_function_unit "athlon_fp" 3 0
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(and (eq_attr "cpu" "athlon")
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(eq_attr "type" "fop,fmul,fistp"))
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4 1)
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;; XFmode loads are slow.
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;; XFmode store is slow too (8 cycles), but we don't need to model it, because
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;; there are no dependent instructions.
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(define_function_unit "athlon_fp" 3 0
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(and (eq_attr "cpu" "athlon")
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(and (eq_attr "type" "fmov")
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(and (eq_attr "memory" "load")
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(eq_attr "mode" "XF"))))
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10 1)
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(define_function_unit "athlon_fp" 3 0
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(and (eq_attr "cpu" "athlon")
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(eq_attr "type" "fmov,fsgn"))
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2 1)
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;; fcmp and ftst instructions
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(define_function_unit "athlon_fp" 3 0
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(and (eq_attr "cpu" "athlon")
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(and (eq_attr "type" "fcmp")
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(eq_attr "athlon_decode" "direct")))
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3 1)
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;; fcmpi instructions.
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(define_function_unit "athlon_fp" 3 0
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(and (eq_attr "cpu" "athlon")
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(and (eq_attr "type" "fcmp")
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(eq_attr "athlon_decode" "vector")))
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3 1)
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(define_function_unit "athlon_fp" 3 0
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(and (eq_attr "cpu" "athlon")
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(eq_attr "type" "fcmov"))
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7 1)
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(define_function_unit "athlon_fp_mul" 1 0
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(and (eq_attr "cpu" "athlon")
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(eq_attr "athlon_fpunits" "mul"))
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1 1)
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(define_function_unit "athlon_fp_add" 1 0
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(and (eq_attr "cpu" "athlon")
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(eq_attr "athlon_fpunits" "add"))
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1 1)
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(define_function_unit "athlon_fp_muladd" 2 0
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(and (eq_attr "cpu" "athlon")
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(eq_attr "athlon_fpunits" "muladd,mul,add"))
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1 1)
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(define_function_unit "athlon_fp_store" 1 0
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(and (eq_attr "cpu" "athlon")
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(eq_attr "athlon_fpunits" "store"))
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1 1)
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;; We don't need to model the Address Generation Unit, since we don't model
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;; the re-order buffer yet and thus we never schedule more than three operations
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;; at time. Later we may want to experiment with MD_SCHED macros modeling the
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;; decoders independently on the functional units.
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;(define_function_unit "athlon_agu" 3 0
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; (and (eq_attr "cpu" "athlon")
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; (and (eq_attr "memory" "!none")
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; (eq_attr "athlon_fpunits" "none")))
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; 1 1)
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;; Model load unit to avoid too long sequences of loads. We don't need to
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;; model store queue, since it is hardly going to be bottleneck.
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(define_function_unit "athlon_load" 2 0
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(and (eq_attr "cpu" "athlon")
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(eq_attr "memory" "load,both"))
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1 1)
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