freebsd-nq/i386.md at 31a119f3ede3e46847ca7849e70407c96e04d1f3

Alexander Kabaev 31a119f3ed Stock files.

2005-06-03 03:50:42 +00:00

738 KiB

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;; GCC machine description for IA-32 and x86-64. ;; Copyright (C) 1988, 1994, 1995, 1996, 1997, 1998, 1999, 2000, ;; 2001, 2002, 2003, 2004 ;; Free Software Foundation, Inc. ;; Mostly by William Schelter. ;; x86_64 support added by Jan Hubicka ;; ;; This file is part of GCC. ;; ;; GCC is free software; you can redistribute it and/or modify ;; it under the terms of the GNU General Public License as published by ;; the Free Software Foundation; either version 2, or (at your option) ;; any later version. ;; ;; GCC is distributed in the hope that it will be useful, ;; but WITHOUT ANY WARRANTY; without even the implied warranty of ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ;; GNU General Public License for more details. ;; ;; You should have received a copy of the GNU General Public License ;; along with GCC; see the file COPYING. If not, write to ;; the Free Software Foundation, 59 Temple Place - Suite 330, ;; Boston, MA 02111-1307, USA. / ;; ;; The original PO technology requires these to be ordered by speed, ;; so that assigner will pick the fastest. ;; ;; See file "rtl.def" for documentation on define_insn, match_, et. al. ;; ;; Macro REG_CLASS_FROM_LETTER in file i386.h defines the register ;; constraint letters. ;; ;; The special asm out single letter directives following a '%' are: ;; 'z' mov%z1 would be movl, movw, or movb depending on the mode of ;; operands[1]. ;; 'L' Print the opcode suffix for a 32-bit integer opcode. ;; 'W' Print the opcode suffix for a 16-bit integer opcode. ;; 'B' Print the opcode suffix for an 8-bit integer opcode. ;; 'Q' Print the opcode suffix for a 64-bit float opcode. ;; 'S' Print the opcode suffix for a 32-bit float opcode. ;; 'T' Print the opcode suffix for an 80-bit extended real XFmode float opcode. ;; 'J' Print the appropriate jump operand. ;; ;; 'b' Print the QImode name of the register for the indicated operand. ;; %b0 would print %al if operands[0] is reg 0. ;; 'w' Likewise, print the HImode name of the register. ;; 'k' Likewise, print the SImode name of the register. ;; 'h' Print the QImode name for a "high" register, either ah, bh, ch or dh. ;; 'y' Print "st(0)" instead of "st" as a register.

;; UNSPEC usage:

(define_constants [; Relocation specifiers (UNSPEC_GOT 0) (UNSPEC_GOTOFF 1) (UNSPEC_GOTPCREL 2) (UNSPEC_GOTTPOFF 3) (UNSPEC_TPOFF 4) (UNSPEC_NTPOFF 5) (UNSPEC_DTPOFF 6) (UNSPEC_GOTNTPOFF 7) (UNSPEC_INDNTPOFF 8)

; Prologue support (UNSPEC_STACK_ALLOC 11) (UNSPEC_SET_GOT 12) (UNSPEC_SSE_PROLOGUE_SAVE 13)

; TLS support (UNSPEC_TP 15) (UNSPEC_TLS_GD 16) (UNSPEC_TLS_LD_BASE 17)

; Other random patterns (UNSPEC_SCAS 20) (UNSPEC_SIN 21) (UNSPEC_COS 22) (UNSPEC_FNSTSW 24) (UNSPEC_SAHF 25) (UNSPEC_FSTCW 26) (UNSPEC_ADD_CARRY 27) (UNSPEC_FLDCW 28)

; For SSE/MMX support: (UNSPEC_FIX 30) (UNSPEC_MASKMOV 32) (UNSPEC_MOVMSK 33) (UNSPEC_MOVNT 34) (UNSPEC_MOVA 38) (UNSPEC_MOVU 39) (UNSPEC_SHUFFLE 41) (UNSPEC_RCP 42) (UNSPEC_RSQRT 43) (UNSPEC_SFENCE 44) (UNSPEC_NOP 45) ; prevents combiner cleverness (UNSPEC_PAVGUSB 49) (UNSPEC_PFRCP 50) (UNSPEC_PFRCPIT1 51) (UNSPEC_PFRCPIT2 52) (UNSPEC_PFRSQRT 53) (UNSPEC_PFRSQIT1 54) (UNSPEC_PSHUFLW 55) (UNSPEC_PSHUFHW 56) (UNSPEC_MFENCE 59) (UNSPEC_LFENCE 60) (UNSPEC_PSADBW 61) (UNSPEC_ADDSUB 71) (UNSPEC_HADD 72) (UNSPEC_HSUB 73) (UNSPEC_MOVSHDUP 74) (UNSPEC_MOVSLDUP 75) (UNSPEC_LDQQU 76) (UNSPEC_MOVDDUP 77)

; x87 Floating point (UNSPEC_FPATAN 65) (UNSPEC_FYL2X 66) (UNSPEC_FSCALE 67) (UNSPEC_FRNDINT 68) (UNSPEC_F2XM1 69)

; REP instruction (UNSPEC_REP 75) ])

(define_constants [(UNSPECV_BLOCKAGE 0) (UNSPECV_STACK_PROBE 10) (UNSPECV_EH_RETURN 13) (UNSPECV_EMMS 31) (UNSPECV_LDMXCSR 37) (UNSPECV_STMXCSR 40) (UNSPECV_FEMMS 46) (UNSPECV_CLFLUSH 57) (UNSPECV_ALIGN 68) (UNSPECV_MONITOR 69) (UNSPECV_MWAIT 70) ])

;; Insns whose names begin with "x86_" are emitted by gen_FOO calls ;; from i386.c.

;; In C guard expressions, put expressions which may be compile-time ;; constants first. This allows for better optimization. For ;; example, write "TARGET_64BIT && reload_completed", not ;; "reload_completed && TARGET_64BIT".

;; Processor type. This attribute must exactly match the processor_type ;; enumeration in i386.h. (define_attr "cpu" "i386,i486,pentium,pentiumpro,k6,athlon,pentium4,k8" (const (symbol_ref "ix86_tune")))

;; A basic instruction type. Refinements due to arguments to be ;; provided in other attributes. (define_attr "type" "other,multi, alu,alu1,negnot,imov,imovx,lea, incdec,ishift,ishift1,rotate,rotate1,imul,idiv, icmp,test,ibr,setcc,icmov, push,pop,call,callv,leave, str,cld, fmov,fop,fsgn,fmul,fdiv,fpspc,fcmov,fcmp,fxch,fistp, sselog,sseiadd,sseishft,sseimul, sse,ssemov,sseadd,ssemul,ssecmp,ssecomi,ssecvt,sseicvt,ssediv, mmx,mmxmov,mmxadd,mmxmul,mmxcmp,mmxcvt,mmxshft" (const_string "other"))

;; Main data type used by the insn (define_attr "mode" "unknown,none,QI,HI,SI,DI,SF,DF,XF,TI,V4SF,V2DF,V2SF" (const_string "unknown"))

;; The CPU unit operations uses. (define_attr "unit" "integer,i387,sse,mmx,unknown" (cond [(eq_attr "type" "fmov,fop,fsgn,fmul,fdiv,fpspc,fcmov,fcmp,fxch,fistp") (const_string "i387") (eq_attr "type" "sselog,sseiadd,sseishft,sseimul, sse,ssemov,sseadd,ssemul,ssecmp,ssecomi,ssecvt,sseicvt,ssediv") (const_string "sse") (eq_attr "type" "mmx,mmxmov,mmxadd,mmxmul,mmxcmp,mmxcvt,mmxshft") (const_string "mmx") (eq_attr "type" "other") (const_string "unknown")] (const_string "integer")))

;; The (bounding maximum) length of an instruction immediate. (define_attr "length_immediate" "" (cond [(eq_attr "type" "incdec,setcc,icmov,str,cld,lea,other,multi,idiv,leave") (const_int 0) (eq_attr "unit" "i387,sse,mmx") (const_int 0) (eq_attr "type" "alu,alu1,negnot,imovx,ishift,rotate,ishift1,rotate1, imul,icmp,push,pop") (symbol_ref "ix86_attr_length_immediate_default(insn,1)") (eq_attr "type" "imov,test") (symbol_ref "ix86_attr_length_immediate_default(insn,0)") (eq_attr "type" "call") (if_then_else (match_operand 0 "constant_call_address_operand" "") (const_int 4) (const_int 0)) (eq_attr "type" "callv") (if_then_else (match_operand 1 "constant_call_address_operand" "") (const_int 4) (const_int 0)) ;; We don't know the size before shorten_branches. Expect ;; the instruction to fit for better scheduling. (eq_attr "type" "ibr") (const_int 1) ] (symbol_ref "/* Update immediate_length and other attributes! */ abort(),1")))

;; The (bounding maximum) length of an instruction address. (define_attr "length_address" "" (cond [(eq_attr "type" "str,cld,other,multi,fxch") (const_int 0) (and (eq_attr "type" "call") (match_operand 0 "constant_call_address_operand" "")) (const_int 0) (and (eq_attr "type" "callv") (match_operand 1 "constant_call_address_operand" "")) (const_int 0) ] (symbol_ref "ix86_attr_length_address_default (insn)")))

;; Set when length prefix is used. (define_attr "prefix_data16" "" (if_then_else (ior (eq_attr "mode" "HI") (and (eq_attr "unit" "sse") (eq_attr "mode" "V2DF"))) (const_int 1) (const_int 0)))

;; Set when string REP prefix is used. (define_attr "prefix_rep" "" (if_then_else (and (eq_attr "unit" "sse") (eq_attr "mode" "SF,DF")) (const_int 1) (const_int 0)))

;; Set when 0f opcode prefix is used. (define_attr "prefix_0f" "" (if_then_else (ior (eq_attr "type" "imovx,setcc,icmov") (eq_attr "unit" "sse,mmx")) (const_int 1) (const_int 0)))

;; Set when 0f opcode prefix is used. (define_attr "prefix_rex" "" (cond [(and (eq_attr "mode" "DI") (eq_attr "type" "!push,pop,call,callv,leave,ibr")) (const_int 1) (and (eq_attr "mode" "QI") (ne (symbol_ref "x86_extended_QIreg_mentioned_p (insn)") (const_int 0))) (const_int 1) (ne (symbol_ref "x86_extended_reg_mentioned_p (insn)") (const_int 0)) (const_int 1) ] (const_int 0)))

;; Set when modrm byte is used. (define_attr "modrm" "" (cond [(eq_attr "type" "str,cld,leave") (const_int 0) (eq_attr "unit" "i387") (const_int 0) (and (eq_attr "type" "incdec") (ior (match_operand:SI 1 "register_operand" "") (match_operand:HI 1 "register_operand" ""))) (const_int 0) (and (eq_attr "type" "push") (not (match_operand 1 "memory_operand" ""))) (const_int 0) (and (eq_attr "type" "pop") (not (match_operand 0 "memory_operand" ""))) (const_int 0) (and (eq_attr "type" "imov") (and (match_operand 0 "register_operand" "") (match_operand 1 "immediate_operand" ""))) (const_int 0) (and (eq_attr "type" "call") (match_operand 0 "constant_call_address_operand" "")) (const_int 0) (and (eq_attr "type" "callv") (match_operand 1 "constant_call_address_operand" "")) (const_int 0) ] (const_int 1)))

;; The (bounding maximum) length of an instruction in bytes. ;; ??? fistp is in fact fldcw/fistp/fldcw sequence. Later we may want ;; to split it and compute proper length as for other insns. (define_attr "length" "" (cond [(eq_attr "type" "other,multi,fistp") (const_int 16) (eq_attr "type" "fcmp") (const_int 4) (eq_attr "unit" "i387") (plus (const_int 2) (plus (attr "prefix_data16") (attr "length_address")))] (plus (plus (attr "modrm") (plus (attr "prefix_0f") (plus (attr "prefix_rex") (const_int 1)))) (plus (attr "prefix_rep") (plus (attr "prefix_data16") (plus (attr "length_immediate") (attr "length_address")))))))

;; The memory' attribute is none' if no memory is referenced, load' or ;; store' if there is a simple memory reference therein, or `unknown' ;; if the instruction is complex.

(define_attr "memory" "none,load,store,both,unknown" (cond [(eq_attr "type" "other,multi,str") (const_string "unknown") (eq_attr "type" "lea,fcmov,fpspc,cld") (const_string "none") (eq_attr "type" "fistp,leave") (const_string "both") (eq_attr "type" "push") (if_then_else (match_operand 1 "memory_operand" "") (const_string "both") (const_string "store")) (eq_attr "type" "pop") (if_then_else (match_operand 0 "memory_operand" "") (const_string "both") (const_string "load")) (eq_attr "type" "setcc") (if_then_else (match_operand 0 "memory_operand" "") (const_string "store") (const_string "none")) (eq_attr "type" "icmp,test,ssecmp,ssecomi,mmxcmp,fcmp") (if_then_else (ior (match_operand 0 "memory_operand" "") (match_operand 1 "memory_operand" "")) (const_string "load") (const_string "none")) (eq_attr "type" "ibr") (if_then_else (match_operand 0 "memory_operand" "") (const_string "load") (const_string "none")) (eq_attr "type" "call") (if_then_else (match_operand 0 "constant_call_address_operand" "") (const_string "none") (const_string "load")) (eq_attr "type" "callv") (if_then_else (match_operand 1 "constant_call_address_operand" "") (const_string "none") (const_string "load")) (and (eq_attr "type" "alu1,negnot,ishift1") (match_operand 1 "memory_operand" "")) (const_string "both") (and (match_operand 0 "memory_operand" "") (match_operand 1 "memory_operand" "")) (const_string "both") (match_operand 0 "memory_operand" "") (const_string "store") (match_operand 1 "memory_operand" "") (const_string "load") (and (eq_attr "type" "!alu1,negnot,ishift1, imov,imovx,icmp,test, fmov,fcmp,fsgn, sse,ssemov,ssecmp,ssecomi,ssecvt,sseicvt, mmx,mmxmov,mmxcmp,mmxcvt") (match_operand 2 "memory_operand" "")) (const_string "load") (and (eq_attr "type" "icmov") (match_operand 3 "memory_operand" "")) (const_string "load") ] (const_string "none")))

;; Indicates if an instruction has both an immediate and a displacement.

(define_attr "imm_disp" "false,true,unknown" (cond [(eq_attr "type" "other,multi") (const_string "unknown") (and (eq_attr "type" "icmp,test,imov,alu1,ishift1,rotate1") (and (match_operand 0 "memory_displacement_operand" "") (match_operand 1 "immediate_operand" ""))) (const_string "true") (and (eq_attr "type" "alu,ishift,rotate,imul,idiv") (and (match_operand 0 "memory_displacement_operand" "") (match_operand 2 "immediate_operand" ""))) (const_string "true") ] (const_string "false")))

;; Indicates if an FP operation has an integer source.

(define_attr "fp_int_src" "false,true" (const_string "false"))

;; Describe a user's asm statement. (define_asm_attributes [(set_attr "length" "128") (set_attr "type" "multi")]) (include "pentium.md") (include "ppro.md") (include "k6.md") (include "athlon.md") ;; Compare instructions.

;; All compare insns have expanders that save the operands away without ;; actually generating RTL. The bCOND or sCOND (emitted immediately ;; after the cmp) will actually emit the cmpM.

(define_expand "cmpdi" [(set (reg:CC 17) (compare:CC (match_operand:DI 0 "nonimmediate_operand" "") (match_operand:DI 1 "x86_64_general_operand" "")))] "" { if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM) operands[0] = force_reg (DImode, operands[0]); ix86_compare_op0 = operands[0]; ix86_compare_op1 = operands[1]; DONE; })

(define_expand "cmpsi" [(set (reg:CC 17) (compare:CC (match_operand:SI 0 "cmpsi_operand" "") (match_operand:SI 1 "general_operand" "")))] "" { if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM) operands[0] = force_reg (SImode, operands[0]); ix86_compare_op0 = operands[0]; ix86_compare_op1 = operands[1]; DONE; })

(define_expand "cmphi" [(set (reg:CC 17) (compare:CC (match_operand:HI 0 "nonimmediate_operand" "") (match_operand:HI 1 "general_operand" "")))] "" { if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM) operands[0] = force_reg (HImode, operands[0]); ix86_compare_op0 = operands[0]; ix86_compare_op1 = operands[1]; DONE; })

(define_expand "cmpqi" [(set (reg:CC 17) (compare:CC (match_operand:QI 0 "nonimmediate_operand" "") (match_operand:QI 1 "general_operand" "")))] "TARGET_QIMODE_MATH" { if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM) operands[0] = force_reg (QImode, operands[0]); ix86_compare_op0 = operands[0]; ix86_compare_op1 = operands[1]; DONE; })

(define_insn "cmpdi_ccno_1_rex64" [(set (reg 17) (compare (match_operand:DI 0 "nonimmediate_operand" "r,?mr") (match_operand:DI 1 "const0_operand" "n,n")))] "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)" "@ test{q}\t{%0, %0|%0, %0} cmp{q}\t{%1, %0|%0, %1}" [(set_attr "type" "test,icmp") (set_attr "length_immediate" "0,1") (set_attr "mode" "DI")])

(define_insn "*cmpdi_minus_1_rex64" [(set (reg 17) (compare (minus:DI (match_operand:DI 0 "nonimmediate_operand" "rm,r") (match_operand:DI 1 "x86_64_general_operand" "re,mr")) (const_int 0)))] "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)" "cmp{q}\t{%1, %0|%0, %1}" [(set_attr "type" "icmp") (set_attr "mode" "DI")])

(define_expand "cmpdi_1_rex64" [(set (reg:CC 17) (compare:CC (match_operand:DI 0 "nonimmediate_operand" "") (match_operand:DI 1 "general_operand" "")))] "TARGET_64BIT" "")

(define_insn "cmpdi_1_insn_rex64" [(set (reg 17) (compare (match_operand:DI 0 "nonimmediate_operand" "mr,r") (match_operand:DI 1 "x86_64_general_operand" "re,mr")))] "TARGET_64BIT && ix86_match_ccmode (insn, CCmode)" "cmp{q}\t{%1, %0|%0, %1}" [(set_attr "type" "icmp") (set_attr "mode" "DI")])

(define_insn "*cmpsi_ccno_1" [(set (reg 17) (compare (match_operand:SI 0 "nonimmediate_operand" "r,?mr") (match_operand:SI 1 "const0_operand" "n,n")))] "ix86_match_ccmode (insn, CCNOmode)" "@ test{l}\t{%0, %0|%0, %0} cmp{l}\t{%1, %0|%0, %1}" [(set_attr "type" "test,icmp") (set_attr "length_immediate" "0,1") (set_attr "mode" "SI")])

(define_insn "*cmpsi_minus_1" [(set (reg 17) (compare (minus:SI (match_operand:SI 0 "nonimmediate_operand" "rm,r") (match_operand:SI 1 "general_operand" "ri,mr")) (const_int 0)))] "ix86_match_ccmode (insn, CCGOCmode)" "cmp{l}\t{%1, %0|%0, %1}" [(set_attr "type" "icmp") (set_attr "mode" "SI")])

(define_expand "cmpsi_1" [(set (reg:CC 17) (compare:CC (match_operand:SI 0 "nonimmediate_operand" "rm,r") (match_operand:SI 1 "general_operand" "ri,mr")))] "" "")

(define_insn "*cmpsi_1_insn" [(set (reg 17) (compare (match_operand:SI 0 "nonimmediate_operand" "rm,r") (match_operand:SI 1 "general_operand" "ri,mr")))] "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM) && ix86_match_ccmode (insn, CCmode)" "cmp{l}\t{%1, %0|%0, %1}" [(set_attr "type" "icmp") (set_attr "mode" "SI")])

(define_insn "*cmphi_ccno_1" [(set (reg 17) (compare (match_operand:HI 0 "nonimmediate_operand" "r,?mr") (match_operand:HI 1 "const0_operand" "n,n")))] "ix86_match_ccmode (insn, CCNOmode)" "@ test{w}\t{%0, %0|%0, %0} cmp{w}\t{%1, %0|%0, %1}" [(set_attr "type" "test,icmp") (set_attr "length_immediate" "0,1") (set_attr "mode" "HI")])

(define_insn "*cmphi_minus_1" [(set (reg 17) (compare (minus:HI (match_operand:HI 0 "nonimmediate_operand" "rm,r") (match_operand:HI 1 "general_operand" "ri,mr")) (const_int 0)))] "ix86_match_ccmode (insn, CCGOCmode)" "cmp{w}\t{%1, %0|%0, %1}" [(set_attr "type" "icmp") (set_attr "mode" "HI")])

(define_insn "*cmphi_1" [(set (reg 17) (compare (match_operand:HI 0 "nonimmediate_operand" "rm,r") (match_operand:HI 1 "general_operand" "ri,mr")))] "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM) && ix86_match_ccmode (insn, CCmode)" "cmp{w}\t{%1, %0|%0, %1}" [(set_attr "type" "icmp") (set_attr "mode" "HI")])

(define_insn "*cmpqi_ccno_1" [(set (reg 17) (compare (match_operand:QI 0 "nonimmediate_operand" "q,?mq") (match_operand:QI 1 "const0_operand" "n,n")))] "ix86_match_ccmode (insn, CCNOmode)" "@ test{b}\t{%0, %0|%0, %0} cmp{b}\t{$0, %0|%0, 0}" [(set_attr "type" "test,icmp") (set_attr "length_immediate" "0,1") (set_attr "mode" "QI")])

(define_insn "*cmpqi_1" [(set (reg 17) (compare (match_operand:QI 0 "nonimmediate_operand" "qm,q") (match_operand:QI 1 "general_operand" "qi,mq")))] "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM) && ix86_match_ccmode (insn, CCmode)" "cmp{b}\t{%1, %0|%0, %1}" [(set_attr "type" "icmp") (set_attr "mode" "QI")])

(define_insn "*cmpqi_minus_1" [(set (reg 17) (compare (minus:QI (match_operand:QI 0 "nonimmediate_operand" "qm,q") (match_operand:QI 1 "general_operand" "qi,mq")) (const_int 0)))] "ix86_match_ccmode (insn, CCGOCmode)" "cmp{b}\t{%1, %0|%0, %1}" [(set_attr "type" "icmp") (set_attr "mode" "QI")])

(define_insn "*cmpqi_ext_1" [(set (reg 17) (compare (match_operand:QI 0 "general_operand" "Qm") (subreg:QI (zero_extract:SI (match_operand 1 "ext_register_operand" "Q") (const_int 8) (const_int 8)) 0)))] "!TARGET_64BIT && ix86_match_ccmode (insn, CCmode)" "cmp{b}\t{%h1, %0|%0, %h1}" [(set_attr "type" "icmp") (set_attr "mode" "QI")])

(define_insn "*cmpqi_ext_1_rex64" [(set (reg 17) (compare (match_operand:QI 0 "register_operand" "Q") (subreg:QI (zero_extract:SI (match_operand 1 "ext_register_operand" "Q") (const_int 8) (const_int 8)) 0)))] "TARGET_64BIT && ix86_match_ccmode (insn, CCmode)" "cmp{b}\t{%h1, %0|%0, %h1}" [(set_attr "type" "icmp") (set_attr "mode" "QI")])

(define_insn "*cmpqi_ext_2" [(set (reg 17) (compare (subreg:QI (zero_extract:SI (match_operand 0 "ext_register_operand" "Q") (const_int 8) (const_int 8)) 0) (match_operand:QI 1 "const0_operand" "n")))] "ix86_match_ccmode (insn, CCNOmode)" "test{b}\t%h0, %h0" [(set_attr "type" "test") (set_attr "length_immediate" "0") (set_attr "mode" "QI")])

(define_expand "cmpqi_ext_3" [(set (reg:CC 17) (compare:CC (subreg:QI (zero_extract:SI (match_operand 0 "ext_register_operand" "") (const_int 8) (const_int 8)) 0) (match_operand:QI 1 "general_operand" "")))] "" "")

(define_insn "cmpqi_ext_3_insn" [(set (reg 17) (compare (subreg:QI (zero_extract:SI (match_operand 0 "ext_register_operand" "Q") (const_int 8) (const_int 8)) 0) (match_operand:QI 1 "general_operand" "Qmn")))] "!TARGET_64BIT && ix86_match_ccmode (insn, CCmode)" "cmp{b}\t{%1, %h0|%h0, %1}" [(set_attr "type" "icmp") (set_attr "mode" "QI")])

(define_insn "cmpqi_ext_3_insn_rex64" [(set (reg 17) (compare (subreg:QI (zero_extract:SI (match_operand 0 "ext_register_operand" "Q") (const_int 8) (const_int 8)) 0) (match_operand:QI 1 "nonmemory_operand" "Qn")))] "TARGET_64BIT && ix86_match_ccmode (insn, CCmode)" "cmp{b}\t{%1, %h0|%h0, %1}" [(set_attr "type" "icmp") (set_attr "mode" "QI")])

(define_insn "*cmpqi_ext_4" [(set (reg 17) (compare (subreg:QI (zero_extract:SI (match_operand 0 "ext_register_operand" "Q") (const_int 8) (const_int 8)) 0) (subreg:QI (zero_extract:SI (match_operand 1 "ext_register_operand" "Q") (const_int 8) (const_int 8)) 0)))] "ix86_match_ccmode (insn, CCmode)" "cmp{b}\t{%h1, %h0|%h0, %h1}" [(set_attr "type" "icmp") (set_attr "mode" "QI")])

;; These implement float point compares. ;; %%% See if we can get away with VOIDmode operands on the actual insns, ;; which would allow mix and match FP modes on the compares. Which is what ;; the old patterns did, but with many more of them.

(define_expand "cmpxf" [(set (reg:CC 17) (compare:CC (match_operand:XF 0 "cmp_fp_expander_operand" "") (match_operand:XF 1 "cmp_fp_expander_operand" "")))] "TARGET_80387" { ix86_compare_op0 = operands[0]; ix86_compare_op1 = operands[1]; DONE; })

(define_expand "cmpdf" [(set (reg:CC 17) (compare:CC (match_operand:DF 0 "cmp_fp_expander_operand" "") (match_operand:DF 1 "cmp_fp_expander_operand" "")))] "TARGET_80387 || TARGET_SSE2" { ix86_compare_op0 = operands[0]; ix86_compare_op1 = operands[1]; DONE; })

(define_expand "cmpsf" [(set (reg:CC 17) (compare:CC (match_operand:SF 0 "cmp_fp_expander_operand" "") (match_operand:SF 1 "cmp_fp_expander_operand" "")))] "TARGET_80387 || TARGET_SSE" { ix86_compare_op0 = operands[0]; ix86_compare_op1 = operands[1]; DONE; })

;; FP compares, step 1: ;; Set the FP condition codes. ;; ;; CCFPmode compare with exceptions ;; CCFPUmode compare with no exceptions

;; %%% It is an unfortunate fact that ftst has no non-popping variant, ;; and that fp moves clobber the condition codes, and that there is ;; currently no way to describe this fact to reg-stack. So there are ;; no splitters yet for this.

;; %%% YIKES! This scheme does not retain a strong connection between ;; the real compare and the ultimate cc0 user, so CC_REVERSE does not ;; work! Only allow tos/mem with tos in op 0. ;; ;; Hmm, of course, this is what the actual hardware does. Perhaps ;; things aren't as bad as they sound...

(define_insn "*cmpfp_0" [(set (match_operand:HI 0 "register_operand" "=a") (unspec:HI [(compare:CCFP (match_operand 1 "register_operand" "f") (match_operand 2 "const0_operand" "X"))] UNSPEC_FNSTSW))] "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1])) && GET_MODE (operands[1]) == GET_MODE (operands[2])" { if (find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) return "ftst;fnstsw\t%0;fstp\t%y0"; else return "ftst;fnstsw\t%0"; } [(set_attr "type" "multi") (set (attr "mode") (cond [(match_operand:SF 1 "" "") (const_string "SF") (match_operand:DF 1 "" "") (const_string "DF") ] (const_string "XF")))])

;; We may not use "#" to split and emit these, since the REG_DEAD notes ;; used to manage the reg stack popping would not be preserved.

(define_insn "cmpfp_2_sf" [(set (reg:CCFP 18) (compare:CCFP (match_operand:SF 0 "register_operand" "f") (match_operand:SF 1 "nonimmediate_operand" "fm")))] "TARGET_80387" " return output_fp_compare (insn, operands, 0, 0);" [(set_attr "type" "fcmp") (set_attr "mode" "SF")])

(define_insn "cmpfp_2_sf_1" [(set (match_operand:HI 0 "register_operand" "=a") (unspec:HI [(compare:CCFP (match_operand:SF 1 "register_operand" "f") (match_operand:SF 2 "nonimmediate_operand" "fm"))] UNSPEC_FNSTSW))] "TARGET_80387" " return output_fp_compare (insn, operands, 2, 0);" [(set_attr "type" "fcmp") (set_attr "mode" "SF")])

(define_insn "cmpfp_2_df" [(set (reg:CCFP 18) (compare:CCFP (match_operand:DF 0 "register_operand" "f") (match_operand:DF 1 "nonimmediate_operand" "fm")))] "TARGET_80387" " return output_fp_compare (insn, operands, 0, 0);" [(set_attr "type" "fcmp") (set_attr "mode" "DF")])

(define_insn "cmpfp_2_df_1" [(set (match_operand:HI 0 "register_operand" "=a") (unspec:HI [(compare:CCFP (match_operand:DF 1 "register_operand" "f") (match_operand:DF 2 "nonimmediate_operand" "fm"))] UNSPEC_FNSTSW))] "TARGET_80387" " return output_fp_compare (insn, operands, 2, 0);" [(set_attr "type" "multi") (set_attr "mode" "DF")])

(define_insn "cmpfp_2_xf" [(set (reg:CCFP 18) (compare:CCFP (match_operand:XF 0 "register_operand" "f") (match_operand:XF 1 "register_operand" "f")))] "TARGET_80387" " return output_fp_compare (insn, operands, 0, 0);" [(set_attr "type" "fcmp") (set_attr "mode" "XF")])

(define_insn "cmpfp_2_xf_1" [(set (match_operand:HI 0 "register_operand" "=a") (unspec:HI [(compare:CCFP (match_operand:XF 1 "register_operand" "f") (match_operand:XF 2 "register_operand" "f"))] UNSPEC_FNSTSW))] "TARGET_80387" " return output_fp_compare (insn, operands, 2, 0);" [(set_attr "type" "multi") (set_attr "mode" "XF")])

(define_insn "cmpfp_2u" [(set (reg:CCFPU 18) (compare:CCFPU (match_operand 0 "register_operand" "f") (match_operand 1 "register_operand" "f")))] "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[0])) && GET_MODE (operands[0]) == GET_MODE (operands[1])" " return output_fp_compare (insn, operands, 0, 1);" [(set_attr "type" "fcmp") (set (attr "mode") (cond [(match_operand:SF 1 "" "") (const_string "SF") (match_operand:DF 1 "" "") (const_string "DF") ] (const_string "XF")))])

(define_insn "cmpfp_2u_1" [(set (match_operand:HI 0 "register_operand" "=a") (unspec:HI [(compare:CCFPU (match_operand 1 "register_operand" "f") (match_operand 2 "register_operand" "f"))] UNSPEC_FNSTSW))] "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1])) && GET_MODE (operands[1]) == GET_MODE (operands[2])" " return output_fp_compare (insn, operands, 2, 1);" [(set_attr "type" "multi") (set (attr "mode") (cond [(match_operand:SF 1 "" "") (const_string "SF") (match_operand:DF 1 "" "") (const_string "DF") ] (const_string "XF")))])

;; Patterns to match the SImode-in-memory ficom instructions. ;; ;; %%% Play games with accepting gp registers, as otherwise we have to ;; force them to memory during rtl generation, which is no good. We ;; can get rid of this once we teach reload to do memory input reloads ;; via pushes.

(define_insn "*ficom_1" [(set (reg:CCFP 18) (compare:CCFP (match_operand 0 "register_operand" "f,f") (float (match_operand:SI 1 "nonimmediate_operand" "m,?r"))))] "0 && TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[0])) && GET_MODE (XEXP (SET_SRC (PATTERN (insn)), 1)) == GET_MODE (operands[0])" "#")

;; Split the not-really-implemented gp register case into a ;; push-op-pop sequence. ;; ;; %%% This is most efficient, but am I gonna get in trouble ;; for separating cc0_setter and cc0_user?

(define_split [(set (reg:CCFP 18) (compare:CCFP (match_operand:SF 0 "register_operand" "") (float (match_operand:SI 1 "register_operand" ""))))] "0 && TARGET_80387 && reload_completed" [(set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 1)) (set (reg:CCFP 18) (compare:CCFP (match_dup 0) (match_dup 2))) (parallel [(set (match_dup 1) (mem:SI (reg:SI 7))) (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])] "operands[2] = gen_rtx_MEM (Pmode, stack_pointer_rtx); operands[2] = gen_rtx_FLOAT (GET_MODE (operands[0]), operands[2]);")

;; FP compares, step 2 ;; Move the fpsw to ax.

(define_insn "*x86_fnstsw_1" [(set (match_operand:HI 0 "register_operand" "=a") (unspec:HI [(reg 18)] UNSPEC_FNSTSW))] "TARGET_80387" "fnstsw\t%0" [(set_attr "length" "2") (set_attr "mode" "SI") (set_attr "unit" "i387") (set_attr "ppro_uops" "few")])

;; FP compares, step 3 ;; Get ax into flags, general case.

(define_insn "x86_sahf_1" [(set (reg:CC 17) (unspec:CC [(match_operand:HI 0 "register_operand" "a")] UNSPEC_SAHF))] "!TARGET_64BIT" "sahf" [(set_attr "length" "1") (set_attr "athlon_decode" "vector") (set_attr "mode" "SI") (set_attr "ppro_uops" "one")])

;; Pentium Pro can do steps 1 through 3 in one go.

(define_insn "cmpfp_i" [(set (reg:CCFP 17) (compare:CCFP (match_operand 0 "register_operand" "f") (match_operand 1 "register_operand" "f")))] "TARGET_80387 && TARGET_CMOVE && !SSE_FLOAT_MODE_P (GET_MODE (operands[0])) && FLOAT_MODE_P (GET_MODE (operands[0])) && GET_MODE (operands[0]) == GET_MODE (operands[0])" " return output_fp_compare (insn, operands, 1, 0);" [(set_attr "type" "fcmp") (set (attr "mode") (cond [(match_operand:SF 1 "" "") (const_string "SF") (match_operand:DF 1 "" "") (const_string "DF") ] (const_string "XF"))) (set_attr "athlon_decode" "vector")])

(define_insn "cmpfp_i_sse" [(set (reg:CCFP 17) (compare:CCFP (match_operand 0 "register_operand" "f#x,x#f") (match_operand 1 "nonimmediate_operand" "f#x,xm#f")))] "TARGET_80387 && SSE_FLOAT_MODE_P (GET_MODE (operands[0])) && GET_MODE (operands[0]) == GET_MODE (operands[0])" " return output_fp_compare (insn, operands, 1, 0);" [(set_attr "type" "fcmp,ssecomi") (set (attr "mode") (if_then_else (match_operand:SF 1 "" "") (const_string "SF") (const_string "DF"))) (set_attr "athlon_decode" "vector")])

(define_insn "cmpfp_i_sse_only" [(set (reg:CCFP 17) (compare:CCFP (match_operand 0 "register_operand" "x") (match_operand 1 "nonimmediate_operand" "xm")))] "SSE_FLOAT_MODE_P (GET_MODE (operands[0])) && GET_MODE (operands[0]) == GET_MODE (operands[0])" " return output_fp_compare (insn, operands, 1, 0);" [(set_attr "type" "ssecomi") (set (attr "mode") (if_then_else (match_operand:SF 1 "" "") (const_string "SF") (const_string "DF"))) (set_attr "athlon_decode" "vector")])

(define_insn "cmpfp_iu" [(set (reg:CCFPU 17) (compare:CCFPU (match_operand 0 "register_operand" "f") (match_operand 1 "register_operand" "f")))] "TARGET_80387 && TARGET_CMOVE && !SSE_FLOAT_MODE_P (GET_MODE (operands[0])) && FLOAT_MODE_P (GET_MODE (operands[0])) && GET_MODE (operands[0]) == GET_MODE (operands[1])" " return output_fp_compare (insn, operands, 1, 1);" [(set_attr "type" "fcmp") (set (attr "mode") (cond [(match_operand:SF 1 "" "") (const_string "SF") (match_operand:DF 1 "" "") (const_string "DF") ] (const_string "XF"))) (set_attr "athlon_decode" "vector")])

(define_insn "cmpfp_iu_sse" [(set (reg:CCFPU 17) (compare:CCFPU (match_operand 0 "register_operand" "f#x,x#f") (match_operand 1 "nonimmediate_operand" "f#x,xm#f")))] "TARGET_80387 && SSE_FLOAT_MODE_P (GET_MODE (operands[0])) && GET_MODE (operands[0]) == GET_MODE (operands[1])" " return output_fp_compare (insn, operands, 1, 1);" [(set_attr "type" "fcmp,ssecomi") (set (attr "mode") (if_then_else (match_operand:SF 1 "" "") (const_string "SF") (const_string "DF"))) (set_attr "athlon_decode" "vector")])

(define_insn "cmpfp_iu_sse_only" [(set (reg:CCFPU 17) (compare:CCFPU (match_operand 0 "register_operand" "x") (match_operand 1 "nonimmediate_operand" "xm")))] "SSE_FLOAT_MODE_P (GET_MODE (operands[0])) && GET_MODE (operands[0]) == GET_MODE (operands[1])" " return output_fp_compare (insn, operands, 1, 1);" [(set_attr "type" "ssecomi") (set (attr "mode") (if_then_else (match_operand:SF 1 "" "") (const_string "SF") (const_string "DF"))) (set_attr "athlon_decode" "vector")]) ;; Move instructions.

;; General case of fullword move.

(define_expand "movsi" [(set (match_operand:SI 0 "nonimmediate_operand" "") (match_operand:SI 1 "general_operand" ""))] "" "ix86_expand_move (SImode, operands); DONE;")

;; Push/pop instructions. They are separate since autoinc/dec is not a ;; general_operand. ;; ;; %%% We don't use a post-inc memory reference because x86 is not a ;; general AUTO_INC_DEC host, which impacts how it is treated in flow. ;; Changing this impacts compiler performance on other non-AUTO_INC_DEC ;; targets without our curiosities, and it is just as easy to represent ;; this differently.

(define_insn "pushsi2" [(set (match_operand:SI 0 "push_operand" "=<") (match_operand:SI 1 "general_no_elim_operand" "rim"))] "!TARGET_64BIT" "push{l}\t%1" [(set_attr "type" "push") (set_attr "mode" "SI")])

;; For 64BIT abi we always round up to 8 bytes. (define_insn "*pushsi2_rex64" [(set (match_operand:SI 0 "push_operand" "=X") (match_operand:SI 1 "nonmemory_no_elim_operand" "ri"))] "TARGET_64BIT" "push{q}\t%q1" [(set_attr "type" "push") (set_attr "mode" "SI")])

(define_insn "pushsi2_prologue" [(set (match_operand:SI 0 "push_operand" "=<") (match_operand:SI 1 "general_no_elim_operand" "rim")) (clobber (mem:BLK (scratch)))] "!TARGET_64BIT" "push{l}\t%1" [(set_attr "type" "push") (set_attr "mode" "SI")])

(define_insn "popsi1_epilogue" [(set (match_operand:SI 0 "nonimmediate_operand" "=rm") (mem:SI (reg:SI 7))) (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4))) (clobber (mem:BLK (scratch)))] "!TARGET_64BIT" "pop{l}\t%0" [(set_attr "type" "pop") (set_attr "mode" "SI")])

(define_insn "popsi1" [(set (match_operand:SI 0 "nonimmediate_operand" "=r*m") (mem:SI (reg:SI 7))) (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))] "!TARGET_64BIT" "pop{l}\t%0" [(set_attr "type" "pop") (set_attr "mode" "SI")])

(define_insn "*movsi_xor" [(set (match_operand:SI 0 "register_operand" "=r") (match_operand:SI 1 "const0_operand" "i")) (clobber (reg:CC 17))] "reload_completed && (!TARGET_USE_MOV0 || optimize_size)" "xor{l}\t{%0, %0|%0, %0}" [(set_attr "type" "alu1") (set_attr "mode" "SI") (set_attr "length_immediate" "0")])

(define_insn "*movsi_or" [(set (match_operand:SI 0 "register_operand" "=r") (match_operand:SI 1 "immediate_operand" "i")) (clobber (reg:CC 17))] "reload_completed && operands[1] == constm1_rtx && (TARGET_PENTIUM || optimize_size)" { operands[1] = constm1_rtx; return "or{l}\t{%1, %0|%0, %1}"; } [(set_attr "type" "alu1") (set_attr "mode" "SI") (set_attr "length_immediate" "1")])

(define_insn "*movsi_1" [(set (match_operand:SI 0 "nonimmediate_operand" "=r,m,!*y,!rm,!*y,!*Y,!rm,!*Y") (match_operand:SI 1 "general_operand" "rinm,rin,*y,*y,rm,*Y,*Y,rm"))] "(TARGET_INTER_UNIT_MOVES || optimize_size) && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)" { switch (get_attr_type (insn)) { case TYPE_SSEMOV: if (get_attr_mode (insn) == MODE_TI) return "movdqa\t{%1, %0|%0, %1}"; return "movd\t{%1, %0|%0, %1}";

case TYPE_MMXMOV:
  if (get_attr_mode (insn) == MODE_DI)
return "movq\t{%1, %0|%0, %1}";
  return "movd\t{%1, %0|%0, %1}";

case TYPE_LEA:
  return "lea{l}\t{%1, %0|%0, %1}";

default:
  if (flag_pic && !LEGITIMATE_PIC_OPERAND_P (operands[1]))
abort();
  return "mov{l}\t{%1, %0|%0, %1}";
}

} [(set (attr "type") (cond [(eq_attr "alternative" "2,3,4") (const_string "mmxmov") (eq_attr "alternative" "5,6,7") (const_string "ssemov") (and (ne (symbol_ref "flag_pic") (const_int 0)) (match_operand:SI 1 "symbolic_operand" "")) (const_string "lea") ] (const_string "imov"))) (set_attr "mode" "SI,SI,DI,SI,SI,TI,SI,SI")])

(define_insn "*movsi_1_nointernunit" [(set (match_operand:SI 0 "nonimmediate_operand" "=r,m,!*y,!m,!*y,!*Y,!m,!*Y") (match_operand:SI 1 "general_operand" "rinm,rin,*y,*y,m,*Y,*Y,m"))] "(!TARGET_INTER_UNIT_MOVES && !optimize_size) && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)" { switch (get_attr_type (insn)) { case TYPE_SSEMOV: if (get_attr_mode (insn) == MODE_TI) return "movdqa\t{%1, %0|%0, %1}"; return "movd\t{%1, %0|%0, %1}";

case TYPE_MMXMOV:
  if (get_attr_mode (insn) == MODE_DI)
return "movq\t{%1, %0|%0, %1}";
  return "movd\t{%1, %0|%0, %1}";

case TYPE_LEA:
  return "lea{l}\t{%1, %0|%0, %1}";

default:
  if (flag_pic && !LEGITIMATE_PIC_OPERAND_P (operands[1]))
abort();
  return "mov{l}\t{%1, %0|%0, %1}";
}

;; Stores and loads of ax to arbitrary constant address. ;; We fake an second form of instruction to force reload to load address ;; into register when rax is not available (define_insn "movabssi_1_rex64" [(set (mem:SI (match_operand:DI 0 "x86_64_movabs_operand" "i,r")) (match_operand:SI 1 "nonmemory_operand" "a,er"))] "TARGET_64BIT && ix86_check_movabs (insn, 0)" "@ movabs{l}\t{%1, %P0|%P0, %1} mov{l}\t{%1, %a0|%a0, %1}" [(set_attr "type" "imov") (set_attr "modrm" "0,") (set_attr "length_address" "8,0") (set_attr "length_immediate" "0,*") (set_attr "memory" "store") (set_attr "mode" "SI")])

(define_insn "movabssi_2_rex64" [(set (match_operand:SI 0 "register_operand" "=a,r") (mem:SI (match_operand:DI 1 "x86_64_movabs_operand" "i,r")))] "TARGET_64BIT && ix86_check_movabs (insn, 1)" "@ movabs{l}\t{%P1, %0|%0, %P1} mov{l}\t{%a1, %0|%0, %a1}" [(set_attr "type" "imov") (set_attr "modrm" "0,") (set_attr "length_address" "8,0") (set_attr "length_immediate" "0") (set_attr "memory" "load") (set_attr "mode" "SI")])

(define_insn "*swapsi" [(set (match_operand:SI 0 "register_operand" "+r") (match_operand:SI 1 "register_operand" "+r")) (set (match_dup 1) (match_dup 0))] "" "xchg{l}\t%1, %0" [(set_attr "type" "imov") (set_attr "mode" "SI") (set_attr "pent_pair" "np") (set_attr "athlon_decode" "vector") (set_attr "ppro_uops" "few")])

(define_expand "movhi" [(set (match_operand:HI 0 "nonimmediate_operand" "") (match_operand:HI 1 "general_operand" ""))] "" "ix86_expand_move (HImode, operands); DONE;")

(define_insn "pushhi2" [(set (match_operand:HI 0 "push_operand" "=<,<") (match_operand:HI 1 "general_no_elim_operand" "n,rm"))] "!TARGET_64BIT" "@ push{w}\t{|WORD PTR }%1 push{w}\t%1" [(set_attr "type" "push") (set_attr "mode" "HI")])

;; For 64BIT abi we always round up to 8 bytes. (define_insn "*pushhi2_rex64" [(set (match_operand:HI 0 "push_operand" "=X") (match_operand:HI 1 "nonmemory_no_elim_operand" "ri"))] "TARGET_64BIT" "push{q}\t%q1" [(set_attr "type" "push") (set_attr "mode" "QI")])

(define_insn "movhi_1" [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,r,m") (match_operand:HI 1 "general_operand" "r,rn,rm,rn"))] "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM" { switch (get_attr_type (insn)) { case TYPE_IMOVX: / movzwl is faster than movw on p2 due to partial word stalls, though not as fast as an aligned movl. */ return "movz{wl|x}\t{%1, %k0|%k0, %1}"; default: if (get_attr_mode (insn) == MODE_SI) return "mov{l}\t{%k1, %k0|%k0, %k1}"; else return "mov{w}\t{%1, %0|%0, %1}"; } } [(set (attr "type") (cond [(and (eq_attr "alternative" "0") (ior (eq (symbol_ref "TARGET_PARTIAL_REG_STALL") (const_int 0)) (eq (symbol_ref "TARGET_HIMODE_MATH") (const_int 0)))) (const_string "imov") (and (eq_attr "alternative" "1,2") (match_operand:HI 1 "aligned_operand" "")) (const_string "imov") (and (ne (symbol_ref "TARGET_MOVX") (const_int 0)) (eq_attr "alternative" "0,2")) (const_string "imovx") ] (const_string "imov"))) (set (attr "mode") (cond [(eq_attr "type" "imovx") (const_string "SI") (and (eq_attr "alternative" "1,2") (match_operand:HI 1 "aligned_operand" "")) (const_string "SI") (and (eq_attr "alternative" "0") (ior (eq (symbol_ref "TARGET_PARTIAL_REG_STALL") (const_int 0)) (eq (symbol_ref "TARGET_HIMODE_MATH") (const_int 0)))) (const_string "SI") ] (const_string "HI")))])

;; Stores and loads of ax to arbitrary constant address. ;; We fake an second form of instruction to force reload to load address ;; into register when rax is not available (define_insn "movabshi_1_rex64" [(set (mem:HI (match_operand:DI 0 "x86_64_movabs_operand" "i,r")) (match_operand:HI 1 "nonmemory_operand" "a,er"))] "TARGET_64BIT && ix86_check_movabs (insn, 0)" "@ movabs{w}\t{%1, %P0|%P0, %1} mov{w}\t{%1, %a0|%a0, %1}" [(set_attr "type" "imov") (set_attr "modrm" "0,") (set_attr "length_address" "8,0") (set_attr "length_immediate" "0,*") (set_attr "memory" "store") (set_attr "mode" "HI")])

(define_insn "movabshi_2_rex64" [(set (match_operand:HI 0 "register_operand" "=a,r") (mem:HI (match_operand:DI 1 "x86_64_movabs_operand" "i,r")))] "TARGET_64BIT && ix86_check_movabs (insn, 1)" "@ movabs{w}\t{%P1, %0|%0, %P1} mov{w}\t{%a1, %0|%0, %a1}" [(set_attr "type" "imov") (set_attr "modrm" "0,") (set_attr "length_address" "8,0") (set_attr "length_immediate" "0") (set_attr "memory" "load") (set_attr "mode" "HI")])

(define_insn "*swaphi_1" [(set (match_operand:HI 0 "register_operand" "+r") (match_operand:HI 1 "register_operand" "+r")) (set (match_dup 1) (match_dup 0))] "!TARGET_PARTIAL_REG_STALL || optimize_size" "xchg{l}\t%k1, %k0" [(set_attr "type" "imov") (set_attr "mode" "SI") (set_attr "pent_pair" "np") (set_attr "athlon_decode" "vector") (set_attr "ppro_uops" "few")])

(define_insn "*swaphi_2" [(set (match_operand:HI 0 "register_operand" "+r") (match_operand:HI 1 "register_operand" "+r")) (set (match_dup 1) (match_dup 0))] "TARGET_PARTIAL_REG_STALL" "xchg{w}\t%1, %0" [(set_attr "type" "imov") (set_attr "mode" "HI") (set_attr "pent_pair" "np") (set_attr "athlon_decode" "vector") (set_attr "ppro_uops" "few")])

(define_expand "movstricthi" [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "")) (match_operand:HI 1 "general_operand" ""))] "! TARGET_PARTIAL_REG_STALL || optimize_size" { /* Don't generate memory->memory moves, go through a register */ if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM) operands[1] = force_reg (HImode, operands[1]); })

(define_insn "*movstricthi_1" [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+rm,r")) (match_operand:HI 1 "general_operand" "rn,m"))] "(! TARGET_PARTIAL_REG_STALL || optimize_size) && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)" "mov{w}\t{%1, %0|%0, %1}" [(set_attr "type" "imov") (set_attr "mode" "HI")])

(define_insn "*movstricthi_xor" [(set (strict_low_part (match_operand:HI 0 "register_operand" "+r")) (match_operand:HI 1 "const0_operand" "i")) (clobber (reg:CC 17))] "reload_completed && ((!TARGET_USE_MOV0 && !TARGET_PARTIAL_REG_STALL) || optimize_size)" "xor{w}\t{%0, %0|%0, %0}" [(set_attr "type" "alu1") (set_attr "mode" "HI") (set_attr "length_immediate" "0")])

(define_expand "movqi" [(set (match_operand:QI 0 "nonimmediate_operand" "") (match_operand:QI 1 "general_operand" ""))] "" "ix86_expand_move (QImode, operands); DONE;")

;; emit_push_insn when it calls move_by_pieces requires an insn to ;; "push a byte". But actually we use pushw, which has the effect ;; of rounding the amount pushed up to a halfword.

(define_insn "*pushqi2" [(set (match_operand:QI 0 "push_operand" "=X,X") (match_operand:QI 1 "nonmemory_no_elim_operand" "n,r"))] "!TARGET_64BIT" "@ push{w}\t{|word ptr }%1 push{w}\t%w1" [(set_attr "type" "push") (set_attr "mode" "HI")])

;; For 64BIT abi we always round up to 8 bytes. (define_insn "*pushqi2_rex64" [(set (match_operand:QI 0 "push_operand" "=X") (match_operand:QI 1 "nonmemory_no_elim_operand" "qi"))] "TARGET_64BIT" "push{q}\t%q1" [(set_attr "type" "push") (set_attr "mode" "QI")])

;; Situation is quite tricky about when to choose full sized (SImode) move ;; over QImode moves. For Q_REG -> Q_REG move we use full size only for ;; partial register dependency machines (such as AMD Athlon), where QImode ;; moves issue extra dependency and for partial register stalls machines ;; that don't use QImode patterns (and QImode move cause stall on the next ;; instruction). ;; ;; For loads of Q_REG to NONQ_REG we use full sized moves except for partial ;; register stall machines with, where we use QImode instructions, since ;; partial register stall can be caused there. Then we use movzx. (define_insn "*movqi_1" [(set (match_operand:QI 0 "nonimmediate_operand" "=q,q ,q ,r,r ,?r,m") (match_operand:QI 1 "general_operand" " q,qn,qm,q,rn,qm,qn"))] "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM" { switch (get_attr_type (insn)) { case TYPE_IMOVX: if (!ANY_QI_REG_P (operands[1]) && GET_CODE (operands[1]) != MEM) abort (); return "movz{bl|x}\t{%1, %k0|%k0, %1}"; default: if (get_attr_mode (insn) == MODE_SI) return "mov{l}\t{%k1, %k0|%k0, %k1}"; else return "mov{b}\t{%1, %0|%0, %1}"; } } [(set (attr "type") (cond [(and (eq_attr "alternative" "3") (ior (eq (symbol_ref "TARGET_PARTIAL_REG_STALL") (const_int 0)) (eq (symbol_ref "TARGET_QIMODE_MATH") (const_int 0)))) (const_string "imov") (eq_attr "alternative" "3,5") (const_string "imovx") (and (ne (symbol_ref "TARGET_MOVX") (const_int 0)) (eq_attr "alternative" "2")) (const_string "imovx") ] (const_string "imov"))) (set (attr "mode") (cond [(eq_attr "alternative" "3,4,5") (const_string "SI") (eq_attr "alternative" "6") (const_string "QI") (eq_attr "type" "imovx") (const_string "SI") (and (eq_attr "type" "imov") (and (eq_attr "alternative" "0,1,2") (ne (symbol_ref "TARGET_PARTIAL_REG_DEPENDENCY") (const_int 0)))) (const_string "SI") ;; Avoid partial register stalls when not using QImode arithmetic (and (eq_attr "type" "imov") (and (eq_attr "alternative" "0,1,2") (and (ne (symbol_ref "TARGET_PARTIAL_REG_STALL") (const_int 0)) (eq (symbol_ref "TARGET_QIMODE_MATH") (const_int 0))))) (const_string "SI") ] (const_string "QI")))])

(define_expand "reload_outqi" [(parallel [(match_operand:QI 0 "" "=m") (match_operand:QI 1 "register_operand" "r") (match_operand:QI 2 "register_operand" "=&q")])] "" { rtx op0, op1, op2; op0 = operands[0]; op1 = operands[1]; op2 = operands[2];

if (reg_overlap_mentioned_p (op2, op0)) abort (); if (! q_regs_operand (op1, QImode)) { emit_insn (gen_movqi (op2, op1)); op1 = op2; } emit_insn (gen_movqi (op0, op1)); DONE; })

(define_insn "*swapqi_1" [(set (match_operand:QI 0 "register_operand" "+r") (match_operand:QI 1 "register_operand" "+r")) (set (match_dup 1) (match_dup 0))] "!TARGET_PARTIAL_REG_STALL || optimize_size" "xchg{l}\t%k1, %k0" [(set_attr "type" "imov") (set_attr "mode" "SI") (set_attr "pent_pair" "np") (set_attr "athlon_decode" "vector") (set_attr "ppro_uops" "few")])

(define_insn "*swapqi_2" [(set (match_operand:QI 0 "register_operand" "+q") (match_operand:QI 1 "register_operand" "+q")) (set (match_dup 1) (match_dup 0))] "TARGET_PARTIAL_REG_STALL" "xchg{b}\t%1, %0" [(set_attr "type" "imov") (set_attr "mode" "QI") (set_attr "pent_pair" "np") (set_attr "athlon_decode" "vector") (set_attr "ppro_uops" "few")])

(define_expand "movstrictqi" [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "")) (match_operand:QI 1 "general_operand" ""))] "! TARGET_PARTIAL_REG_STALL || optimize_size" { /* Don't generate memory->memory moves, go through a register. */ if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM) operands[1] = force_reg (QImode, operands[1]); })

(define_insn "*movstrictqi_1" [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,q")) (match_operand:QI 1 "general_operand" "*qn,m"))] "(! TARGET_PARTIAL_REG_STALL || optimize_size) && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)" "mov{b}\t{%1, %0|%0, %1}" [(set_attr "type" "imov") (set_attr "mode" "QI")])

(define_insn "*movstrictqi_xor" [(set (strict_low_part (match_operand:QI 0 "q_regs_operand" "+q")) (match_operand:QI 1 "const0_operand" "i")) (clobber (reg:CC 17))] "reload_completed && (!TARGET_USE_MOV0 || optimize_size)" "xor{b}\t{%0, %0|%0, %0}" [(set_attr "type" "alu1") (set_attr "mode" "QI") (set_attr "length_immediate" "0")])

(define_insn "*movsi_extv_1" [(set (match_operand:SI 0 "register_operand" "=R") (sign_extract:SI (match_operand 1 "ext_register_operand" "Q") (const_int 8) (const_int 8)))] "" "movs{bl|x}\t{%h1, %0|%0, %h1}" [(set_attr "type" "imovx") (set_attr "mode" "SI")])

(define_insn "*movhi_extv_1" [(set (match_operand:HI 0 "register_operand" "=R") (sign_extract:HI (match_operand 1 "ext_register_operand" "Q") (const_int 8) (const_int 8)))] "" "movs{bl|x}\t{%h1, %k0|%k0, %h1}" [(set_attr "type" "imovx") (set_attr "mode" "SI")])

(define_insn "*movqi_extv_1" [(set (match_operand:QI 0 "nonimmediate_operand" "=Qm,?r") (sign_extract:QI (match_operand 1 "ext_register_operand" "Q,Q") (const_int 8) (const_int 8)))] "!TARGET_64BIT" { switch (get_attr_type (insn)) { case TYPE_IMOVX: return "movs{bl|x}\t{%h1, %k0|%k0, %h1}"; default: return "mov{b}\t{%h1, %0|%0, %h1}"; } } [(set (attr "type") (if_then_else (and (match_operand:QI 0 "register_operand" "") (ior (not (match_operand:QI 0 "q_regs_operand" "")) (ne (symbol_ref "TARGET_MOVX") (const_int 0)))) (const_string "imovx") (const_string "imov"))) (set (attr "mode") (if_then_else (eq_attr "type" "imovx") (const_string "SI") (const_string "QI")))])

(define_insn "*movqi_extv_1_rex64" [(set (match_operand:QI 0 "register_operand" "=Q,?R") (sign_extract:QI (match_operand 1 "ext_register_operand" "Q,Q") (const_int 8) (const_int 8)))] "TARGET_64BIT" { switch (get_attr_type (insn)) { case TYPE_IMOVX: return "movs{bl|x}\t{%h1, %k0|%k0, %h1}"; default: return "mov{b}\t{%h1, %0|%0, %h1}"; } } [(set (attr "type") (if_then_else (and (match_operand:QI 0 "register_operand" "") (ior (not (match_operand:QI 0 "q_regs_operand" "")) (ne (symbol_ref "TARGET_MOVX") (const_int 0)))) (const_string "imovx") (const_string "imov"))) (set (attr "mode") (if_then_else (eq_attr "type" "imovx") (const_string "SI") (const_string "QI")))])

;; Stores and loads of ax to arbitrary constant address. ;; We fake an second form of instruction to force reload to load address ;; into register when rax is not available (define_insn "movabsqi_1_rex64" [(set (mem:QI (match_operand:DI 0 "x86_64_movabs_operand" "i,r")) (match_operand:QI 1 "nonmemory_operand" "a,er"))] "TARGET_64BIT && ix86_check_movabs (insn, 0)" "@ movabs{b}\t{%1, %P0|%P0, %1} mov{b}\t{%1, %a0|%a0, %1}" [(set_attr "type" "imov") (set_attr "modrm" "0,") (set_attr "length_address" "8,0") (set_attr "length_immediate" "0,*") (set_attr "memory" "store") (set_attr "mode" "QI")])

(define_insn "movabsqi_2_rex64" [(set (match_operand:QI 0 "register_operand" "=a,r") (mem:QI (match_operand:DI 1 "x86_64_movabs_operand" "i,r")))] "TARGET_64BIT && ix86_check_movabs (insn, 1)" "@ movabs{b}\t{%P1, %0|%0, %P1} mov{b}\t{%a1, %0|%0, %a1}" [(set_attr "type" "imov") (set_attr "modrm" "0,") (set_attr "length_address" "8,0") (set_attr "length_immediate" "0") (set_attr "memory" "load") (set_attr "mode" "QI")])

(define_insn "*movsi_extzv_1" [(set (match_operand:SI 0 "register_operand" "=R") (zero_extract:SI (match_operand 1 "ext_register_operand" "Q") (const_int 8) (const_int 8)))] "" "movz{bl|x}\t{%h1, %0|%0, %h1}" [(set_attr "type" "imovx") (set_attr "mode" "SI")])

(define_insn "*movqi_extzv_2" [(set (match_operand:QI 0 "nonimmediate_operand" "=Qm,?R") (subreg:QI (zero_extract:SI (match_operand 1 "ext_register_operand" "Q,Q") (const_int 8) (const_int 8)) 0))] "!TARGET_64BIT" { switch (get_attr_type (insn)) { case TYPE_IMOVX: return "movz{bl|x}\t{%h1, %k0|%k0, %h1}"; default: return "mov{b}\t{%h1, %0|%0, %h1}"; } } [(set (attr "type") (if_then_else (and (match_operand:QI 0 "register_operand" "") (ior (not (match_operand:QI 0 "q_regs_operand" "")) (ne (symbol_ref "TARGET_MOVX") (const_int 0)))) (const_string "imovx") (const_string "imov"))) (set (attr "mode") (if_then_else (eq_attr "type" "imovx") (const_string "SI") (const_string "QI")))])

(define_insn "*movqi_extzv_2_rex64" [(set (match_operand:QI 0 "register_operand" "=Q,?R") (subreg:QI (zero_extract:SI (match_operand 1 "ext_register_operand" "Q,Q") (const_int 8) (const_int 8)) 0))] "TARGET_64BIT" { switch (get_attr_type (insn)) { case TYPE_IMOVX: return "movz{bl|x}\t{%h1, %k0|%k0, %h1}"; default: return "mov{b}\t{%h1, %0|%0, %h1}"; } } [(set (attr "type") (if_then_else (ior (not (match_operand:QI 0 "q_regs_operand" "")) (ne (symbol_ref "TARGET_MOVX") (const_int 0))) (const_string "imovx") (const_string "imov"))) (set (attr "mode") (if_then_else (eq_attr "type" "imovx") (const_string "SI") (const_string "QI")))])

(define_insn "movsi_insv_1" [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "+Q") (const_int 8) (const_int 8)) (match_operand:SI 1 "general_operand" "Qmn"))] "!TARGET_64BIT" "mov{b}\t{%b1, %h0|%h0, %b1}" [(set_attr "type" "imov") (set_attr "mode" "QI")])

(define_insn "movdi_insv_1_rex64" [(set (zero_extract:DI (match_operand 0 "ext_register_operand" "+Q") (const_int 8) (const_int 8)) (match_operand:DI 1 "nonmemory_operand" "Qn"))] "TARGET_64BIT" "mov{b}\t{%b1, %h0|%h0, %b1}" [(set_attr "type" "imov") (set_attr "mode" "QI")])

(define_insn "*movqi_insv_2" [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "+Q") (const_int 8) (const_int 8)) (lshiftrt:SI (match_operand:SI 1 "register_operand" "Q") (const_int 8)))] "" "mov{b}\t{%h1, %h0|%h0, %h1}" [(set_attr "type" "imov") (set_attr "mode" "QI")])

(define_expand "movdi" [(set (match_operand:DI 0 "nonimmediate_operand" "") (match_operand:DI 1 "general_operand" ""))] "" "ix86_expand_move (DImode, operands); DONE;")

(define_insn "pushdi" [(set (match_operand:DI 0 "push_operand" "=<") (match_operand:DI 1 "general_no_elim_operand" "riFm"))] "!TARGET_64BIT" "#")

(define_insn "pushdi2_rex64" [(set (match_operand:DI 0 "push_operand" "=<,!<") (match_operand:DI 1 "general_no_elim_operand" "re*m,n"))] "TARGET_64BIT" "@ push{q}\t%1 #" [(set_attr "type" "push,multi") (set_attr "mode" "DI")])

;; Convert impossible pushes of immediate to existing instructions. ;; First try to get scratch register and go through it. In case this ;; fails, push sign extended lower part first and then overwrite ;; upper part by 32bit move. (define_peephole2 [(match_scratch:DI 2 "r") (set (match_operand:DI 0 "push_operand" "") (match_operand:DI 1 "immediate_operand" ""))] "TARGET_64BIT && !symbolic_operand (operands[1], DImode) && !x86_64_immediate_operand (operands[1], DImode)" [(set (match_dup 2) (match_dup 1)) (set (match_dup 0) (match_dup 2))] "")

;; We need to define this as both peepholer and splitter for case ;; peephole2 pass is not run. (define_peephole2 [(set (match_operand:DI 0 "push_operand" "") (match_operand:DI 1 "immediate_operand" ""))] "TARGET_64BIT && !symbolic_operand (operands[1], DImode) && !x86_64_immediate_operand (operands[1], DImode) && 1" [(set (match_dup 0) (match_dup 1)) (set (match_dup 2) (match_dup 3))] "split_di (operands + 1, 1, operands + 2, operands + 3); operands[1] = gen_lowpart (DImode, operands[2]); operands[2] = gen_rtx_MEM (SImode, gen_rtx_PLUS (DImode, stack_pointer_rtx, GEN_INT (4))); ")

(define_split [(set (match_operand:DI 0 "push_operand" "") (match_operand:DI 1 "immediate_operand" ""))] "TARGET_64BIT && (flow2_completed || (reload_completed && !flag_peephole2)) && !symbolic_operand (operands[1], DImode) && !x86_64_immediate_operand (operands[1], DImode)" [(set (match_dup 0) (match_dup 1)) (set (match_dup 2) (match_dup 3))] "split_di (operands + 1, 1, operands + 2, operands + 3); operands[1] = gen_lowpart (DImode, operands[2]); operands[2] = gen_rtx_MEM (SImode, gen_rtx_PLUS (DImode, stack_pointer_rtx, GEN_INT (4))); ")

(define_insn "pushdi2_prologue_rex64" [(set (match_operand:DI 0 "push_operand" "=<") (match_operand:DI 1 "general_no_elim_operand" "rem")) (clobber (mem:BLK (scratch)))] "TARGET_64BIT" "push{q}\t%1" [(set_attr "type" "push") (set_attr "mode" "DI")])

(define_insn "popdi1_epilogue_rex64" [(set (match_operand:DI 0 "nonimmediate_operand" "=rm") (mem:DI (reg:DI 7))) (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8))) (clobber (mem:BLK (scratch)))] "TARGET_64BIT" "pop{q}\t%0" [(set_attr "type" "pop") (set_attr "mode" "DI")])

(define_insn "popdi1" [(set (match_operand:DI 0 "nonimmediate_operand" "=r*m") (mem:DI (reg:DI 7))) (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))] "TARGET_64BIT" "pop{q}\t%0" [(set_attr "type" "pop") (set_attr "mode" "DI")])

(define_insn "*movdi_xor_rex64" [(set (match_operand:DI 0 "register_operand" "=r") (match_operand:DI 1 "const0_operand" "i")) (clobber (reg:CC 17))] "TARGET_64BIT && (!TARGET_USE_MOV0 || optimize_size) && reload_completed" "xor{l}\t{%k0, %k0|%k0, %k0}" [(set_attr "type" "alu1") (set_attr "mode" "SI") (set_attr "length_immediate" "0")])

(define_insn "*movdi_or_rex64" [(set (match_operand:DI 0 "register_operand" "=r") (match_operand:DI 1 "const_int_operand" "i")) (clobber (reg:CC 17))] "TARGET_64BIT && (TARGET_PENTIUM || optimize_size) && reload_completed && operands[1] == constm1_rtx" { operands[1] = constm1_rtx; return "or{q}\t{%1, %0|%0, %1}"; } [(set_attr "type" "alu1") (set_attr "mode" "DI") (set_attr "length_immediate" "1")])

(define_insn "movdi_2" [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o,!my,!*y,!m,!*Y,!*Y") (match_operand:DI 1 "general_operand" "riFo,riF,*y,m,*Y,*Y,m"))] "!TARGET_64BIT && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)" "@

movq\t{%1, %0|%0, %1} movq\t{%1, %0|%0, %1} movq\t{%1, %0|%0, %1} movdqa\t{%1, %0|%0, %1} movq\t{%1, %0|%0, %1}" [(set_attr "type" ",,mmx,mmx,ssemov,ssemov,ssemov") (set_attr "mode" "DI,DI,DI,DI,DI,TI,DI")])

(define_split [(set (match_operand:DI 0 "push_operand" "") (match_operand:DI 1 "general_operand" ""))] "!TARGET_64BIT && reload_completed && (! MMX_REG_P (operands[1]) && !SSE_REG_P (operands[1]))" [(const_int 0)] "ix86_split_long_move (operands); DONE;")

;; %%% This multiword shite has got to go. (define_split [(set (match_operand:DI 0 "nonimmediate_operand" "") (match_operand:DI 1 "general_operand" ""))] "!TARGET_64BIT && reload_completed && (!MMX_REG_P (operands[0]) && !SSE_REG_P (operands[0])) && (!MMX_REG_P (operands[1]) && !SSE_REG_P (operands[1]))" [(const_int 0)] "ix86_split_long_move (operands); DONE;")

(define_insn "movdi_1_rex64" [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,mr,!mr,!y,!rm,!y,!Y,!rm,!Y") (match_operand:DI 1 "general_operand" "Z,rem,i,re,n,y,y,rm,Y,Y,rm"))] "TARGET_64BIT && (TARGET_INTER_UNIT_MOVES || optimize_size) && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)" { switch (get_attr_type (insn)) { case TYPE_SSEMOV: if (get_attr_mode (insn) == MODE_TI) return "movdqa\t{%1, %0|%0, %1}"; / FALLTHRU / case TYPE_MMXMOV: / Moves from and into integer register is done using movd opcode with REX prefix. / if (GENERAL_REG_P (operands[0]) || GENERAL_REG_P (operands[1])) return "movd\t{%1, %0|%0, %1}"; return "movq\t{%1, %0|%0, %1}"; case TYPE_MULTI: return "#"; case TYPE_LEA: return "lea{q}\t{%a1, %0|%0, %a1}"; default: if (flag_pic && !LEGITIMATE_PIC_OPERAND_P (operands[1])) abort (); if (get_attr_mode (insn) == MODE_SI) return "mov{l}\t{%k1, %k0|%k0, %k1}"; else if (which_alternative == 2) return "movabs{q}\t{%1, %0|%0, %1}"; else return "mov{q}\t{%1, %0|%0, %1}"; } } [(set (attr "type") (cond [(eq_attr "alternative" "5,6,7") (const_string "mmxmov") (eq_attr "alternative" "8,9,10") (const_string "ssemov") (eq_attr "alternative" "4") (const_string "multi") (and (ne (symbol_ref "flag_pic") (const_int 0)) (match_operand:DI 1 "symbolic_operand" "")) (const_string "lea") ] (const_string "imov"))) (set_attr "modrm" ",0,0,,,,,,,,") (set_attr "length_immediate" ",4,8,,,,,,,,*") (set_attr "mode" "SI,DI,DI,DI,SI,DI,DI,DI,TI,DI,DI")])

(define_insn "movdi_1_rex64_nointerunit" [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,mr,!mr,!y,!m,!y,!Y,!m,!Y") (match_operand:DI 1 "general_operand" "Z,rem,i,re,n,y,y,m,Y,Y,m"))] "TARGET_64BIT && (!TARGET_INTER_UNIT_MOVES && !optimize_size) && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)" { switch (get_attr_type (insn)) { case TYPE_SSEMOV: if (get_attr_mode (insn) == MODE_TI) return "movdqa\t{%1, %0|%0, %1}"; / FALLTHRU / case TYPE_MMXMOV: return "movq\t{%1, %0|%0, %1}"; case TYPE_MULTI: return "#"; case TYPE_LEA: return "lea{q}\t{%a1, %0|%0, %a1}"; default: if (flag_pic && !LEGITIMATE_PIC_OPERAND_P (operands[1])) abort (); if (get_attr_mode (insn) == MODE_SI) return "mov{l}\t{%k1, %k0|%k0, %k1}"; else if (which_alternative == 2) return "movabs{q}\t{%1, %0|%0, %1}"; else return "mov{q}\t{%1, %0|%0, %1}"; } } [(set (attr "type") (cond [(eq_attr "alternative" "5,6,7") (const_string "mmxmov") (eq_attr "alternative" "8,9,10") (const_string "ssemov") (eq_attr "alternative" "4") (const_string "multi") (and (ne (symbol_ref "flag_pic") (const_int 0)) (match_operand:DI 1 "symbolic_operand" "")) (const_string "lea") ] (const_string "imov"))) (set_attr "modrm" ",0,0,,,,,,,,") (set_attr "length_immediate" ",4,8,,,,,,,,*") (set_attr "mode" "SI,DI,DI,DI,SI,DI,DI,DI,TI,DI,DI")])

;; Stores and loads of ax to arbitrary constant address. ;; We fake an second form of instruction to force reload to load address ;; into register when rax is not available (define_insn "movabsdi_1_rex64" [(set (mem:DI (match_operand:DI 0 "x86_64_movabs_operand" "i,r")) (match_operand:DI 1 "nonmemory_operand" "a,er"))] "TARGET_64BIT && ix86_check_movabs (insn, 0)" "@ movabs{q}\t{%1, %P0|%P0, %1} mov{q}\t{%1, %a0|%a0, %1}" [(set_attr "type" "imov") (set_attr "modrm" "0,") (set_attr "length_address" "8,0") (set_attr "length_immediate" "0,*") (set_attr "memory" "store") (set_attr "mode" "DI")])

(define_insn "movabsdi_2_rex64" [(set (match_operand:DI 0 "register_operand" "=a,r") (mem:DI (match_operand:DI 1 "x86_64_movabs_operand" "i,r")))] "TARGET_64BIT && ix86_check_movabs (insn, 1)" "@ movabs{q}\t{%P1, %0|%0, %P1} mov{q}\t{%a1, %0|%0, %a1}" [(set_attr "type" "imov") (set_attr "modrm" "0,") (set_attr "length_address" "8,0") (set_attr "length_immediate" "0") (set_attr "memory" "load") (set_attr "mode" "DI")])

;; Convert impossible stores of immediate to existing instructions. ;; First try to get scratch register and go through it. In case this ;; fails, move by 32bit parts. (define_peephole2 [(match_scratch:DI 2 "r") (set (match_operand:DI 0 "memory_operand" "") (match_operand:DI 1 "immediate_operand" ""))] "TARGET_64BIT && !symbolic_operand (operands[1], DImode) && !x86_64_immediate_operand (operands[1], DImode)" [(set (match_dup 2) (match_dup 1)) (set (match_dup 0) (match_dup 2))] "")

;; We need to define this as both peepholer and splitter for case ;; peephole2 pass is not run. (define_peephole2 [(set (match_operand:DI 0 "memory_operand" "") (match_operand:DI 1 "immediate_operand" ""))] "TARGET_64BIT && !symbolic_operand (operands[1], DImode) && !x86_64_immediate_operand (operands[1], DImode) && 1" [(set (match_dup 2) (match_dup 3)) (set (match_dup 4) (match_dup 5))] "split_di (operands, 2, operands + 2, operands + 4);")

(define_split [(set (match_operand:DI 0 "memory_operand" "") (match_operand:DI 1 "immediate_operand" ""))] "TARGET_64BIT && (flow2_completed || (reload_completed && !flag_peephole2)) && !symbolic_operand (operands[1], DImode) && !x86_64_immediate_operand (operands[1], DImode)" [(set (match_dup 2) (match_dup 3)) (set (match_dup 4) (match_dup 5))] "split_di (operands, 2, operands + 2, operands + 4);")

(define_insn "*swapdi_rex64" [(set (match_operand:DI 0 "register_operand" "+r") (match_operand:DI 1 "register_operand" "+r")) (set (match_dup 1) (match_dup 0))] "TARGET_64BIT" "xchg{q}\t%1, %0" [(set_attr "type" "imov") (set_attr "mode" "DI") (set_attr "pent_pair" "np") (set_attr "athlon_decode" "vector") (set_attr "ppro_uops" "few")])

(define_expand "movsf" [(set (match_operand:SF 0 "nonimmediate_operand" "") (match_operand:SF 1 "general_operand" ""))] "" "ix86_expand_move (SFmode, operands); DONE;")

(define_insn "*pushsf" [(set (match_operand:SF 0 "push_operand" "=<,<,<") (match_operand:SF 1 "general_no_elim_operand" "f#rx,rFm#fx,x#rf"))] "!TARGET_64BIT" { switch (which_alternative) { case 1: return "push{l}\t%1";

default:
  /* This insn should be already split before reg-stack.  */
  abort ();
}

} [(set_attr "type" "multi,push,multi") (set_attr "mode" "SF,SI,SF")])

(define_insn "*pushsf_rex64" [(set (match_operand:SF 0 "push_operand" "=X,X,X") (match_operand:SF 1 "nonmemory_no_elim_operand" "f#rx,rF#fx,x#rf"))] "TARGET_64BIT" { switch (which_alternative) { case 1: return "push{q}\t%q1";

default:
  /* This insn should be already split before reg-stack.  */
  abort ();
}

} [(set_attr "type" "multi,push,multi") (set_attr "mode" "SF,DI,SF")])

(define_split [(set (match_operand:SF 0 "push_operand" "") (match_operand:SF 1 "memory_operand" ""))] "reload_completed && GET_CODE (operands[1]) == MEM && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (XEXP (operands[1], 0))" [(set (match_dup 0) (match_dup 1))] "operands[1] = get_pool_constant (XEXP (operands[1], 0));")

;; %%% Kill this when call knows how to work this out. (define_split [(set (match_operand:SF 0 "push_operand" "") (match_operand:SF 1 "any_fp_register_operand" ""))] "!TARGET_64BIT" [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -4))) (set (mem:SF (reg:SI 7)) (match_dup 1))])

(define_split [(set (match_operand:SF 0 "push_operand" "") (match_operand:SF 1 "any_fp_register_operand" ""))] "TARGET_64BIT" [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -8))) (set (mem:SF (reg:DI 7)) (match_dup 1))])

(define_insn "*movsf_1" [(set (match_operand:SF 0 "nonimmediate_operand" "=f#xr,m,f#xr,r#xf,m,x#rf,x#rf,x#rf,m,!*y,!rm,!*y") (match_operand:SF 1 "general_operand" "fm#rx,f#rx,G,rmF#fx,Fr#fx,C,x,xm#rf,x#rf,rm,*y,*y"))] "(TARGET_INTER_UNIT_MOVES || optimize_size) && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM) && (reload_in_progress || reload_completed || (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE) || GET_CODE (operands[1]) != CONST_DOUBLE || memory_operand (operands[0], SFmode))" { switch (which_alternative) { case 0: if (REG_P (operands[1]) && find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) return "fstp\t%y0"; else if (STACK_TOP_P (operands[0])) return "fld%z1\t%y1"; else return "fst\t%y0";

case 1:
  if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
    return "fstp%z0\t%y0";
  else
    return "fst%z0\t%y0";

case 2:
  return standard_80387_constant_opcode (operands[1]);

case 3:
case 4:
  return "mov{l}\t{%1, %0|%0, %1}";
case 5:
  if (get_attr_mode (insn) == MODE_TI)
return "pxor\t%0, %0";
  else
return "xorps\t%0, %0";
case 6:
  if (get_attr_mode (insn) == MODE_V4SF)
return "movaps\t{%1, %0|%0, %1}";
  else
return "movss\t{%1, %0|%0, %1}";
case 7:
case 8:
  return "movss\t{%1, %0|%0, %1}";

case 9:
case 10:
  return "movd\t{%1, %0|%0, %1}";

case 11:
  return "movq\t{%1, %0|%0, %1}";

default:
  abort();
}

} [(set_attr "type" "fmov,fmov,fmov,imov,imov,ssemov,ssemov,ssemov,ssemov,mmxmov,mmxmov,mmxmov") (set (attr "mode") (cond [(eq_attr "alternative" "3,4,9,10") (const_string "SI") (eq_attr "alternative" "5") (if_then_else (and (and (ne (symbol_ref "TARGET_SSE_LOAD0_BY_PXOR") (const_int 0)) (ne (symbol_ref "TARGET_SSE2") (const_int 0))) (eq (symbol_ref "optimize_size") (const_int 0))) (const_string "TI") (const_string "V4SF")) /* For architectures resolving dependencies on whole SSE registers use APS move to break dependency chains, otherwise use short move to avoid extra work.

	  Do the same for architectures resolving dependencies on
	  the parts.  While in DF mode it is better to always handle
	  just register parts, the SF mode is different due to lack
	  of instructions to load just part of the register.  It is
	  better to maintain the whole registers in single format
	  to avoid problems on using packed logical operations.  */
       (eq_attr "alternative" "6")
	 (if_then_else
	   (ior (ne (symbol_ref "TARGET_SSE_PARTIAL_REG_DEPENDENCY")
		    (const_int 0))
		(ne (symbol_ref "TARGET_SSE_PARTIAL_REGS")
		    (const_int 0)))
	   (const_string "V4SF")
	   (const_string "SF"))
       (eq_attr "alternative" "11")
	 (const_string "DI")]
       (const_string "SF")))])

(define_insn "*movsf_1_nointerunit" [(set (match_operand:SF 0 "nonimmediate_operand" "=f#xr,m,f#xr,r#xf,m,x#rf,x#rf,x#rf,m,!*y,!m,!*y") (match_operand:SF 1 "general_operand" "fm#rx,f#rx,G,rmF#fx,Fr#fx,C,x,xm#rf,x#rf,m,*y,*y"))] "(!TARGET_INTER_UNIT_MOVES && !optimize_size) && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM) && (reload_in_progress || reload_completed || (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE) || GET_CODE (operands[1]) != CONST_DOUBLE || memory_operand (operands[0], SFmode))" { switch (which_alternative) { case 0: if (REG_P (operands[1]) && find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) { if (REGNO (operands[0]) == FIRST_STACK_REG && TARGET_USE_FFREEP) return "ffreep\t%y0"; return "fstp\t%y0"; } else if (STACK_TOP_P (operands[0])) return "fld%z1\t%y1"; else return "fst\t%y0";

case 1:
  if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
    return "fstp%z0\t%y0";
  else
    return "fst%z0\t%y0";

case 2:
  return standard_80387_constant_opcode (operands[1]);

case 3:
case 4:
  return "mov{l}\t{%1, %0|%0, %1}";
case 5:
  if (get_attr_mode (insn) == MODE_TI)
return "pxor\t%0, %0";
  else
return "xorps\t%0, %0";
case 6:
  if (get_attr_mode (insn) == MODE_V4SF)
return "movaps\t{%1, %0|%0, %1}";
  else
return "movss\t{%1, %0|%0, %1}";
case 7:
case 8:
  return "movss\t{%1, %0|%0, %1}";

case 9:
case 10:
  return "movd\t{%1, %0|%0, %1}";

case 11:
  return "movq\t{%1, %0|%0, %1}";

default:
  abort();
}

	  Do the same for architectures resolving dependencies on
	  the parts.  While in DF mode it is better to always handle
	  just register parts, the SF mode is different due to lack
	  of instructions to load just part of the register.  It is
	  better to maintain the whole registers in single format
	  to avoid problems on using packed logical operations.  */
       (eq_attr "alternative" "6")
	 (if_then_else
	   (ior (ne (symbol_ref "TARGET_SSE_PARTIAL_REG_DEPENDENCY")
		    (const_int 0))
		(ne (symbol_ref "TARGET_SSE_PARTIAL_REGS")
		    (const_int 0)))
	   (const_string "V4SF")
	   (const_string "SF"))
       (eq_attr "alternative" "11")
	 (const_string "DI")]
       (const_string "SF")))])

(define_insn "*swapsf" [(set (match_operand:SF 0 "register_operand" "+f") (match_operand:SF 1 "register_operand" "+f")) (set (match_dup 1) (match_dup 0))] "reload_completed || !TARGET_SSE" { if (STACK_TOP_P (operands[0])) return "fxch\t%1"; else return "fxch\t%0"; } [(set_attr "type" "fxch") (set_attr "mode" "SF")])

(define_expand "movdf" [(set (match_operand:DF 0 "nonimmediate_operand" "") (match_operand:DF 1 "general_operand" ""))] "" "ix86_expand_move (DFmode, operands); DONE;")

;; Size of pushdf is 3 (for sub) + 2 (for fstp) + memory operand size. ;; Size of pushdf using integer instructions is 2+2*memory operand size ;; On the average, pushdf using integers can be still shorter. Allow this ;; pattern for optimize_size too.

(define_insn "*pushdf_nointeger" [(set (match_operand:DF 0 "push_operand" "=<,<,<,<") (match_operand:DF 1 "general_no_elim_operand" "f#Y,Fo#fY,r#fY,Y#f"))] "!TARGET_64BIT && !TARGET_INTEGER_DFMODE_MOVES" { / This insn should be already split before reg-stack. */ abort (); } [(set_attr "type" "multi") (set_attr "mode" "DF,SI,SI,DF")])

(define_insn "pushdf_integer" [(set (match_operand:DF 0 "push_operand" "=<,<,<") (match_operand:DF 1 "general_no_elim_operand" "f#rY,rFo#fY,Y#rf"))] "TARGET_64BIT || TARGET_INTEGER_DFMODE_MOVES" { / This insn should be already split before reg-stack. */ abort (); } [(set_attr "type" "multi") (set_attr "mode" "DF,SI,DF")])

;; %%% Kill this when call knows how to work this out. (define_split [(set (match_operand:DF 0 "push_operand" "") (match_operand:DF 1 "any_fp_register_operand" ""))] "!TARGET_64BIT && reload_completed" [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -8))) (set (mem:DF (reg:SI 7)) (match_dup 1))] "")

(define_split [(set (match_operand:DF 0 "push_operand" "") (match_operand:DF 1 "any_fp_register_operand" ""))] "TARGET_64BIT && reload_completed" [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -8))) (set (mem:DF (reg:DI 7)) (match_dup 1))] "")

(define_split [(set (match_operand:DF 0 "push_operand" "") (match_operand:DF 1 "general_operand" ""))] "reload_completed" [(const_int 0)] "ix86_split_long_move (operands); DONE;")

;; Moving is usually shorter when only FP registers are used. This separate ;; movdf pattern avoids the use of integer registers for FP operations ;; when optimizing for size.

(define_insn "*movdf_nointeger" [(set (match_operand:DF 0 "nonimmediate_operand" "=f#Y,m,f#Y,*r,o,Y#f,Y#f,Y#f,m") (match_operand:DF 1 "general_operand" "fm#Y,f#Y,G,roF,Fr,C,Y#f,YHm#f,Y#f"))] "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM) && ((optimize_size || !TARGET_INTEGER_DFMODE_MOVES) && !TARGET_64BIT) && (reload_in_progress || reload_completed || (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE) || GET_CODE (operands[1]) != CONST_DOUBLE || memory_operand (operands[0], DFmode))" { switch (which_alternative) { case 0: if (REG_P (operands[1]) && find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) { if (REGNO (operands[0]) == FIRST_STACK_REG && TARGET_USE_FFREEP) return "ffreep\t%y0"; return "fstp\t%y0"; } else if (STACK_TOP_P (operands[0])) return "fld%z1\t%y1"; else return "fst\t%y0";

case 1:
  if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
    return "fstp%z0\t%y0";
  else
    return "fst%z0\t%y0";

case 2:
  return standard_80387_constant_opcode (operands[1]);

case 3:
case 4:
  return "#";
case 5:
  switch (get_attr_mode (insn))
{
case MODE_V4SF:
  return "xorps\t%0, %0";
case MODE_V2DF:
  return "xorpd\t%0, %0";
case MODE_TI:
  return "pxor\t%0, %0";
default:
  abort ();
}
case 6:
  switch (get_attr_mode (insn))
{
case MODE_V4SF:
  return "movaps\t{%1, %0|%0, %1}";
case MODE_V2DF:
  return "movapd\t{%1, %0|%0, %1}";
case MODE_DF:
  return "movsd\t{%1, %0|%0, %1}";
default:
  abort ();
}
case 7:
  if (get_attr_mode (insn) == MODE_V2DF)
return "movlpd\t{%1, %0|%0, %1}";
  else
return "movsd\t{%1, %0|%0, %1}";
case 8:
  return "movsd\t{%1, %0|%0, %1}";

default:
  abort();
}

} [(set_attr "type" "fmov,fmov,fmov,multi,multi,ssemov,ssemov,ssemov,ssemov") (set (attr "mode") (cond [(eq_attr "alternative" "3,4") (const_string "SI") /* xorps is one byte shorter. / (eq_attr "alternative" "5") (cond [(ne (symbol_ref "optimize_size") (const_int 0)) (const_string "V4SF") (ne (symbol_ref "TARGET_SSE_LOAD0_BY_PXOR") (const_int 0)) (const_string "TI")] (const_string "V2DF")) / For architectures resolving dependencies on whole SSE registers use APD move to break dependency chains, otherwise use short move to avoid extra work.

	  movaps encodes one byte shorter.  */
       (eq_attr "alternative" "6")
	 (cond
	  [(ne (symbol_ref "optimize_size")
	       (const_int 0))
	     (const_string "V4SF")
	   (ne (symbol_ref "TARGET_SSE_PARTIAL_REG_DEPENDENCY")
	       (const_int 0))
	     (const_string "V2DF")]
	   (const_string "DF"))
       /* For architectures resolving dependencies on register
	  parts we may avoid extra work to zero out upper part
	  of register.  */
       (eq_attr "alternative" "7")
	 (if_then_else
	   (ne (symbol_ref "TARGET_SSE_PARTIAL_REGS")
	       (const_int 0))
	   (const_string "V2DF")
	   (const_string "DF"))]
       (const_string "DF")))])

(define_insn "*movdf_integer" [(set (match_operand:DF 0 "nonimmediate_operand" "=f#Yr,m,f#Yr,r#Yf,o,Y#rf,Y#rf,Y#rf,m") (match_operand:DF 1 "general_operand" "fm#Yr,f#Yr,G,roF#Yf,Fr#Yf,C,Y#rf,Ym#rf,Y#rf"))] "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM) && ((!optimize_size && TARGET_INTEGER_DFMODE_MOVES) || TARGET_64BIT) && (reload_in_progress || reload_completed || (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE) || GET_CODE (operands[1]) != CONST_DOUBLE || memory_operand (operands[0], DFmode))" { switch (which_alternative) { case 0: if (REG_P (operands[1]) && find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) { if (REGNO (operands[0]) == FIRST_STACK_REG && TARGET_USE_FFREEP) return "ffreep\t%y0"; return "fstp\t%y0"; } else if (STACK_TOP_P (operands[0])) return "fld%z1\t%y1"; else return "fst\t%y0";

case 1:
  if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
    return "fstp%z0\t%y0";
  else
    return "fst%z0\t%y0";

case 2:
  return standard_80387_constant_opcode (operands[1]);

case 3:
case 4:
  return "#";

case 5:
  switch (get_attr_mode (insn))
{
case MODE_V4SF:
  return "xorps\t%0, %0";
case MODE_V2DF:
  return "xorpd\t%0, %0";
case MODE_TI:
  return "pxor\t%0, %0";
default:
  abort ();
}
case 6:
  switch (get_attr_mode (insn))
{
case MODE_V4SF:
  return "movaps\t{%1, %0|%0, %1}";
case MODE_V2DF:
  return "movapd\t{%1, %0|%0, %1}";
case MODE_DF:
  return "movsd\t{%1, %0|%0, %1}";
default:
  abort ();
}
case 7:
  if (get_attr_mode (insn) == MODE_V2DF)
return "movlpd\t{%1, %0|%0, %1}";
  else
return "movsd\t{%1, %0|%0, %1}";
case 8:
  return "movsd\t{%1, %0|%0, %1}";

default:
  abort();
}

	  movaps encodes one byte shorter.  */
       (eq_attr "alternative" "6")
	 (cond
	  [(ne (symbol_ref "optimize_size")
	       (const_int 0))
	     (const_string "V4SF")
	   (ne (symbol_ref "TARGET_SSE_PARTIAL_REG_DEPENDENCY")
	       (const_int 0))
	     (const_string "V2DF")]
	   (const_string "DF"))
       /* For architectures resolving dependencies on register
	  parts we may avoid extra work to zero out upper part
	  of register.  */
       (eq_attr "alternative" "7")
	 (if_then_else
	   (ne (symbol_ref "TARGET_SSE_PARTIAL_REGS")
	       (const_int 0))
	   (const_string "V2DF")
	   (const_string "DF"))]
       (const_string "DF")))])

(define_split [(set (match_operand:DF 0 "nonimmediate_operand" "") (match_operand:DF 1 "general_operand" ""))] "reload_completed && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM) && ! (ANY_FP_REG_P (operands[0]) || (GET_CODE (operands[0]) == SUBREG && ANY_FP_REG_P (SUBREG_REG (operands[0])))) && ! (ANY_FP_REG_P (operands[1]) || (GET_CODE (operands[1]) == SUBREG && ANY_FP_REG_P (SUBREG_REG (operands[1]))))" [(const_int 0)] "ix86_split_long_move (operands); DONE;")

(define_insn "*swapdf" [(set (match_operand:DF 0 "register_operand" "+f") (match_operand:DF 1 "register_operand" "+f")) (set (match_dup 1) (match_dup 0))] "reload_completed || !TARGET_SSE2" { if (STACK_TOP_P (operands[0])) return "fxch\t%1"; else return "fxch\t%0"; } [(set_attr "type" "fxch") (set_attr "mode" "DF")])

(define_expand "movxf" [(set (match_operand:XF 0 "nonimmediate_operand" "") (match_operand:XF 1 "general_operand" ""))] "" "ix86_expand_move (XFmode, operands); DONE;")

;; Size of pushdf is 3 (for sub) + 2 (for fstp) + memory operand size. ;; Size of pushdf using integer instructions is 3+3*memory operand size ;; Pushing using integer instructions is longer except for constants ;; and direct memory references. ;; (assuming that any given constant is pushed only once, but this ought to be ;; handled elsewhere).

(define_insn "*pushxf_nointeger" [(set (match_operand:XF 0 "push_operand" "=X,X,X") (match_operand:XF 1 "general_no_elim_operand" "f,Fo,r"))] "optimize_size" { / This insn should be already split before reg-stack. */ abort (); } [(set_attr "type" "multi") (set_attr "mode" "XF,SI,SI")])

(define_insn "pushxf_integer" [(set (match_operand:XF 0 "push_operand" "=<,<") (match_operand:XF 1 "general_no_elim_operand" "f#r,ro#f"))] "!optimize_size" { / This insn should be already split before reg-stack. */ abort (); } [(set_attr "type" "multi") (set_attr "mode" "XF,SI")])

(define_split [(set (match_operand 0 "push_operand" "") (match_operand 1 "general_operand" ""))] "reload_completed && (GET_MODE (operands[0]) == XFmode || GET_MODE (operands[0]) == DFmode) && !ANY_FP_REG_P (operands[1])" [(const_int 0)] "ix86_split_long_move (operands); DONE;")

(define_split [(set (match_operand:XF 0 "push_operand" "") (match_operand:XF 1 "any_fp_register_operand" ""))] "!TARGET_64BIT" [(set (reg:SI 7) (plus:SI (reg:SI 7) (match_dup 2))) (set (mem:XF (reg:SI 7)) (match_dup 1))] "operands[2] = GEN_INT (TARGET_128BIT_LONG_DOUBLE ? -16 : -12);")

(define_split [(set (match_operand:XF 0 "push_operand" "") (match_operand:XF 1 "any_fp_register_operand" ""))] "TARGET_64BIT" [(set (reg:DI 7) (plus:DI (reg:DI 7) (match_dup 2))) (set (mem:XF (reg:DI 7)) (match_dup 1))] "operands[2] = GEN_INT (TARGET_128BIT_LONG_DOUBLE ? -16 : -12);")

;; Do not use integer registers when optimizing for size (define_insn "*movxf_nointeger" [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m,f,*r,o") (match_operand:XF 1 "general_operand" "fm,f,G,roF,Fr"))] "optimize_size && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM) && (reload_in_progress || reload_completed || GET_CODE (operands[1]) != CONST_DOUBLE || memory_operand (operands[0], XFmode))" { switch (which_alternative) { case 0: if (REG_P (operands[1]) && find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) { if (REGNO (operands[0]) == FIRST_STACK_REG && TARGET_USE_FFREEP) return "ffreep\t%y0"; return "fstp\t%y0"; } else if (STACK_TOP_P (operands[0])) return "fld%z1\t%y1"; else return "fst\t%y0";

case 1:
  /* There is no non-popping store to memory for XFmode.  So if
 we need one, follow the store with a load.  */
  if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
    return "fstp%z0\t%y0\;fld%z0\t%y0";
  else
    return "fstp%z0\t%y0";

case 2:
  return standard_80387_constant_opcode (operands[1]);

case 3: case 4:
  return "#";
}

abort(); } [(set_attr "type" "fmov,fmov,fmov,multi,multi") (set_attr "mode" "XF,XF,XF,SI,SI")])

(define_insn "*movxf_integer" [(set (match_operand:XF 0 "nonimmediate_operand" "=f#r,m,f#r,r#f,o") (match_operand:XF 1 "general_operand" "fm#r,f#r,G,roF#f,Fr#f"))] "!optimize_size && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM) && (reload_in_progress || reload_completed || GET_CODE (operands[1]) != CONST_DOUBLE || memory_operand (operands[0], XFmode))" { switch (which_alternative) { case 0: if (REG_P (operands[1]) && find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) { if (REGNO (operands[0]) == FIRST_STACK_REG && TARGET_USE_FFREEP) return "ffreep\t%y0"; return "fstp\t%y0"; } else if (STACK_TOP_P (operands[0])) return "fld%z1\t%y1"; else return "fst\t%y0";

case 1:
  /* There is no non-popping store to memory for XFmode.  So if
 we need one, follow the store with a load.  */
  if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
    return "fstp%z0\t%y0\;fld%z0\t%y0";
  else
    return "fstp%z0\t%y0";

case 2:
  return standard_80387_constant_opcode (operands[1]);

case 3: case 4:
  return "#";
}

abort(); } [(set_attr "type" "fmov,fmov,fmov,multi,multi") (set_attr "mode" "XF,XF,XF,SI,SI")])

(define_split [(set (match_operand 0 "nonimmediate_operand" "") (match_operand 1 "general_operand" ""))] "reload_completed && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM) && GET_MODE (operands[0]) == XFmode && ! (ANY_FP_REG_P (operands[0]) || (GET_CODE (operands[0]) == SUBREG && ANY_FP_REG_P (SUBREG_REG (operands[0])))) && ! (ANY_FP_REG_P (operands[1]) || (GET_CODE (operands[1]) == SUBREG && ANY_FP_REG_P (SUBREG_REG (operands[1]))))" [(const_int 0)] "ix86_split_long_move (operands); DONE;")

(define_split [(set (match_operand 0 "register_operand" "") (match_operand 1 "memory_operand" ""))] "reload_completed && GET_CODE (operands[1]) == MEM && (GET_MODE (operands[0]) == XFmode || GET_MODE (operands[0]) == SFmode || GET_MODE (operands[0]) == DFmode) && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (XEXP (operands[1], 0))" [(set (match_dup 0) (match_dup 1))] { rtx c = get_pool_constant (XEXP (operands[1], 0)); rtx r = operands[0];

if (GET_CODE (r) == SUBREG) r = SUBREG_REG (r);

if (SSE_REG_P (r)) { if (!standard_sse_constant_p (c)) FAIL; } else if (FP_REG_P (r)) { if (!standard_80387_constant_p (c)) FAIL; } else if (MMX_REG_P (r)) FAIL;

operands[1] = c; })

(define_insn "swapxf" [(set (match_operand:XF 0 "register_operand" "+f") (match_operand:XF 1 "register_operand" "+f")) (set (match_dup 1) (match_dup 0))] "" { if (STACK_TOP_P (operands[0])) return "fxch\t%1"; else return "fxch\t%0"; } [(set_attr "type" "fxch") (set_attr "mode" "XF")]) ;; Zero extension instructions

(define_expand "zero_extendhisi2" [(set (match_operand:SI 0 "register_operand" "") (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "")))] "" { if (TARGET_ZERO_EXTEND_WITH_AND && !optimize_size) { operands[1] = force_reg (HImode, operands[1]); emit_insn (gen_zero_extendhisi2_and (operands[0], operands[1])); DONE; } })

(define_insn "zero_extendhisi2_and" [(set (match_operand:SI 0 "register_operand" "=r") (zero_extend:SI (match_operand:HI 1 "register_operand" "0"))) (clobber (reg:CC 17))] "TARGET_ZERO_EXTEND_WITH_AND && !optimize_size" "#" [(set_attr "type" "alu1") (set_attr "mode" "SI")])

(define_split [(set (match_operand:SI 0 "register_operand" "") (zero_extend:SI (match_operand:HI 1 "register_operand" ""))) (clobber (reg:CC 17))] "reload_completed && TARGET_ZERO_EXTEND_WITH_AND && !optimize_size" [(parallel [(set (match_dup 0) (and:SI (match_dup 0) (const_int 65535))) (clobber (reg:CC 17))])] "")

(define_insn "*zero_extendhisi2_movzwl" [(set (match_operand:SI 0 "register_operand" "=r") (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "rm")))] "!TARGET_ZERO_EXTEND_WITH_AND || optimize_size" "movz{wl|x}\t{%1, %0|%0, %1}" [(set_attr "type" "imovx") (set_attr "mode" "SI")])

(define_expand "zero_extendqihi2" [(parallel [(set (match_operand:HI 0 "register_operand" "") (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" ""))) (clobber (reg:CC 17))])] "" "")

(define_insn "*zero_extendqihi2_and" [(set (match_operand:HI 0 "register_operand" "=r,?&q") (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "0,qm"))) (clobber (reg:CC 17))] "TARGET_ZERO_EXTEND_WITH_AND && !optimize_size" "#" [(set_attr "type" "alu1") (set_attr "mode" "HI")])

(define_insn "*zero_extendqihi2_movzbw_and" [(set (match_operand:HI 0 "register_operand" "=r,r") (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "qm,0"))) (clobber (reg:CC 17))] "!TARGET_ZERO_EXTEND_WITH_AND || optimize_size" "#" [(set_attr "type" "imovx,alu1") (set_attr "mode" "HI")])

(define_insn "*zero_extendqihi2_movzbw" [(set (match_operand:HI 0 "register_operand" "=r") (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "qm")))] "(!TARGET_ZERO_EXTEND_WITH_AND || optimize_size) && reload_completed" "movz{bw|x}\t{%1, %0|%0, %1}" [(set_attr "type" "imovx") (set_attr "mode" "HI")])

;; For the movzbw case strip only the clobber (define_split [(set (match_operand:HI 0 "register_operand" "") (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" ""))) (clobber (reg:CC 17))] "reload_completed && (!TARGET_ZERO_EXTEND_WITH_AND || optimize_size) && (!REG_P (operands[1]) || ANY_QI_REG_P (operands[1]))" [(set (match_operand:HI 0 "register_operand" "") (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))])

;; When source and destination does not overlap, clear destination ;; first and then do the movb (define_split [(set (match_operand:HI 0 "register_operand" "") (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" ""))) (clobber (reg:CC 17))] "reload_completed && ANY_QI_REG_P (operands[0]) && (TARGET_ZERO_EXTEND_WITH_AND && !optimize_size) && !reg_overlap_mentioned_p (operands[0], operands[1])" [(set (match_dup 0) (const_int 0)) (set (strict_low_part (match_dup 2)) (match_dup 1))] "operands[2] = gen_lowpart (QImode, operands[0]);")

;; Rest is handled by single and. (define_split [(set (match_operand:HI 0 "register_operand" "") (zero_extend:HI (match_operand:QI 1 "register_operand" ""))) (clobber (reg:CC 17))] "reload_completed && true_regnum (operands[0]) == true_regnum (operands[1])" [(parallel [(set (match_dup 0) (and:HI (match_dup 0) (const_int 255))) (clobber (reg:CC 17))])] "")

(define_expand "zero_extendqisi2" [(parallel [(set (match_operand:SI 0 "register_operand" "") (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" ""))) (clobber (reg:CC 17))])] "" "")

(define_insn "*zero_extendqisi2_and" [(set (match_operand:SI 0 "register_operand" "=r,?&q") (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "0,qm"))) (clobber (reg:CC 17))] "TARGET_ZERO_EXTEND_WITH_AND && !optimize_size" "#" [(set_attr "type" "alu1") (set_attr "mode" "SI")])

(define_insn "*zero_extendqisi2_movzbw_and" [(set (match_operand:SI 0 "register_operand" "=r,r") (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "qm,0"))) (clobber (reg:CC 17))] "!TARGET_ZERO_EXTEND_WITH_AND || optimize_size" "#" [(set_attr "type" "imovx,alu1") (set_attr "mode" "SI")])

(define_insn "*zero_extendqisi2_movzbw" [(set (match_operand:SI 0 "register_operand" "=r") (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "qm")))] "(!TARGET_ZERO_EXTEND_WITH_AND || optimize_size) && reload_completed" "movz{bl|x}\t{%1, %0|%0, %1}" [(set_attr "type" "imovx") (set_attr "mode" "SI")])

;; For the movzbl case strip only the clobber (define_split [(set (match_operand:SI 0 "register_operand" "") (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" ""))) (clobber (reg:CC 17))] "reload_completed && (!TARGET_ZERO_EXTEND_WITH_AND || optimize_size) && (!REG_P (operands[1]) || ANY_QI_REG_P (operands[1]))" [(set (match_dup 0) (zero_extend:SI (match_dup 1)))])

;; When source and destination does not overlap, clear destination ;; first and then do the movb (define_split [(set (match_operand:SI 0 "register_operand" "") (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" ""))) (clobber (reg:CC 17))] "reload_completed && ANY_QI_REG_P (operands[0]) && (ANY_QI_REG_P (operands[1]) || GET_CODE (operands[1]) == MEM) && (TARGET_ZERO_EXTEND_WITH_AND && !optimize_size) && !reg_overlap_mentioned_p (operands[0], operands[1])" [(set (match_dup 0) (const_int 0)) (set (strict_low_part (match_dup 2)) (match_dup 1))] "operands[2] = gen_lowpart (QImode, operands[0]);")

;; Rest is handled by single and. (define_split [(set (match_operand:SI 0 "register_operand" "") (zero_extend:SI (match_operand:QI 1 "register_operand" ""))) (clobber (reg:CC 17))] "reload_completed && true_regnum (operands[0]) == true_regnum (operands[1])" [(parallel [(set (match_dup 0) (and:SI (match_dup 0) (const_int 255))) (clobber (reg:CC 17))])] "")

;; %%% Kill me once multi-word ops are sane. (define_expand "zero_extendsidi2" [(set (match_operand:DI 0 "register_operand" "=r") (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "rm")))] "" "if (!TARGET_64BIT) { emit_insn (gen_zero_extendsidi2_32 (operands[0], operands[1])); DONE; } ")

(define_insn "zero_extendsidi2_32" [(set (match_operand:DI 0 "nonimmediate_operand" "=r,?r,?*o,!?y,!?Y") (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "0,rm,r,m,m"))) (clobber (reg:CC 17))] "!TARGET_64BIT && !TARGET_INTER_UNIT_MOVES" "@

movd\t{%1, %0|%0, %1} movd\t{%1, %0|%0, %1}" [(set_attr "mode" "SI,SI,SI,DI,TI") (set_attr "type" "multi,multi,multi,mmxmov,ssemov")])

(define_insn "*zero_extendsidi2_32_1" [(set (match_operand:DI 0 "nonimmediate_operand" "=r,?r,?*o,!?y,!?Y") (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "0,rm,r,rm,rm"))) (clobber (reg:CC 17))] "!TARGET_64BIT && TARGET_INTER_UNIT_MOVES" "@

movd\t{%1, %0|%0, %1} movd\t{%1, %0|%0, %1}" [(set_attr "mode" "SI,SI,SI,DI,TI") (set_attr "type" "multi,multi,multi,mmxmov,ssemov")])

(define_insn "zero_extendsidi2_rex64" [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o,!?y,!?Y") (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "rm,0,m,m")))] "TARGET_64BIT && !TARGET_INTER_UNIT_MOVES" "@ mov\t{%k1, %k0|%k0, %k1}

movd\t{%1, %0|%0, %1} movd\t{%1, %0|%0, %1}" [(set_attr "type" "imovx,imov,mmxmov,ssemov") (set_attr "mode" "SI,DI,DI,TI")])

(define_insn "zero_extendsidi2_rex64_1" [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o,!?y,!?") (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "rm,0,rm,rm")))] "TARGET_64BIT && TARGET_INTER_UNIT_MOVES" "@ mov\t{%k1, %k0|%k0, %k1}

movd\t{%1, %0|%0, %1} movd\t{%1, %0|%0, %1}" [(set_attr "type" "imovx,imov,mmxmov,ssemov") (set_attr "mode" "SI,DI,SI,SI")])

(define_split [(set (match_operand:DI 0 "memory_operand" "") (zero_extend:DI (match_dup 0)))] "TARGET_64BIT" [(set (match_dup 4) (const_int 0))] "split_di (&operands[0], 1, &operands[3], &operands[4]);")

(define_split [(set (match_operand:DI 0 "register_operand" "") (zero_extend:DI (match_operand:SI 1 "register_operand" ""))) (clobber (reg:CC 17))] "!TARGET_64BIT && reload_completed && true_regnum (operands[0]) == true_regnum (operands[1])" [(set (match_dup 4) (const_int 0))] "split_di (&operands[0], 1, &operands[3], &operands[4]);")

(define_split [(set (match_operand:DI 0 "nonimmediate_operand" "") (zero_extend:DI (match_operand:SI 1 "general_operand" ""))) (clobber (reg:CC 17))] "!TARGET_64BIT && reload_completed && !SSE_REG_P (operands[0]) && !MMX_REG_P (operands[0])" [(set (match_dup 3) (match_dup 1)) (set (match_dup 4) (const_int 0))] "split_di (&operands[0], 1, &operands[3], &operands[4]);")

(define_insn "zero_extendhidi2" [(set (match_operand:DI 0 "register_operand" "=r,r") (zero_extend:DI (match_operand:HI 1 "nonimmediate_operand" "r,m")))] "TARGET_64BIT" "@ movz{wl|x}\t{%1, %k0|%k0, %1} movz{wq|x}\t{%1, %0|%0, %1}" [(set_attr "type" "imovx") (set_attr "mode" "SI,DI")])

(define_insn "zero_extendqidi2" [(set (match_operand:DI 0 "register_operand" "=r,r") (zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "Q,m")))] "TARGET_64BIT" "@ movz{bl|x}\t{%1, %k0|%k0, %1} movz{bq|x}\t{%1, %0|%0, %1}" [(set_attr "type" "imovx") (set_attr "mode" "SI,DI")]) ;; Sign extension instructions

(define_expand "extendsidi2" [(parallel [(set (match_operand:DI 0 "register_operand" "") (sign_extend:DI (match_operand:SI 1 "register_operand" ""))) (clobber (reg:CC 17)) (clobber (match_scratch:SI 2 ""))])] "" { if (TARGET_64BIT) { emit_insn (gen_extendsidi2_rex64 (operands[0], operands[1])); DONE; } })

(define_insn "*extendsidi2_1" [(set (match_operand:DI 0 "nonimmediate_operand" "=*A,r,?r,?*o") (sign_extend:DI (match_operand:SI 1 "register_operand" "0,0,r,r"))) (clobber (reg:CC 17)) (clobber (match_scratch:SI 2 "=X,X,X,&r"))] "!TARGET_64BIT" "#")

(define_insn "extendsidi2_rex64" [(set (match_operand:DI 0 "register_operand" "=*a,r") (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "*0,rm")))] "TARGET_64BIT" "@ {cltq|cdqe} movs{lq|x}\t{%1,%0|%0, %1}" [(set_attr "type" "imovx") (set_attr "mode" "DI") (set_attr "prefix_0f" "0") (set_attr "modrm" "0,1")])

(define_insn "extendhidi2" [(set (match_operand:DI 0 "register_operand" "=r") (sign_extend:DI (match_operand:HI 1 "nonimmediate_operand" "rm")))] "TARGET_64BIT" "movs{wq|x}\t{%1,%0|%0, %1}" [(set_attr "type" "imovx") (set_attr "mode" "DI")])

(define_insn "extendqidi2" [(set (match_operand:DI 0 "register_operand" "=r") (sign_extend:DI (match_operand:QI 1 "nonimmediate_operand" "qm")))] "TARGET_64BIT" "movs{bq|x}\t{%1,%0|%0, %1}" [(set_attr "type" "imovx") (set_attr "mode" "DI")])

;; Extend to memory case when source register does die. (define_split [(set (match_operand:DI 0 "memory_operand" "") (sign_extend:DI (match_operand:SI 1 "register_operand" ""))) (clobber (reg:CC 17)) (clobber (match_operand:SI 2 "register_operand" ""))] "(reload_completed && dead_or_set_p (insn, operands[1]) && !reg_mentioned_p (operands[1], operands[0]))" [(set (match_dup 3) (match_dup 1)) (parallel [(set (match_dup 1) (ashiftrt:SI (match_dup 1) (const_int 31))) (clobber (reg:CC 17))]) (set (match_dup 4) (match_dup 1))] "split_di (&operands[0], 1, &operands[3], &operands[4]);")

;; Extend to memory case when source register does not die. (define_split [(set (match_operand:DI 0 "memory_operand" "") (sign_extend:DI (match_operand:SI 1 "register_operand" ""))) (clobber (reg:CC 17)) (clobber (match_operand:SI 2 "register_operand" ""))] "reload_completed" [(const_int 0)] { split_di (&operands[0], 1, &operands[3], &operands[4]);

emit_move_insn (operands[3], operands[1]);

/* Generate a cltd if possible and doing so it profitable. */ if (true_regnum (operands[1]) == 0 && true_regnum (operands[2]) == 1 && (optimize_size || TARGET_USE_CLTD)) { emit_insn (gen_ashrsi3_31 (operands[2], operands[1], GEN_INT (31))); } else { emit_move_insn (operands[2], operands[1]); emit_insn (gen_ashrsi3_31 (operands[2], operands[2], GEN_INT (31))); } emit_move_insn (operands[4], operands[2]); DONE; })

;; Extend to register case. Optimize case where source and destination ;; registers match and cases where we can use cltd. (define_split [(set (match_operand:DI 0 "register_operand" "") (sign_extend:DI (match_operand:SI 1 "register_operand" ""))) (clobber (reg:CC 17)) (clobber (match_scratch:SI 2 ""))] "reload_completed" [(const_int 0)] { split_di (&operands[0], 1, &operands[3], &operands[4]);

if (true_regnum (operands[3]) != true_regnum (operands[1])) emit_move_insn (operands[3], operands[1]);

/* Generate a cltd if possible and doing so it profitable. */ if (true_regnum (operands[3]) == 0 && (optimize_size || TARGET_USE_CLTD)) { emit_insn (gen_ashrsi3_31 (operands[4], operands[3], GEN_INT (31))); DONE; }

if (true_regnum (operands[4]) != true_regnum (operands[1])) emit_move_insn (operands[4], operands[1]);

emit_insn (gen_ashrsi3_31 (operands[4], operands[4], GEN_INT (31))); DONE; })

(define_insn "extendhisi2" [(set (match_operand:SI 0 "register_operand" "=*a,r") (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "*0,rm")))] "" { switch (get_attr_prefix_0f (insn)) { case 0: return "{cwtl|cwde}"; default: return "movs{wl|x}\t{%1,%0|%0, %1}"; } } [(set_attr "type" "imovx") (set_attr "mode" "SI") (set (attr "prefix_0f") ;; movsx is short decodable while cwtl is vector decoded. (if_then_else (and (eq_attr "cpu" "!k6") (eq_attr "alternative" "0")) (const_string "0") (const_string "1"))) (set (attr "modrm") (if_then_else (eq_attr "prefix_0f" "0") (const_string "0") (const_string "1")))])

(define_insn "*extendhisi2_zext" [(set (match_operand:DI 0 "register_operand" "=*a,r") (zero_extend:DI (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "*0,rm"))))] "TARGET_64BIT" { switch (get_attr_prefix_0f (insn)) { case 0: return "{cwtl|cwde}"; default: return "movs{wl|x}\t{%1,%k0|%k0, %1}"; } } [(set_attr "type" "imovx") (set_attr "mode" "SI") (set (attr "prefix_0f") ;; movsx is short decodable while cwtl is vector decoded. (if_then_else (and (eq_attr "cpu" "!k6") (eq_attr "alternative" "0")) (const_string "0") (const_string "1"))) (set (attr "modrm") (if_then_else (eq_attr "prefix_0f" "0") (const_string "0") (const_string "1")))])

(define_insn "extendqihi2" [(set (match_operand:HI 0 "register_operand" "=*a,r") (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "*0,qm")))] "" { switch (get_attr_prefix_0f (insn)) { case 0: return "{cbtw|cbw}"; default: return "movs{bw|x}\t{%1,%0|%0, %1}"; } } [(set_attr "type" "imovx") (set_attr "mode" "HI") (set (attr "prefix_0f") ;; movsx is short decodable while cwtl is vector decoded. (if_then_else (and (eq_attr "cpu" "!k6") (eq_attr "alternative" "0")) (const_string "0") (const_string "1"))) (set (attr "modrm") (if_then_else (eq_attr "prefix_0f" "0") (const_string "0") (const_string "1")))])

(define_insn "extendqisi2" [(set (match_operand:SI 0 "register_operand" "=r") (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "qm")))] "" "movs{bl|x}\t{%1,%0|%0, %1}" [(set_attr "type" "imovx") (set_attr "mode" "SI")])

(define_insn "*extendqisi2_zext" [(set (match_operand:DI 0 "register_operand" "=r") (zero_extend:DI (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "qm"))))] "TARGET_64BIT" "movs{bl|x}\t{%1,%k0|%k0, %1}" [(set_attr "type" "imovx") (set_attr "mode" "SI")]) ;; Conversions between float and double.

;; These are all no-ops in the model used for the 80387. So just ;; emit moves.

;; %%% Kill these when call knows how to work out a DFmode push earlier. (define_insn "*dummy_extendsfdf2" [(set (match_operand:DF 0 "push_operand" "=<") (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "fY")))] "0" "#")

(define_split [(set (match_operand:DF 0 "push_operand" "") (float_extend:DF (match_operand:SF 1 "fp_register_operand" "")))] "!TARGET_64BIT" [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -8))) (set (mem:DF (reg:SI 7)) (float_extend:DF (match_dup 1)))])

(define_split [(set (match_operand:DF 0 "push_operand" "") (float_extend:DF (match_operand:SF 1 "fp_register_operand" "")))] "TARGET_64BIT" [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -8))) (set (mem:DF (reg:DI 7)) (float_extend:DF (match_dup 1)))])

(define_insn "*dummy_extendsfxf2" [(set (match_operand:XF 0 "push_operand" "=<") (float_extend:XF (match_operand:SF 1 "nonimmediate_operand" "f")))] "0" "#")

(define_split [(set (match_operand:XF 0 "push_operand" "") (float_extend:XF (match_operand:SF 1 "fp_register_operand" "")))] "" [(set (reg:SI 7) (plus:SI (reg:SI 7) (match_dup 2))) (set (mem:XF (reg:SI 7)) (float_extend:XF (match_dup 1)))] "operands[2] = GEN_INT (TARGET_128BIT_LONG_DOUBLE ? -16 : -12);")

(define_split [(set (match_operand:XF 0 "push_operand" "") (float_extend:XF (match_operand:SF 1 "fp_register_operand" "")))] "TARGET_64BIT" [(set (reg:DI 7) (plus:DI (reg:DI 7) (match_dup 2))) (set (mem:DF (reg:DI 7)) (float_extend:XF (match_dup 1)))] "operands[2] = GEN_INT (TARGET_128BIT_LONG_DOUBLE ? -16 : -12);")

(define_split [(set (match_operand:XF 0 "push_operand" "") (float_extend:XF (match_operand:DF 1 "fp_register_operand" "")))] "" [(set (reg:SI 7) (plus:SI (reg:SI 7) (match_dup 2))) (set (mem:DF (reg:SI 7)) (float_extend:XF (match_dup 1)))] "operands[2] = GEN_INT (TARGET_128BIT_LONG_DOUBLE ? -16 : -12);")

(define_split [(set (match_operand:XF 0 "push_operand" "") (float_extend:XF (match_operand:DF 1 "fp_register_operand" "")))] "TARGET_64BIT" [(set (reg:DI 7) (plus:DI (reg:DI 7) (match_dup 2))) (set (mem:XF (reg:DI 7)) (float_extend:XF (match_dup 1)))] "operands[2] = GEN_INT (TARGET_128BIT_LONG_DOUBLE ? -16 : -12);")

(define_expand "extendsfdf2" [(set (match_operand:DF 0 "nonimmediate_operand" "") (float_extend:DF (match_operand:SF 1 "general_operand" "")))] "TARGET_80387 || TARGET_SSE2" { /* ??? Needed for compress_float_constant since all fp constants are LEGITIMATE_CONSTANT_P. */ if (GET_CODE (operands[1]) == CONST_DOUBLE) operands[1] = validize_mem (force_const_mem (SFmode, operands[1])); if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM) operands[1] = force_reg (SFmode, operands[1]); })

(define_insn "*extendsfdf2_1" [(set (match_operand:DF 0 "nonimmediate_operand" "=f#Y,mf#Y,Y#f") (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "fm#Y,f#Y,mY#f")))] "(TARGET_80387 || TARGET_SSE2) && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)" { switch (which_alternative) { case 0: if (REG_P (operands[1]) && find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) return "fstp\t%y0"; else if (STACK_TOP_P (operands[0])) return "fld%z1\t%y1"; else return "fst\t%y0";

case 1:
  if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
    return "fstp%z0\t%y0";

  else
    return "fst%z0\t%y0";
case 2:
  return "cvtss2sd\t{%1, %0|%0, %1}";

default:
  abort ();
}

} [(set_attr "type" "fmov,fmov,ssecvt") (set_attr "mode" "SF,XF,DF")])

(define_insn "*extendsfdf2_1_sse_only" [(set (match_operand:DF 0 "register_operand" "=Y") (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "mY")))] "!TARGET_80387 && TARGET_SSE2 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)" "cvtss2sd\t{%1, %0|%0, %1}" [(set_attr "type" "ssecvt") (set_attr "mode" "DF")])

(define_expand "extendsfxf2" [(set (match_operand:XF 0 "nonimmediate_operand" "") (float_extend:XF (match_operand:SF 1 "general_operand" "")))] "TARGET_80387" { /* ??? Needed for compress_float_constant since all fp constants are LEGITIMATE_CONSTANT_P. */ if (GET_CODE (operands[1]) == CONST_DOUBLE) operands[1] = validize_mem (force_const_mem (SFmode, operands[1])); if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM) operands[1] = force_reg (SFmode, operands[1]); })

(define_insn "*extendsfxf2_1" [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m") (float_extend:XF (match_operand:SF 1 "nonimmediate_operand" "fm,f")))] "TARGET_80387 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)" { switch (which_alternative) { case 0: if (REG_P (operands[1]) && find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) return "fstp\t%y0"; else if (STACK_TOP_P (operands[0])) return "fld%z1\t%y1"; else return "fst\t%y0";

case 1:
  /* There is no non-popping store to memory for XFmode.  So if
 we need one, follow the store with a load.  */
  if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
    return "fstp%z0\t%y0\n\tfld%z0\t%y0";
  else
    return "fstp%z0\t%y0";

default:
  abort ();
}

} [(set_attr "type" "fmov") (set_attr "mode" "SF,XF")])

(define_expand "extenddfxf2" [(set (match_operand:XF 0 "nonimmediate_operand" "") (float_extend:XF (match_operand:DF 1 "general_operand" "")))] "TARGET_80387" { /* ??? Needed for compress_float_constant since all fp constants are LEGITIMATE_CONSTANT_P. */ if (GET_CODE (operands[1]) == CONST_DOUBLE) operands[1] = validize_mem (force_const_mem (DFmode, operands[1])); if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM) operands[1] = force_reg (DFmode, operands[1]); })

(define_insn "*extenddfxf2_1" [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m") (float_extend:XF (match_operand:DF 1 "nonimmediate_operand" "fm,f")))] "TARGET_80387 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)" { switch (which_alternative) { case 0: if (REG_P (operands[1]) && find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) return "fstp\t%y0"; else if (STACK_TOP_P (operands[0])) return "fld%z1\t%y1"; else return "fst\t%y0";

case 1:
  /* There is no non-popping store to memory for XFmode.  So if
 we need one, follow the store with a load.  */
  if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
    return "fstp%z0\t%y0\n\tfld%z0\t%y0";
  else
    return "fstp%z0\t%y0";

default:
  abort ();
}

} [(set_attr "type" "fmov") (set_attr "mode" "DF,XF")])

;; %%% This seems bad bad news. ;; This cannot output into an f-reg because there is no way to be sure ;; of truncating in that case. Otherwise this is just like a simple move ;; insn. So we pretend we can output to a reg in order to get better ;; register preferencing, but we really use a stack slot.

(define_expand "truncdfsf2" [(parallel [(set (match_operand:SF 0 "nonimmediate_operand" "") (float_truncate:SF (match_operand:DF 1 "register_operand" ""))) (clobber (match_dup 2))])] "TARGET_80387 || TARGET_SSE2" " if (TARGET_80387) operands[2] = assign_386_stack_local (SFmode, 0); else { emit_insn (gen_truncdfsf2_sse_only (operands[0], operands[1])); DONE; } ")

(define_insn "*truncdfsf2_1" [(set (match_operand:SF 0 "nonimmediate_operand" "=m,?f#rx,?r#fx,?x#rf") (float_truncate:SF (match_operand:DF 1 "register_operand" "f,f,f,f"))) (clobber (match_operand:SF 2 "memory_operand" "=X,m,m,m"))] "TARGET_80387 && !TARGET_SSE2" { switch (which_alternative) { case 0: if (find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) return "fstp%z0\t%y0"; else return "fst%z0\t%y0"; default: abort (); } } [(set_attr "type" "fmov,multi,multi,multi") (set_attr "mode" "SF,SF,SF,SF")])

(define_insn "truncdfsf2_1_sse" [(set (match_operand:SF 0 "nonimmediate_operand" "=!m#fxr,?f#xr,?r#fx,?x#fr,Y#fr") (float_truncate:SF (match_operand:DF 1 "nonimmediate_operand" "f#Y,f#Y,f#Y,f#Y,mY#f"))) (clobber (match_operand:SF 2 "memory_operand" "=X,m,m,m,X"))] "TARGET_80387 && TARGET_SSE2 && !TARGET_SSE_PARTIAL_REGS_FOR_CVTSD2SS" { switch (which_alternative) { case 0: if (find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) return "fstp%z0\t%y0"; else return "fst%z0\t%y0"; case 4: return "#"; default: abort (); } } [(set_attr "type" "fmov,multi,multi,multi,ssecvt") (set_attr "mode" "SF,SF,SF,SF,DF")])

(define_insn "truncdfsf2_1_sse_nooverlap" [(set (match_operand:SF 0 "nonimmediate_operand" "=!m,?f#rx,?r#fx,?x#rf,&Y") (float_truncate:SF (match_operand:DF 1 "nonimmediate_operand" "f#Y,f#Y,f#Y,f#Y,mY#f"))) (clobber (match_operand:SF 2 "memory_operand" "=X,m,m,m,X"))] "TARGET_80387 && TARGET_SSE2 && TARGET_SSE_PARTIAL_REGS_FOR_CVTSD2SS" { switch (which_alternative) { case 0: if (find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) return "fstp%z0\t%y0"; else return "fst%z0\t%y0"; case 4: return "#"; default: abort (); } } [(set_attr "type" "fmov,multi,multi,multi,ssecvt") (set_attr "mode" "SF,SF,SF,SF,DF")])

(define_insn "truncdfsf2_2" [(set (match_operand:SF 0 "nonimmediate_operand" "=Y,Y,!m") (float_truncate:SF (match_operand:DF 1 "nonimmediate_operand" "Y,mY,f#Y")))] "TARGET_80387 && TARGET_SSE2 && !TARGET_SSE_PARTIAL_REGS_FOR_CVTSD2SS && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)" { switch (which_alternative) { case 0: case 1: return "cvtsd2ss\t{%1, %0|%0, %1}"; case 2: if (find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) return "fstp%z0\t%y0"; else return "fst%z0\t%y0"; default: abort (); } } [(set_attr "type" "ssecvt,ssecvt,fmov") (set_attr "athlon_decode" "vector,double,") (set_attr "mode" "SF,SF,SF")])

(define_insn "*truncdfsf2_2_nooverlap" [(set (match_operand:SF 0 "nonimmediate_operand" "=&Y,!m") (float_truncate:SF (match_operand:DF 1 "nonimmediate_operand" "mY,f")))] "TARGET_80387 && TARGET_SSE2 && TARGET_SSE_PARTIAL_REGS_FOR_CVTSD2SS && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)" { switch (which_alternative) { case 0: return "#"; case 1: if (find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) return "fstp%z0\t%y0"; else return "fst%z0\t%y0"; default: abort (); } } [(set_attr "type" "ssecvt,fmov") (set_attr "mode" "DF,SF")])

(define_insn "*truncdfsf2_3" [(set (match_operand:SF 0 "memory_operand" "=m") (float_truncate:SF (match_operand:DF 1 "register_operand" "f")))] "TARGET_80387" { if (find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) return "fstp%z0\t%y0"; else return "fst%z0\t%y0"; } [(set_attr "type" "fmov") (set_attr "mode" "SF")])

(define_insn "truncdfsf2_sse_only" [(set (match_operand:SF 0 "register_operand" "=Y,Y") (float_truncate:SF (match_operand:DF 1 "nonimmediate_operand" "Y,mY")))] "!TARGET_80387 && TARGET_SSE2 && !TARGET_SSE_PARTIAL_REGS_FOR_CVTSD2SS" "cvtsd2ss\t{%1, %0|%0, %1}" [(set_attr "type" "ssecvt") (set_attr "athlon_decode" "vector,double") (set_attr "mode" "SF")])

(define_insn "*truncdfsf2_sse_only_nooverlap" [(set (match_operand:SF 0 "register_operand" "=&Y") (float_truncate:SF (match_operand:DF 1 "nonimmediate_operand" "mY")))] "!TARGET_80387 && TARGET_SSE2 && TARGET_SSE_PARTIAL_REGS_FOR_CVTSD2SS" "#" [(set_attr "type" "ssecvt") (set_attr "mode" "DF")])

(define_split [(set (match_operand:SF 0 "memory_operand" "") (float_truncate:SF (match_operand:DF 1 "register_operand" ""))) (clobber (match_operand:SF 2 "memory_operand" ""))] "TARGET_80387" [(set (match_dup 0) (float_truncate:SF (match_dup 1)))] "")

; Avoid possible reformatting penalty on the destination by first ; zeroing it out (define_split [(set (match_operand:SF 0 "register_operand" "") (float_truncate:SF (match_operand:DF 1 "nonimmediate_operand" ""))) (clobber (match_operand 2 "" ""))] "TARGET_80387 && reload_completed && SSE_REG_P (operands[0]) && !STACK_REG_P (operands[1])" [(const_int 0)] { rtx src, dest; if (!TARGET_SSE_PARTIAL_REGS_FOR_CVTSD2SS) emit_insn (gen_truncdfsf2_sse_only (operands[0], operands[1])); else { dest = simplify_gen_subreg (V4SFmode, operands[0], SFmode, 0); src = simplify_gen_subreg (V2DFmode, operands[1], DFmode, 0); /* simplify_gen_subreg refuses to widen memory references. */ if (GET_CODE (src) == SUBREG) alter_subreg (&src); if (reg_overlap_mentioned_p (operands[0], operands[1])) abort (); emit_insn (gen_sse_clrv4sf (dest, CONST0_RTX (V4SFmode))); emit_insn (gen_cvtsd2ss (dest, dest, src)); } DONE; })

(define_split [(set (match_operand:SF 0 "register_operand" "") (float_truncate:SF (match_operand:DF 1 "nonimmediate_operand" "")))] "TARGET_80387 && reload_completed && SSE_REG_P (operands[0]) && TARGET_SSE_PARTIAL_REGS_FOR_CVTSD2SS" [(const_int 0)] { rtx src, dest; dest = simplify_gen_subreg (V4SFmode, operands[0], SFmode, 0); src = simplify_gen_subreg (V2DFmode, operands[1], DFmode, 0); /* simplify_gen_subreg refuses to widen memory references. */ if (GET_CODE (src) == SUBREG) alter_subreg (&src); if (reg_overlap_mentioned_p (operands[0], operands[1])) abort (); emit_insn (gen_sse_clrv4sf (dest, CONST0_RTX (V4SFmode))); emit_insn (gen_cvtsd2ss (dest, dest, src)); DONE; })

(define_split [(set (match_operand:SF 0 "register_operand" "") (float_truncate:SF (match_operand:DF 1 "fp_register_operand" ""))) (clobber (match_operand:SF 2 "memory_operand" ""))] "TARGET_80387 && reload_completed" [(set (match_dup 2) (float_truncate:SF (match_dup 1))) (set (match_dup 0) (match_dup 2))] "")

(define_expand "truncxfsf2" [(parallel [(set (match_operand:SF 0 "nonimmediate_operand" "") (float_truncate:SF (match_operand:XF 1 "register_operand" ""))) (clobber (match_dup 2))])] "TARGET_80387" "operands[2] = assign_386_stack_local (SFmode, 0);")

(define_insn "*truncxfsf2_1" [(set (match_operand:SF 0 "nonimmediate_operand" "=m,?f#rx,?r#fx,?x#rf") (float_truncate:SF (match_operand:XF 1 "register_operand" "f,f,f,f"))) (clobber (match_operand:SF 2 "memory_operand" "=X,m,m,m"))] "TARGET_80387" { switch (which_alternative) { case 0: if (find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) return "fstp%z0\t%y0"; else return "fst%z0\t%y0"; default: abort(); } } [(set_attr "type" "fmov,multi,multi,multi") (set_attr "mode" "SF")])

(define_insn "*truncxfsf2_2" [(set (match_operand:SF 0 "memory_operand" "=m") (float_truncate:SF (match_operand:XF 1 "register_operand" "f")))] "TARGET_80387" { if (find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) return "fstp%z0\t%y0"; else return "fst%z0\t%y0"; } [(set_attr "type" "fmov") (set_attr "mode" "SF")])

(define_split [(set (match_operand:SF 0 "memory_operand" "") (float_truncate:SF (match_operand:XF 1 "register_operand" ""))) (clobber (match_operand:SF 2 "memory_operand" ""))] "TARGET_80387" [(set (match_dup 0) (float_truncate:SF (match_dup 1)))] "")

(define_split [(set (match_operand:SF 0 "register_operand" "") (float_truncate:SF (match_operand:XF 1 "register_operand" ""))) (clobber (match_operand:SF 2 "memory_operand" ""))] "TARGET_80387 && reload_completed" [(set (match_dup 2) (float_truncate:SF (match_dup 1))) (set (match_dup 0) (match_dup 2))] "")

(define_expand "truncxfdf2" [(parallel [(set (match_operand:DF 0 "nonimmediate_operand" "") (float_truncate:DF (match_operand:XF 1 "register_operand" ""))) (clobber (match_dup 2))])] "TARGET_80387" "operands[2] = assign_386_stack_local (DFmode, 0);")

(define_insn "*truncxfdf2_1" [(set (match_operand:DF 0 "nonimmediate_operand" "=m,?f#rY,?r#fY,?Y#rf") (float_truncate:DF (match_operand:XF 1 "register_operand" "f,f,f,f"))) (clobber (match_operand:DF 2 "memory_operand" "=X,m,m,m"))] "TARGET_80387" { switch (which_alternative) { case 0: if (find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) return "fstp%z0\t%y0"; else return "fst%z0\t%y0"; default: abort(); } abort (); } [(set_attr "type" "fmov,multi,multi,multi") (set_attr "mode" "DF")])

(define_insn "*truncxfdf2_2" [(set (match_operand:DF 0 "memory_operand" "=m") (float_truncate:DF (match_operand:XF 1 "register_operand" "f")))] "TARGET_80387" { if (find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) return "fstp%z0\t%y0"; else return "fst%z0\t%y0"; } [(set_attr "type" "fmov") (set_attr "mode" "DF")])

(define_split [(set (match_operand:DF 0 "memory_operand" "") (float_truncate:DF (match_operand:XF 1 "register_operand" ""))) (clobber (match_operand:DF 2 "memory_operand" ""))] "TARGET_80387" [(set (match_dup 0) (float_truncate:DF (match_dup 1)))] "")

(define_split [(set (match_operand:DF 0 "register_operand" "") (float_truncate:DF (match_operand:XF 1 "register_operand" ""))) (clobber (match_operand:DF 2 "memory_operand" ""))] "TARGET_80387 && reload_completed" [(set (match_dup 2) (float_truncate:DF (match_dup 1))) (set (match_dup 0) (match_dup 2))] "")

;; %%% Break up all these bad boys.

;; Signed conversion to DImode.

(define_expand "fix_truncxfdi2" [(set (match_operand:DI 0 "nonimmediate_operand" "") (fix:DI (match_operand:XF 1 "register_operand" "")))] "TARGET_80387" "")

(define_expand "fix_truncdfdi2" [(set (match_operand:DI 0 "nonimmediate_operand" "") (fix:DI (match_operand:DF 1 "register_operand" "")))] "TARGET_80387 || (TARGET_SSE2 && TARGET_64BIT)" { if (TARGET_64BIT && TARGET_SSE2) { rtx out = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (DImode); emit_insn (gen_fix_truncdfdi_sse (out, operands[1])); if (out != operands[0]) emit_move_insn (operands[0], out); DONE; } })

(define_expand "fix_truncsfdi2" [(set (match_operand:DI 0 "nonimmediate_operand" "") (fix:DI (match_operand:SF 1 "register_operand" "")))] "TARGET_80387 || (TARGET_SSE && TARGET_64BIT)" { if (TARGET_SSE && TARGET_64BIT) { rtx out = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (DImode); emit_insn (gen_fix_truncsfdi_sse (out, operands[1])); if (out != operands[0]) emit_move_insn (operands[0], out); DONE; } })

;; See the comments in i386.h near OPTIMIZE_MODE_SWITCHING for the description ;; of the machinery. (define_insn_and_split "*fix_truncdi_1" [(set (match_operand:DI 0 "nonimmediate_operand" "=m,?r") (fix:DI (match_operand 1 "register_operand" "f,f")))] "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1])) && !reload_completed && !reload_in_progress && (!SSE_FLOAT_MODE_P (GET_MODE (operands[1])) || !TARGET_64BIT)" "#" "&& 1" [(const_int 0)] { ix86_optimize_mode_switching = 1; operands[2] = assign_386_stack_local (HImode, 1); operands[3] = assign_386_stack_local (HImode, 2); if (memory_operand (operands[0], VOIDmode)) emit_insn (gen_fix_truncdi_memory (operands[0], operands[1], operands[2], operands[3])); else { operands[4] = assign_386_stack_local (DImode, 0); emit_insn (gen_fix_truncdi_nomemory (operands[0], operands[1], operands[2], operands[3], operands[4])); } DONE; } [(set_attr "type" "fistp") (set_attr "mode" "DI")])

(define_insn "fix_truncdi_nomemory" [(set (match_operand:DI 0 "nonimmediate_operand" "=m,?r") (fix:DI (match_operand 1 "register_operand" "f,f"))) (use (match_operand:HI 2 "memory_operand" "m,m")) (use (match_operand:HI 3 "memory_operand" "m,m")) (clobber (match_operand:DI 4 "memory_operand" "=m,m")) (clobber (match_scratch:DF 5 "=&1f,&1f"))] "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1])) && (!SSE_FLOAT_MODE_P (GET_MODE (operands[1])) || !TARGET_64BIT)" "#" [(set_attr "type" "fistp") (set_attr "mode" "DI")])

(define_insn "fix_truncdi_memory" [(set (match_operand:DI 0 "memory_operand" "=m") (fix:DI (match_operand 1 "register_operand" "f"))) (use (match_operand:HI 2 "memory_operand" "m")) (use (match_operand:HI 3 "memory_operand" "m")) (clobber (match_scratch:DF 4 "=&1f"))] "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1])) && (!SSE_FLOAT_MODE_P (GET_MODE (operands[1])) || !TARGET_64BIT)" "* operands[5] = operands[4]; return output_fix_trunc (insn, operands);" [(set_attr "type" "fistp") (set_attr "mode" "DI")])

(define_split [(set (match_operand:DI 0 "register_operand" "") (fix:DI (match_operand 1 "register_operand" ""))) (use (match_operand:HI 2 "memory_operand" "")) (use (match_operand:HI 3 "memory_operand" "")) (clobber (match_operand:DI 4 "memory_operand" "")) (clobber (match_scratch 5 ""))] "reload_completed" [(parallel [(set (match_dup 4) (fix:DI (match_dup 1))) (use (match_dup 2)) (use (match_dup 3)) (clobber (match_dup 5))]) (set (match_dup 0) (match_dup 4))] "")

(define_split [(set (match_operand:DI 0 "memory_operand" "") (fix:DI (match_operand 1 "register_operand" ""))) (use (match_operand:HI 2 "memory_operand" "")) (use (match_operand:HI 3 "memory_operand" "")) (clobber (match_operand:DI 4 "memory_operand" "")) (clobber (match_scratch 5 ""))] "reload_completed" [(parallel [(set (match_dup 0) (fix:DI (match_dup 1))) (use (match_dup 2)) (use (match_dup 3)) (clobber (match_dup 5))])] "")

;; When SSE available, it is always faster to use it! (define_insn "fix_truncsfdi_sse" [(set (match_operand:DI 0 "register_operand" "=r,r") (fix:DI (match_operand:SF 1 "nonimmediate_operand" "x,xm")))] "TARGET_64BIT && TARGET_SSE" "cvttss2si{q}\t{%1, %0|%0, %1}" [(set_attr "type" "sseicvt") (set_attr "mode" "SF") (set_attr "athlon_decode" "double,vector")])

;; Avoid vector decoded form of the instruction. (define_peephole2 [(match_scratch:SF 2 "x") (set (match_operand:DI 0 "register_operand" "") (fix:DI (match_operand:SF 1 "memory_operand" "")))] "TARGET_K8 && !optimize_size" [(set (match_dup 2) (match_dup 1)) (set (match_dup 0) (fix:DI (match_dup 2)))] "")

(define_insn "fix_truncdfdi_sse" [(set (match_operand:DI 0 "register_operand" "=r,r") (fix:DI (match_operand:DF 1 "nonimmediate_operand" "Y,Ym")))] "TARGET_64BIT && TARGET_SSE2" "cvttsd2si{q}\t{%1, %0|%0, %1}" [(set_attr "type" "sseicvt,sseicvt") (set_attr "mode" "DF") (set_attr "athlon_decode" "double,vector")])

;; Avoid vector decoded form of the instruction. (define_peephole2 [(match_scratch:DF 2 "Y") (set (match_operand:DI 0 "register_operand" "") (fix:DI (match_operand:DF 1 "memory_operand" "")))] "TARGET_K8 && !optimize_size" [(set (match_dup 2) (match_dup 1)) (set (match_dup 0) (fix:DI (match_dup 2)))] "")

;; Signed conversion to SImode.

(define_expand "fix_truncxfsi2" [(set (match_operand:SI 0 "nonimmediate_operand" "") (fix:SI (match_operand:XF 1 "register_operand" "")))] "TARGET_80387" "")

(define_expand "fix_truncdfsi2" [(set (match_operand:SI 0 "nonimmediate_operand" "") (fix:SI (match_operand:DF 1 "register_operand" "")))] "TARGET_80387 || TARGET_SSE2" { if (TARGET_SSE2) { rtx out = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (SImode); emit_insn (gen_fix_truncdfsi_sse (out, operands[1])); if (out != operands[0]) emit_move_insn (operands[0], out); DONE; } })

(define_expand "fix_truncsfsi2" [(set (match_operand:SI 0 "nonimmediate_operand" "") (fix:SI (match_operand:SF 1 "register_operand" "")))] "TARGET_80387 || TARGET_SSE" { if (TARGET_SSE) { rtx out = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (SImode); emit_insn (gen_fix_truncsfsi_sse (out, operands[1])); if (out != operands[0]) emit_move_insn (operands[0], out); DONE; } })

;; See the comments in i386.h near OPTIMIZE_MODE_SWITCHING for the description ;; of the machinery. (define_insn_and_split "*fix_truncsi_1" [(set (match_operand:SI 0 "nonimmediate_operand" "=m,?r") (fix:SI (match_operand 1 "register_operand" "f,f")))] "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1])) && !reload_completed && !reload_in_progress && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))" "#" "&& 1" [(const_int 0)] { ix86_optimize_mode_switching = 1; operands[2] = assign_386_stack_local (HImode, 1); operands[3] = assign_386_stack_local (HImode, 2); if (memory_operand (operands[0], VOIDmode)) emit_insn (gen_fix_truncsi_memory (operands[0], operands[1], operands[2], operands[3])); else { operands[4] = assign_386_stack_local (SImode, 0); emit_insn (gen_fix_truncsi_nomemory (operands[0], operands[1], operands[2], operands[3], operands[4])); } DONE; } [(set_attr "type" "fistp") (set_attr "mode" "SI")])

(define_insn "fix_truncsi_nomemory" [(set (match_operand:SI 0 "nonimmediate_operand" "=m,?r") (fix:SI (match_operand 1 "register_operand" "f,f"))) (use (match_operand:HI 2 "memory_operand" "m,m")) (use (match_operand:HI 3 "memory_operand" "m,m")) (clobber (match_operand:SI 4 "memory_operand" "=m,m"))] "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1])) && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))" "#" [(set_attr "type" "fistp") (set_attr "mode" "SI")])

(define_insn "fix_truncsi_memory" [(set (match_operand:SI 0 "memory_operand" "=m") (fix:SI (match_operand 1 "register_operand" "f"))) (use (match_operand:HI 2 "memory_operand" "m")) (use (match_operand:HI 3 "memory_operand" "m"))] "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1])) && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))" "* return output_fix_trunc (insn, operands);" [(set_attr "type" "fistp") (set_attr "mode" "SI")])

;; When SSE available, it is always faster to use it! (define_insn "fix_truncsfsi_sse" [(set (match_operand:SI 0 "register_operand" "=r,r") (fix:SI (match_operand:SF 1 "nonimmediate_operand" "x,xm")))] "TARGET_SSE" "cvttss2si\t{%1, %0|%0, %1}" [(set_attr "type" "sseicvt") (set_attr "mode" "DF") (set_attr "athlon_decode" "double,vector")])

;; Avoid vector decoded form of the instruction. (define_peephole2 [(match_scratch:SF 2 "x") (set (match_operand:SI 0 "register_operand" "") (fix:SI (match_operand:SF 1 "memory_operand" "")))] "TARGET_K8 && !optimize_size" [(set (match_dup 2) (match_dup 1)) (set (match_dup 0) (fix:SI (match_dup 2)))] "")

(define_insn "fix_truncdfsi_sse" [(set (match_operand:SI 0 "register_operand" "=r,r") (fix:SI (match_operand:DF 1 "nonimmediate_operand" "Y,Ym")))] "TARGET_SSE2" "cvttsd2si\t{%1, %0|%0, %1}" [(set_attr "type" "sseicvt") (set_attr "mode" "DF") (set_attr "athlon_decode" "double,vector")])

;; Avoid vector decoded form of the instruction. (define_peephole2 [(match_scratch:DF 2 "Y") (set (match_operand:SI 0 "register_operand" "") (fix:SI (match_operand:DF 1 "memory_operand" "")))] "TARGET_K8 && !optimize_size" [(set (match_dup 2) (match_dup 1)) (set (match_dup 0) (fix:SI (match_dup 2)))] "")

(define_split [(set (match_operand:SI 0 "register_operand" "") (fix:SI (match_operand 1 "register_operand" ""))) (use (match_operand:HI 2 "memory_operand" "")) (use (match_operand:HI 3 "memory_operand" "")) (clobber (match_operand:SI 4 "memory_operand" ""))] "reload_completed" [(parallel [(set (match_dup 4) (fix:SI (match_dup 1))) (use (match_dup 2)) (use (match_dup 3))]) (set (match_dup 0) (match_dup 4))] "")

(define_split [(set (match_operand:SI 0 "memory_operand" "") (fix:SI (match_operand 1 "register_operand" ""))) (use (match_operand:HI 2 "memory_operand" "")) (use (match_operand:HI 3 "memory_operand" "")) (clobber (match_operand:SI 4 "memory_operand" ""))] "reload_completed" [(parallel [(set (match_dup 0) (fix:SI (match_dup 1))) (use (match_dup 2)) (use (match_dup 3))])] "")

;; Signed conversion to HImode.

(define_expand "fix_truncxfhi2" [(set (match_operand:HI 0 "nonimmediate_operand" "") (fix:HI (match_operand:XF 1 "register_operand" "")))] "TARGET_80387" "")

(define_expand "fix_truncdfhi2" [(set (match_operand:HI 0 "nonimmediate_operand" "") (fix:HI (match_operand:DF 1 "register_operand" "")))] "TARGET_80387 && !TARGET_SSE2" "")

(define_expand "fix_truncsfhi2" [(set (match_operand:HI 0 "nonimmediate_operand" "") (fix:HI (match_operand:SF 1 "register_operand" "")))] "TARGET_80387 && !TARGET_SSE" "")

;; See the comments in i386.h near OPTIMIZE_MODE_SWITCHING for the description ;; of the machinery. (define_insn_and_split "*fix_trunchi_1" [(set (match_operand:HI 0 "nonimmediate_operand" "=m,?r") (fix:HI (match_operand 1 "register_operand" "f,f")))] "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1])) && !reload_completed && !reload_in_progress && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))" "#" "" [(const_int 0)] { ix86_optimize_mode_switching = 1; operands[2] = assign_386_stack_local (HImode, 1); operands[3] = assign_386_stack_local (HImode, 2); if (memory_operand (operands[0], VOIDmode)) emit_insn (gen_fix_trunchi_memory (operands[0], operands[1], operands[2], operands[3])); else { operands[4] = assign_386_stack_local (HImode, 0); emit_insn (gen_fix_trunchi_nomemory (operands[0], operands[1], operands[2], operands[3], operands[4])); } DONE; } [(set_attr "type" "fistp") (set_attr "mode" "HI")])

(define_insn "fix_trunchi_nomemory" [(set (match_operand:HI 0 "nonimmediate_operand" "=m,?r") (fix:HI (match_operand 1 "register_operand" "f,f"))) (use (match_operand:HI 2 "memory_operand" "m,m")) (use (match_operand:HI 3 "memory_operand" "m,m")) (clobber (match_operand:HI 4 "memory_operand" "=m,m"))] "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1])) && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))" "#" [(set_attr "type" "fistp") (set_attr "mode" "HI")])

(define_insn "fix_trunchi_memory" [(set (match_operand:HI 0 "memory_operand" "=m") (fix:HI (match_operand 1 "register_operand" "f"))) (use (match_operand:HI 2 "memory_operand" "m")) (use (match_operand:HI 3 "memory_operand" "m"))] "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1])) && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))" "* return output_fix_trunc (insn, operands);" [(set_attr "type" "fistp") (set_attr "mode" "HI")])

(define_split [(set (match_operand:HI 0 "memory_operand" "") (fix:HI (match_operand 1 "register_operand" ""))) (use (match_operand:HI 2 "memory_operand" "")) (use (match_operand:HI 3 "memory_operand" "")) (clobber (match_operand:HI 4 "memory_operand" ""))] "reload_completed" [(parallel [(set (match_dup 0) (fix:HI (match_dup 1))) (use (match_dup 2)) (use (match_dup 3))])] "")

(define_split [(set (match_operand:HI 0 "register_operand" "") (fix:HI (match_operand 1 "register_operand" ""))) (use (match_operand:HI 2 "memory_operand" "")) (use (match_operand:HI 3 "memory_operand" "")) (clobber (match_operand:HI 4 "memory_operand" ""))] "reload_completed" [(parallel [(set (match_dup 4) (fix:HI (match_dup 1))) (use (match_dup 2)) (use (match_dup 3)) (clobber (match_dup 4))]) (set (match_dup 0) (match_dup 4))] "")

;; %% Not used yet. (define_insn "x86_fnstcw_1" [(set (match_operand:HI 0 "memory_operand" "=m") (unspec:HI [(reg:HI 18)] UNSPEC_FSTCW))] "TARGET_80387" "fnstcw\t%0" [(set_attr "length" "2") (set_attr "mode" "HI") (set_attr "unit" "i387") (set_attr "ppro_uops" "few")])

(define_insn "x86_fldcw_1" [(set (reg:HI 18) (unspec:HI [(match_operand:HI 0 "memory_operand" "m")] UNSPEC_FLDCW))] "TARGET_80387" "fldcw\t%0" [(set_attr "length" "2") (set_attr "mode" "HI") (set_attr "unit" "i387") (set_attr "athlon_decode" "vector") (set_attr "ppro_uops" "few")]) ;; Conversion between fixed point and floating point.

;; Even though we only accept memory inputs, the backend really ;; wants to be able to do this between registers.

(define_expand "floathisf2" [(set (match_operand:SF 0 "register_operand" "") (float:SF (match_operand:HI 1 "nonimmediate_operand" "")))] "TARGET_SSE || TARGET_80387" { if (TARGET_SSE && TARGET_SSE_MATH) { emit_insn (gen_floatsisf2 (operands[0], convert_to_mode (SImode, operands[1], 0))); DONE; } })

(define_insn "*floathisf2_1" [(set (match_operand:SF 0 "register_operand" "=f,f") (float:SF (match_operand:HI 1 "nonimmediate_operand" "m,r")))] "TARGET_80387 && (!TARGET_SSE || !TARGET_SSE_MATH)" "@ fild%z1\t%1 #" [(set_attr "type" "fmov,multi") (set_attr "mode" "SF") (set_attr "fp_int_src" "true")])

(define_expand "floatsisf2" [(set (match_operand:SF 0 "register_operand" "") (float:SF (match_operand:SI 1 "nonimmediate_operand" "")))] "TARGET_SSE || TARGET_80387" "")

(define_insn "*floatsisf2_i387" [(set (match_operand:SF 0 "register_operand" "=f#x,?f#x,x#f,x#f") (float:SF (match_operand:SI 1 "nonimmediate_operand" "m,r,r,mr")))] "TARGET_80387 && (!TARGET_SSE || TARGET_MIX_SSE_I387)" "@ fild%z1\t%1

cvtsi2ss\t{%1, %0|%0, %1} cvtsi2ss\t{%1, %0|%0, %1}" [(set_attr "type" "fmov,multi,sseicvt,sseicvt") (set_attr "mode" "SF") (set_attr "athlon_decode" ",,vector,double") (set_attr "fp_int_src" "true")])

(define_insn "*floatsisf2_sse" [(set (match_operand:SF 0 "register_operand" "=x,x") (float:SF (match_operand:SI 1 "nonimmediate_operand" "r,mr")))] "TARGET_SSE" "cvtsi2ss\t{%1, %0|%0, %1}" [(set_attr "type" "sseicvt") (set_attr "mode" "SF") (set_attr "athlon_decode" "vector,double") (set_attr "fp_int_src" "true")])

; Avoid possible reformatting penalty on the destination by first ; zeroing it out (define_split [(set (match_operand:SF 0 "register_operand" "") (float:SF (match_operand:SI 1 "nonimmediate_operand" "")))] "TARGET_80387 && reload_completed && TARGET_SSE_PARTIAL_REGS && SSE_REG_P (operands[0])" [(const_int 0)] { rtx dest; dest = simplify_gen_subreg (V4SFmode, operands[0], SFmode, 0); emit_insn (gen_sse_clrv4sf (dest, CONST0_RTX (V4SFmode))); emit_insn (gen_cvtsi2ss (dest, dest, operands[1])); DONE; })

(define_expand "floatdisf2" [(set (match_operand:SF 0 "register_operand" "") (float:SF (match_operand:DI 1 "nonimmediate_operand" "")))] "(TARGET_64BIT && TARGET_SSE) || TARGET_80387" "")

(define_insn "*floatdisf2_i387_only" [(set (match_operand:SF 0 "register_operand" "=f,?f") (float:SF (match_operand:DI 1 "nonimmediate_operand" "m,r")))] "TARGET_80387 && (!TARGET_SSE || !TARGET_64BIT || TARGET_MIX_SSE_I387)" "@ fild%z1\t%1 #" [(set_attr "type" "fmov,multi") (set_attr "mode" "SF") (set_attr "fp_int_src" "true")])

(define_insn "*floatdisf2_i387" [(set (match_operand:SF 0 "register_operand" "=f#x,?f#x,x#f,x#f") (float:SF (match_operand:DI 1 "nonimmediate_operand" "m,r,r,mr")))] "TARGET_64BIT && TARGET_80387 && (!TARGET_SSE || TARGET_MIX_SSE_I387)" "@ fild%z1\t%1

cvtsi2ss{q}\t{%1, %0|%0, %1} cvtsi2ss{q}\t{%1, %0|%0, %1}" [(set_attr "type" "fmov,multi,sseicvt,sseicvt") (set_attr "mode" "SF") (set_attr "athlon_decode" ",,vector,double") (set_attr "fp_int_src" "true")])

(define_insn "*floatdisf2_sse" [(set (match_operand:SF 0 "register_operand" "=x,x") (float:SF (match_operand:DI 1 "nonimmediate_operand" "r,mr")))] "TARGET_64BIT && TARGET_SSE" "cvtsi2ss{q}\t{%1, %0|%0, %1}" [(set_attr "type" "sseicvt") (set_attr "mode" "SF") (set_attr "athlon_decode" "vector,double") (set_attr "fp_int_src" "true")])

; Avoid possible reformatting penalty on the destination by first ; zeroing it out (define_split [(set (match_operand:SF 0 "register_operand" "") (float:SF (match_operand:DI 1 "nonimmediate_operand" "")))] "TARGET_80387 && reload_completed && TARGET_SSE_PARTIAL_REGS && SSE_REG_P (operands[0])" [(const_int 0)] { rtx dest; dest = simplify_gen_subreg (V4SFmode, operands[0], SFmode, 0); emit_insn (gen_sse_clrv4sf (dest, CONST0_RTX (V4SFmode))); emit_insn (gen_cvtsi2ssq (dest, dest, operands[1])); DONE; })

(define_expand "floathidf2" [(set (match_operand:DF 0 "register_operand" "") (float:DF (match_operand:HI 1 "nonimmediate_operand" "")))] "TARGET_SSE2 || TARGET_80387" { if (TARGET_SSE && TARGET_SSE_MATH) { emit_insn (gen_floatsidf2 (operands[0], convert_to_mode (SImode, operands[1], 0))); DONE; } })

(define_insn "*floathidf2_1" [(set (match_operand:DF 0 "register_operand" "=f,f") (float:DF (match_operand:HI 1 "nonimmediate_operand" "m,r")))] "TARGET_80387 && (!TARGET_SSE2 || !TARGET_SSE_MATH)" "@ fild%z1\t%1 #" [(set_attr "type" "fmov,multi") (set_attr "mode" "DF") (set_attr "fp_int_src" "true")])

(define_expand "floatsidf2" [(set (match_operand:DF 0 "register_operand" "") (float:DF (match_operand:SI 1 "nonimmediate_operand" "")))] "TARGET_80387 || TARGET_SSE2" "")

(define_insn "*floatsidf2_i387" [(set (match_operand:DF 0 "register_operand" "=f#Y,?f#Y,Y#f,Y#f") (float:DF (match_operand:SI 1 "nonimmediate_operand" "m,r,r,mr")))] "TARGET_80387 && (!TARGET_SSE2 || TARGET_MIX_SSE_I387)" "@ fild%z1\t%1

cvtsi2sd\t{%1, %0|%0, %1} cvtsi2sd\t{%1, %0|%0, %1}" [(set_attr "type" "fmov,multi,sseicvt,sseicvt") (set_attr "mode" "DF") (set_attr "athlon_decode" ",,double,direct") (set_attr "fp_int_src" "true")])

(define_insn "*floatsidf2_sse" [(set (match_operand:DF 0 "register_operand" "=Y,Y") (float:DF (match_operand:SI 1 "nonimmediate_operand" "r,mr")))] "TARGET_SSE2" "cvtsi2sd\t{%1, %0|%0, %1}" [(set_attr "type" "sseicvt") (set_attr "mode" "DF") (set_attr "athlon_decode" "double,direct") (set_attr "fp_int_src" "true")])

(define_expand "floatdidf2" [(set (match_operand:DF 0 "register_operand" "") (float:DF (match_operand:DI 1 "nonimmediate_operand" "")))] "(TARGET_64BIT && TARGET_SSE2) || TARGET_80387" "")

(define_insn "*floatdidf2_i387_only" [(set (match_operand:DF 0 "register_operand" "=f,?f") (float:DF (match_operand:DI 1 "nonimmediate_operand" "m,r")))] "TARGET_80387 && (!TARGET_SSE2 || !TARGET_64BIT)" "@ fild%z1\t%1 #" [(set_attr "type" "fmov,multi") (set_attr "mode" "DF") (set_attr "fp_int_src" "true")])

(define_insn "*floatdidf2_i387" [(set (match_operand:DF 0 "register_operand" "=f#Y,?f#Y,Y#f,Y#f") (float:DF (match_operand:DI 1 "nonimmediate_operand" "m,r,r,mr")))] "TARGET_64BIT && TARGET_80387 && (!TARGET_SSE2 || TARGET_MIX_SSE_I387)" "@ fild%z1\t%1

cvtsi2sd{q}\t{%1, %0|%0, %1} cvtsi2sd{q}\t{%1, %0|%0, %1}" [(set_attr "type" "fmov,multi,sseicvt,sseicvt") (set_attr "mode" "DF") (set_attr "athlon_decode" ",,double,direct") (set_attr "fp_int_src" "true")])

(define_insn "*floatdidf2_sse" [(set (match_operand:DF 0 "register_operand" "=Y,Y") (float:DF (match_operand:DI 1 "nonimmediate_operand" "r,mr")))] "TARGET_SSE2" "cvtsi2sd{q}\t{%1, %0|%0, %1}" [(set_attr "type" "sseicvt") (set_attr "mode" "DF") (set_attr "athlon_decode" "double,direct") (set_attr "fp_int_src" "true")])

(define_insn "floathixf2" [(set (match_operand:XF 0 "register_operand" "=f,f") (float:XF (match_operand:HI 1 "nonimmediate_operand" "m,r")))] "TARGET_80387" "@ fild%z1\t%1 #" [(set_attr "type" "fmov,multi") (set_attr "mode" "XF") (set_attr "fp_int_src" "true")])

(define_insn "floatsixf2" [(set (match_operand:XF 0 "register_operand" "=f,f") (float:XF (match_operand:SI 1 "nonimmediate_operand" "m,r")))] "TARGET_80387" "@ fild%z1\t%1 #" [(set_attr "type" "fmov,multi") (set_attr "mode" "XF") (set_attr "fp_int_src" "true")])

(define_insn "floatdixf2" [(set (match_operand:XF 0 "register_operand" "=f,f") (float:XF (match_operand:DI 1 "nonimmediate_operand" "m,r")))] "TARGET_80387" "@ fild%z1\t%1 #" [(set_attr "type" "fmov,multi") (set_attr "mode" "XF") (set_attr "fp_int_src" "true")])

;; %%% Kill these when reload knows how to do it. (define_split [(set (match_operand 0 "fp_register_operand" "") (float (match_operand 1 "register_operand" "")))] "reload_completed && FLOAT_MODE_P (GET_MODE (operands[0]))" [(const_int 0)] { operands[2] = ix86_force_to_memory (GET_MODE (operands[1]), operands[1]); operands[2] = gen_rtx_FLOAT (GET_MODE (operands[0]), operands[2]); emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[2])); ix86_free_from_memory (GET_MODE (operands[1])); DONE; })

(define_expand "floatunssisf2" [(use (match_operand:SF 0 "register_operand" "")) (use (match_operand:SI 1 "register_operand" ""))] "TARGET_SSE && TARGET_SSE_MATH && !TARGET_64BIT" "x86_emit_floatuns (operands); DONE;")

(define_expand "floatunsdisf2" [(use (match_operand:SF 0 "register_operand" "")) (use (match_operand:DI 1 "register_operand" ""))] "TARGET_SSE && TARGET_SSE_MATH && TARGET_64BIT" "x86_emit_floatuns (operands); DONE;")

(define_expand "floatunsdidf2" [(use (match_operand:DF 0 "register_operand" "")) (use (match_operand:DI 1 "register_operand" ""))] "TARGET_SSE2 && TARGET_SSE_MATH && TARGET_64BIT" "x86_emit_floatuns (operands); DONE;") ;; SSE extract/set expanders

(define_expand "vec_setv2df" [(match_operand:V2DF 0 "register_operand" "") (match_operand:DF 1 "register_operand" "") (match_operand 2 "const_int_operand" "")] "TARGET_SSE2" { switch (INTVAL (operands[2])) { case 0: emit_insn (gen_sse2_movsd (operands[0], operands[0], simplify_gen_subreg (V2DFmode, operands[1], DFmode, 0))); break; case 1: { rtx op1 = simplify_gen_subreg (V2DFmode, operands[1], DFmode, 0);

emit_insn (gen_sse2_unpcklpd (operands[0], operands[0], op1));
  }
  break;
default:
  abort ();
}

DONE; })

(define_expand "vec_extractv2df" [(match_operand:DF 0 "register_operand" "") (match_operand:V2DF 1 "register_operand" "") (match_operand 2 "const_int_operand" "")] "TARGET_SSE2" { switch (INTVAL (operands[2])) { case 0: emit_move_insn (operands[0], gen_lowpart (DFmode, operands[1])); break; case 1: { rtx dest = simplify_gen_subreg (V2DFmode, operands[0], DFmode, 0);

emit_insn (gen_sse2_unpckhpd (dest, operands[1], operands[1]));
  }
  break;
default:
  abort ();
}

DONE; })

(define_expand "vec_initv2df" [(match_operand:V2DF 0 "register_operand" "") (match_operand 1 "" "")] "TARGET_SSE2" { ix86_expand_vector_init (operands[0], operands[1]); DONE; })

(define_expand "vec_setv4sf" [(match_operand:V4SF 0 "register_operand" "") (match_operand:SF 1 "register_operand" "") (match_operand 2 "const_int_operand" "")] "TARGET_SSE" { switch (INTVAL (operands[2])) { case 0: emit_insn (gen_sse_movss (operands[0], operands[0], simplify_gen_subreg (V4SFmode, operands[1], SFmode, 0))); break; case 1: { rtx op1 = simplify_gen_subreg (V4SFmode, operands[1], SFmode, 0); rtx tmp = gen_reg_rtx (V4SFmode);

    emit_move_insn (tmp, operands[0]);
emit_insn (gen_sse_unpcklps (operands[0], operands[0], operands[0]));
emit_insn (gen_sse_movss (operands[0], operands[0], op1));
    emit_insn (gen_sse_shufps (operands[0], operands[0], tmp,
                               GEN_INT (1 + (0<<2) + (2<<4) + (3<<6))));
  }
case 2:
  {
    rtx op1 = simplify_gen_subreg (V4SFmode, operands[1], SFmode, 0);
    rtx tmp = gen_reg_rtx (V4SFmode);

    emit_move_insn (tmp, operands[0]);
    emit_insn (gen_sse_movss (tmp, tmp, op1));
    emit_insn (gen_sse_shufps (operands[0], operands[0], tmp,
                               GEN_INT (0 + (1<<2) + (0<<4) + (3<<6))));
  }
  break;
case 3:
  {
    rtx op1 = simplify_gen_subreg (V4SFmode, operands[1], SFmode, 0);
    rtx tmp = gen_reg_rtx (V4SFmode);

    emit_move_insn (tmp, operands[0]);
    emit_insn (gen_sse_movss (tmp, tmp, op1));
    emit_insn (gen_sse_shufps (operands[0], operands[0], tmp,
                               GEN_INT (0 + (1<<2) + (2<<4) + (0<<6))));
  }
  break;
default:
  abort ();
}

DONE; })

(define_expand "vec_extractv4sf" [(match_operand:SF 0 "register_operand" "") (match_operand:V4SF 1 "register_operand" "") (match_operand 2 "const_int_operand" "")] "TARGET_SSE" { switch (INTVAL (operands[2])) { case 0: emit_move_insn (operands[0], gen_lowpart (SFmode, operands[1])); break; case 1: { rtx op0 = simplify_gen_subreg (V4SFmode, operands[1], SFmode, 0); rtx tmp = gen_reg_rtx (V4SFmode);

    emit_move_insn (tmp, operands[1]);
    emit_insn (gen_sse_shufps (op0, tmp, tmp,
                               GEN_INT (1)));
  }
case 2:
  {
rtx op0 = simplify_gen_subreg (V4SFmode, operands[1], SFmode, 0);
rtx tmp = gen_reg_rtx (V4SFmode);

    emit_move_insn (tmp, operands[1]);
    emit_insn (gen_sse_unpckhps (op0, tmp, tmp));
  }
case 3:
  {
rtx op0 = simplify_gen_subreg (V4SFmode, operands[1], SFmode, 0);
rtx tmp = gen_reg_rtx (V4SFmode);

    emit_move_insn (tmp, operands[1]);
    emit_insn (gen_sse_shufps (op0, tmp, tmp,
                               GEN_INT (3)));
  }
default:
  abort ();
}

DONE; })

(define_expand "vec_initv4sf" [(match_operand:V4SF 0 "register_operand" "") (match_operand 1 "" "")] "TARGET_SSE" { ix86_expand_vector_init (operands[0], operands[1]); DONE; }) ;; Add instructions

;; %%% splits for addsidi3 ; [(set (match_operand:DI 0 "nonimmediate_operand" "") ; (plus:DI (match_operand:DI 1 "general_operand" "") ; (zero_extend:DI (match_operand:SI 2 "general_operand" ""))))]

(define_expand "adddi3" [(set (match_operand:DI 0 "nonimmediate_operand" "") (plus:DI (match_operand:DI 1 "nonimmediate_operand" "") (match_operand:DI 2 "x86_64_general_operand" ""))) (clobber (reg:CC 17))] "" "ix86_expand_binary_operator (PLUS, DImode, operands); DONE;")

(define_insn "*adddi3_1" [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o") (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") (match_operand:DI 2 "general_operand" "roiF,riF"))) (clobber (reg:CC 17))] "!TARGET_64BIT && ix86_binary_operator_ok (PLUS, DImode, operands)" "#")

(define_split [(set (match_operand:DI 0 "nonimmediate_operand" "") (plus:DI (match_operand:DI 1 "nonimmediate_operand" "") (match_operand:DI 2 "general_operand" ""))) (clobber (reg:CC 17))] "!TARGET_64BIT && reload_completed" [(parallel [(set (reg:CC 17) (unspec:CC [(match_dup 1) (match_dup 2)] UNSPEC_ADD_CARRY)) (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]) (parallel [(set (match_dup 3) (plus:SI (plus:SI (ltu:SI (reg:CC 17) (const_int 0)) (match_dup 4)) (match_dup 5))) (clobber (reg:CC 17))])] "split_di (operands+0, 1, operands+0, operands+3); split_di (operands+1, 1, operands+1, operands+4); split_di (operands+2, 1, operands+2, operands+5);")

(define_insn "adddi3_carry_rex64" [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r") (plus:DI (plus:DI (match_operand:DI 3 "ix86_carry_flag_operator" "") (match_operand:DI 1 "nonimmediate_operand" "%0,0")) (match_operand:DI 2 "x86_64_general_operand" "re,rm"))) (clobber (reg:CC 17))] "TARGET_64BIT && ix86_binary_operator_ok (PLUS, DImode, operands)" "adc{q}\t{%2, %0|%0, %2}" [(set_attr "type" "alu") (set_attr "pent_pair" "pu") (set_attr "mode" "DI") (set_attr "ppro_uops" "few")])

(define_insn "*adddi3_cc_rex64" [(set (reg:CC 17) (unspec:CC [(match_operand:DI 1 "nonimmediate_operand" "%0,0") (match_operand:DI 2 "x86_64_general_operand" "re,rm")] UNSPEC_ADD_CARRY)) (set (match_operand:DI 0 "nonimmediate_operand" "=rm,r") (plus:DI (match_dup 1) (match_dup 2)))] "TARGET_64BIT && ix86_binary_operator_ok (PLUS, DImode, operands)" "add{q}\t{%2, %0|%0, %2}" [(set_attr "type" "alu") (set_attr "mode" "DI")])

(define_insn "addqi3_carry" [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q") (plus:QI (plus:QI (match_operand:QI 3 "ix86_carry_flag_operator" "") (match_operand:QI 1 "nonimmediate_operand" "%0,0")) (match_operand:QI 2 "general_operand" "qi,qm"))) (clobber (reg:CC 17))] "ix86_binary_operator_ok (PLUS, QImode, operands)" "adc{b}\t{%2, %0|%0, %2}" [(set_attr "type" "alu") (set_attr "pent_pair" "pu") (set_attr "mode" "QI") (set_attr "ppro_uops" "few")])

(define_insn "addhi3_carry" [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r") (plus:HI (plus:HI (match_operand:HI 3 "ix86_carry_flag_operator" "") (match_operand:HI 1 "nonimmediate_operand" "%0,0")) (match_operand:HI 2 "general_operand" "ri,rm"))) (clobber (reg:CC 17))] "ix86_binary_operator_ok (PLUS, HImode, operands)" "adc{w}\t{%2, %0|%0, %2}" [(set_attr "type" "alu") (set_attr "pent_pair" "pu") (set_attr "mode" "HI") (set_attr "ppro_uops" "few")])

(define_insn "addsi3_carry" [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r") (plus:SI (plus:SI (match_operand:SI 3 "ix86_carry_flag_operator" "") (match_operand:SI 1 "nonimmediate_operand" "%0,0")) (match_operand:SI 2 "general_operand" "ri,rm"))) (clobber (reg:CC 17))] "ix86_binary_operator_ok (PLUS, SImode, operands)" "adc{l}\t{%2, %0|%0, %2}" [(set_attr "type" "alu") (set_attr "pent_pair" "pu") (set_attr "mode" "SI") (set_attr "ppro_uops" "few")])

(define_insn "*addsi3_carry_zext" [(set (match_operand:DI 0 "register_operand" "=r") (zero_extend:DI (plus:SI (plus:SI (match_operand:SI 3 "ix86_carry_flag_operator" "") (match_operand:SI 1 "nonimmediate_operand" "%0")) (match_operand:SI 2 "general_operand" "rim")))) (clobber (reg:CC 17))] "TARGET_64BIT && ix86_binary_operator_ok (PLUS, SImode, operands)" "adc{l}\t{%2, %k0|%k0, %2}" [(set_attr "type" "alu") (set_attr "pent_pair" "pu") (set_attr "mode" "SI") (set_attr "ppro_uops" "few")])

(define_insn "*addsi3_cc" [(set (reg:CC 17) (unspec:CC [(match_operand:SI 1 "nonimmediate_operand" "%0,0") (match_operand:SI 2 "general_operand" "ri,rm")] UNSPEC_ADD_CARRY)) (set (match_operand:SI 0 "nonimmediate_operand" "=rm,r") (plus:SI (match_dup 1) (match_dup 2)))] "ix86_binary_operator_ok (PLUS, SImode, operands)" "add{l}\t{%2, %0|%0, %2}" [(set_attr "type" "alu") (set_attr "mode" "SI")])

(define_insn "addqi3_cc" [(set (reg:CC 17) (unspec:CC [(match_operand:QI 1 "nonimmediate_operand" "%0,0") (match_operand:QI 2 "general_operand" "qi,qm")] UNSPEC_ADD_CARRY)) (set (match_operand:QI 0 "nonimmediate_operand" "=qm,q") (plus:QI (match_dup 1) (match_dup 2)))] "ix86_binary_operator_ok (PLUS, QImode, operands)" "add{b}\t{%2, %0|%0, %2}" [(set_attr "type" "alu") (set_attr "mode" "QI")])

(define_expand "addsi3" [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "") (plus:SI (match_operand:SI 1 "nonimmediate_operand" "") (match_operand:SI 2 "general_operand" ""))) (clobber (reg:CC 17))])] "" "ix86_expand_binary_operator (PLUS, SImode, operands); DONE;")

(define_insn "*lea_1" [(set (match_operand:SI 0 "register_operand" "=r") (match_operand:SI 1 "no_seg_address_operand" "p"))] "!TARGET_64BIT" "lea{l}\t{%a1, %0|%0, %a1}" [(set_attr "type" "lea") (set_attr "mode" "SI")])

(define_insn "*lea_1_rex64" [(set (match_operand:SI 0 "register_operand" "=r") (subreg:SI (match_operand:DI 1 "no_seg_address_operand" "p") 0))] "TARGET_64BIT" "lea{l}\t{%a1, %0|%0, %a1}" [(set_attr "type" "lea") (set_attr "mode" "SI")])

(define_insn "*lea_1_zext" [(set (match_operand:DI 0 "register_operand" "=r") (zero_extend:DI (subreg:SI (match_operand:DI 1 "no_seg_address_operand" "p") 0)))] "TARGET_64BIT" "lea{l}\t{%a1, %k0|%k0, %a1}" [(set_attr "type" "lea") (set_attr "mode" "SI")])

(define_insn "*lea_2_rex64" [(set (match_operand:DI 0 "register_operand" "=r") (match_operand:DI 1 "no_seg_address_operand" "p"))] "TARGET_64BIT" "lea{q}\t{%a1, %0|%0, %a1}" [(set_attr "type" "lea") (set_attr "mode" "DI")])

;; The lea patterns for non-Pmodes needs to be matched by several ;; insns converted to real lea by splitters.

(define_insn_and_split "*lea_general_1" [(set (match_operand 0 "register_operand" "=r") (plus (plus (match_operand 1 "index_register_operand" "r") (match_operand 2 "register_operand" "r")) (match_operand 3 "immediate_operand" "i")))] "(GET_MODE (operands[0]) == QImode || GET_MODE (operands[0]) == HImode || (TARGET_64BIT && GET_MODE (operands[0]) == SImode)) && (!TARGET_PARTIAL_REG_STALL || optimize_size) && GET_MODE (operands[0]) == GET_MODE (operands[1]) && GET_MODE (operands[0]) == GET_MODE (operands[2]) && (GET_MODE (operands[0]) == GET_MODE (operands[3]) || GET_MODE (operands[3]) == VOIDmode)" "#" "&& reload_completed" [(const_int 0)] { rtx pat; operands[0] = gen_lowpart (SImode, operands[0]); operands[1] = gen_lowpart (Pmode, operands[1]); operands[2] = gen_lowpart (Pmode, operands[2]); operands[3] = gen_lowpart (Pmode, operands[3]); pat = gen_rtx_PLUS (Pmode, gen_rtx_PLUS (Pmode, operands[1], operands[2]), operands[3]); if (Pmode != SImode) pat = gen_rtx_SUBREG (SImode, pat, 0); emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat)); DONE; } [(set_attr "type" "lea") (set_attr "mode" "SI")])

(define_insn_and_split "*lea_general_1_zext" [(set (match_operand:DI 0 "register_operand" "=r") (zero_extend:DI (plus:SI (plus:SI (match_operand:SI 1 "index_register_operand" "r") (match_operand:SI 2 "register_operand" "r")) (match_operand:SI 3 "immediate_operand" "i"))))] "TARGET_64BIT" "#" "&& reload_completed" [(set (match_dup 0) (zero_extend:DI (subreg:SI (plus:DI (plus:DI (match_dup 1) (match_dup 2)) (match_dup 3)) 0)))] { operands[1] = gen_lowpart (Pmode, operands[1]); operands[2] = gen_lowpart (Pmode, operands[2]); operands[3] = gen_lowpart (Pmode, operands[3]); } [(set_attr "type" "lea") (set_attr "mode" "SI")])

(define_insn_and_split "*lea_general_2" [(set (match_operand 0 "register_operand" "=r") (plus (mult (match_operand 1 "index_register_operand" "r") (match_operand 2 "const248_operand" "i")) (match_operand 3 "nonmemory_operand" "ri")))] "(GET_MODE (operands[0]) == QImode || GET_MODE (operands[0]) == HImode || (TARGET_64BIT && GET_MODE (operands[0]) == SImode)) && (!TARGET_PARTIAL_REG_STALL || optimize_size) && GET_MODE (operands[0]) == GET_MODE (operands[1]) && (GET_MODE (operands[0]) == GET_MODE (operands[3]) || GET_MODE (operands[3]) == VOIDmode)" "#" "&& reload_completed" [(const_int 0)] { rtx pat; operands[0] = gen_lowpart (SImode, operands[0]); operands[1] = gen_lowpart (Pmode, operands[1]); operands[3] = gen_lowpart (Pmode, operands[3]); pat = gen_rtx_PLUS (Pmode, gen_rtx_MULT (Pmode, operands[1], operands[2]), operands[3]); if (Pmode != SImode) pat = gen_rtx_SUBREG (SImode, pat, 0); emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat)); DONE; } [(set_attr "type" "lea") (set_attr "mode" "SI")])

(define_insn_and_split "*lea_general_2_zext" [(set (match_operand:DI 0 "register_operand" "=r") (zero_extend:DI (plus:SI (mult:SI (match_operand:SI 1 "index_register_operand" "r") (match_operand:SI 2 "const248_operand" "n")) (match_operand:SI 3 "nonmemory_operand" "ri"))))] "TARGET_64BIT" "#" "&& reload_completed" [(set (match_dup 0) (zero_extend:DI (subreg:SI (plus:DI (mult:DI (match_dup 1) (match_dup 2)) (match_dup 3)) 0)))] { operands[1] = gen_lowpart (Pmode, operands[1]); operands[3] = gen_lowpart (Pmode, operands[3]); } [(set_attr "type" "lea") (set_attr "mode" "SI")])

(define_insn_and_split "*lea_general_3" [(set (match_operand 0 "register_operand" "=r") (plus (plus (mult (match_operand 1 "index_register_operand" "r") (match_operand 2 "const248_operand" "i")) (match_operand 3 "register_operand" "r")) (match_operand 4 "immediate_operand" "i")))] "(GET_MODE (operands[0]) == QImode || GET_MODE (operands[0]) == HImode || (TARGET_64BIT && GET_MODE (operands[0]) == SImode)) && (!TARGET_PARTIAL_REG_STALL || optimize_size) && GET_MODE (operands[0]) == GET_MODE (operands[1]) && GET_MODE (operands[0]) == GET_MODE (operands[3])" "#" "&& reload_completed" [(const_int 0)] { rtx pat; operands[0] = gen_lowpart (SImode, operands[0]); operands[1] = gen_lowpart (Pmode, operands[1]); operands[3] = gen_lowpart (Pmode, operands[3]); operands[4] = gen_lowpart (Pmode, operands[4]); pat = gen_rtx_PLUS (Pmode, gen_rtx_PLUS (Pmode, gen_rtx_MULT (Pmode, operands[1], operands[2]), operands[3]), operands[4]); if (Pmode != SImode) pat = gen_rtx_SUBREG (SImode, pat, 0); emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat)); DONE; } [(set_attr "type" "lea") (set_attr "mode" "SI")])

(define_insn_and_split "*lea_general_3_zext" [(set (match_operand:DI 0 "register_operand" "=r") (zero_extend:DI (plus:SI (plus:SI (mult:SI (match_operand:SI 1 "index_register_operand" "r") (match_operand:SI 2 "const248_operand" "n")) (match_operand:SI 3 "register_operand" "r")) (match_operand:SI 4 "immediate_operand" "i"))))] "TARGET_64BIT" "#" "&& reload_completed" [(set (match_dup 0) (zero_extend:DI (subreg:SI (plus:DI (plus:DI (mult:DI (match_dup 1) (match_dup 2)) (match_dup 3)) (match_dup 4)) 0)))] { operands[1] = gen_lowpart (Pmode, operands[1]); operands[3] = gen_lowpart (Pmode, operands[3]); operands[4] = gen_lowpart (Pmode, operands[4]); } [(set_attr "type" "lea") (set_attr "mode" "SI")])

(define_insn "*adddi_1_rex64" [(set (match_operand:DI 0 "nonimmediate_operand" "=r,rm,r") (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,r") (match_operand:DI 2 "x86_64_general_operand" "rme,re,re"))) (clobber (reg:CC 17))] "TARGET_64BIT && ix86_binary_operator_ok (PLUS, DImode, operands)" { switch (get_attr_type (insn)) { case TYPE_LEA: operands[2] = SET_SRC (XVECEXP (PATTERN (insn), 0, 0)); return "lea{q}\t{%a2, %0|%0, %a2}";

case TYPE_INCDEC:
  if (! rtx_equal_p (operands[0], operands[1]))
abort ();
  if (operands[2] == const1_rtx)
    return "inc{q}\t%0";
  else if (operands[2] == constm1_rtx)
    return "dec{q}\t%0";
  else
abort ();

default:
  if (! rtx_equal_p (operands[0], operands[1]))
abort ();

  /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
 Exceptions: -128 encodes smaller than 128, so swap sign and op.  */
  if (GET_CODE (operands[2]) == CONST_INT
  /* Avoid overflows.  */
  && ((INTVAL (operands[2]) & ((((unsigned int) 1) << 31) - 1)))
      && (INTVAL (operands[2]) == 128
      || (INTVAL (operands[2]) < 0
	  && INTVAL (operands[2]) != -128)))
    {
      operands[2] = GEN_INT (-INTVAL (operands[2]));
      return "sub{q}\t{%2, %0|%0, %2}";
    }
  return "add{q}\t{%2, %0|%0, %2}";
}

} [(set (attr "type") (cond [(eq_attr "alternative" "2") (const_string "lea") ; Current assemblers are broken and do not allow @GOTOFF in ; ought but a memory context. (match_operand:DI 2 "pic_symbolic_operand" "") (const_string "lea") (match_operand:DI 2 "incdec_operand" "") (const_string "incdec") ] (const_string "alu"))) (set_attr "mode" "DI")])

;; Convert lea to the lea pattern to avoid flags dependency. (define_split [(set (match_operand:DI 0 "register_operand" "") (plus:DI (match_operand:DI 1 "register_operand" "") (match_operand:DI 2 "x86_64_nonmemory_operand" ""))) (clobber (reg:CC 17))] "TARGET_64BIT && reload_completed && true_regnum (operands[0]) != true_regnum (operands[1])" [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))] "")

(define_insn "adddi_2_rex64" [(set (reg 17) (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") (match_operand:DI 2 "x86_64_general_operand" "rme,re")) (const_int 0))) (set (match_operand:DI 0 "nonimmediate_operand" "=r,rm") (plus:DI (match_dup 1) (match_dup 2)))] "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode) && ix86_binary_operator_ok (PLUS, DImode, operands) / Current assemblers are broken and do not allow @GOTOFF in ought but a memory context. */ && ! pic_symbolic_operand (operands[2], VOIDmode)" { switch (get_attr_type (insn)) { case TYPE_INCDEC: if (! rtx_equal_p (operands[0], operands[1])) abort (); if (operands[2] == const1_rtx) return "inc{q}\t%0"; else if (operands[2] == constm1_rtx) return "dec{q}\t%0"; else abort ();

default:
  if (! rtx_equal_p (operands[0], operands[1]))
abort ();
  /* ???? We ought to handle there the 32bit case too
 - do we need new constraint?  */
  /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
 Exceptions: -128 encodes smaller than 128, so swap sign and op.  */
  if (GET_CODE (operands[2]) == CONST_INT
  /* Avoid overflows.  */
  && ((INTVAL (operands[2]) & ((((unsigned int) 1) << 31) - 1)))
      && (INTVAL (operands[2]) == 128
      || (INTVAL (operands[2]) < 0
	  && INTVAL (operands[2]) != -128)))
    {
      operands[2] = GEN_INT (-INTVAL (operands[2]));
      return "sub{q}\t{%2, %0|%0, %2}";
    }
  return "add{q}\t{%2, %0|%0, %2}";
}

} [(set (attr "type") (if_then_else (match_operand:DI 2 "incdec_operand" "") (const_string "incdec") (const_string "alu"))) (set_attr "mode" "DI")])

(define_insn "adddi_3_rex64" [(set (reg 17) (compare (neg:DI (match_operand:DI 2 "x86_64_general_operand" "rme")) (match_operand:DI 1 "x86_64_general_operand" "%0"))) (clobber (match_scratch:DI 0 "=r"))] "TARGET_64BIT && ix86_match_ccmode (insn, CCZmode) && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM) / Current assemblers are broken and do not allow @GOTOFF in ought but a memory context. */ && ! pic_symbolic_operand (operands[2], VOIDmode)" { switch (get_attr_type (insn)) { case TYPE_INCDEC: if (! rtx_equal_p (operands[0], operands[1])) abort (); if (operands[2] == const1_rtx) return "inc{q}\t%0"; else if (operands[2] == constm1_rtx) return "dec{q}\t%0"; else abort ();

default:
  if (! rtx_equal_p (operands[0], operands[1]))
abort ();
  /* ???? We ought to handle there the 32bit case too
 - do we need new constraint?  */
  /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
 Exceptions: -128 encodes smaller than 128, so swap sign and op.  */
  if (GET_CODE (operands[2]) == CONST_INT
  /* Avoid overflows.  */
  && ((INTVAL (operands[2]) & ((((unsigned int) 1) << 31) - 1)))
      && (INTVAL (operands[2]) == 128
      || (INTVAL (operands[2]) < 0
	  && INTVAL (operands[2]) != -128)))
    {
      operands[2] = GEN_INT (-INTVAL (operands[2]));
      return "sub{q}\t{%2, %0|%0, %2}";
    }
  return "add{q}\t{%2, %0|%0, %2}";
}

} [(set (attr "type") (if_then_else (match_operand:DI 2 "incdec_operand" "") (const_string "incdec") (const_string "alu"))) (set_attr "mode" "DI")])

; For comparisons against 1, -1 and 128, we may generate better code ; by converting cmp to add, inc or dec as done by peephole2. This pattern ; is matched then. We can't accept general immediate, because for ; case of overflows, the result is messed up. ; This pattern also don't hold of 0x8000000000000000, since the value overflows ; when negated. ; Also carry flag is reversed compared to cmp, so this conversion is valid ; only for comparisons not depending on it. (define_insn "*adddi_4_rex64" [(set (reg 17) (compare (match_operand:DI 1 "nonimmediate_operand" "0") (match_operand:DI 2 "x86_64_immediate_operand" "e"))) (clobber (match_scratch:DI 0 "=rm"))] "TARGET_64BIT && ix86_match_ccmode (insn, CCGCmode)" { switch (get_attr_type (insn)) { case TYPE_INCDEC: if (operands[2] == constm1_rtx) return "inc{q}\t%0"; else if (operands[2] == const1_rtx) return "dec{q}\t%0"; else abort();

default:
  if (! rtx_equal_p (operands[0], operands[1]))
abort ();
  /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
 Exceptions: -128 encodes smaller than 128, so swap sign and op.  */
  if ((INTVAL (operands[2]) == -128
   || (INTVAL (operands[2]) > 0
       && INTVAL (operands[2]) != 128))
  /* Avoid overflows.  */
  && ((INTVAL (operands[2]) & ((((unsigned int) 1) << 31) - 1))))
return "sub{q}\t{%2, %0|%0, %2}";
  operands[2] = GEN_INT (-INTVAL (operands[2]));
  return "add{q}\t{%2, %0|%0, %2}";
}

} [(set (attr "type") (if_then_else (match_operand:DI 2 "incdec_operand" "") (const_string "incdec") (const_string "alu"))) (set_attr "mode" "DI")])

(define_insn "adddi_5_rex64" [(set (reg 17) (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0") (match_operand:DI 2 "x86_64_general_operand" "rme")) (const_int 0))) (clobber (match_scratch:DI 0 "=r"))] "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode) && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM) / Current assemblers are broken and do not allow @GOTOFF in ought but a memory context. */ && ! pic_symbolic_operand (operands[2], VOIDmode)" { switch (get_attr_type (insn)) { case TYPE_INCDEC: if (! rtx_equal_p (operands[0], operands[1])) abort (); if (operands[2] == const1_rtx) return "inc{q}\t%0"; else if (operands[2] == constm1_rtx) return "dec{q}\t%0"; else abort();

default:
  if (! rtx_equal_p (operands[0], operands[1]))
abort ();
  /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
 Exceptions: -128 encodes smaller than 128, so swap sign and op.  */
  if (GET_CODE (operands[2]) == CONST_INT
  /* Avoid overflows.  */
  && ((INTVAL (operands[2]) & ((((unsigned int) 1) << 31) - 1)))
      && (INTVAL (operands[2]) == 128
      || (INTVAL (operands[2]) < 0
	  && INTVAL (operands[2]) != -128)))
    {
      operands[2] = GEN_INT (-INTVAL (operands[2]));
      return "sub{q}\t{%2, %0|%0, %2}";
    }
  return "add{q}\t{%2, %0|%0, %2}";
}

} [(set (attr "type") (if_then_else (match_operand:DI 2 "incdec_operand" "") (const_string "incdec") (const_string "alu"))) (set_attr "mode" "DI")])

(define_insn "*addsi_1" [(set (match_operand:SI 0 "nonimmediate_operand" "=r,rm,r") (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,r") (match_operand:SI 2 "general_operand" "rmni,rni,rni"))) (clobber (reg:CC 17))] "ix86_binary_operator_ok (PLUS, SImode, operands)" { switch (get_attr_type (insn)) { case TYPE_LEA: operands[2] = SET_SRC (XVECEXP (PATTERN (insn), 0, 0)); return "lea{l}\t{%a2, %0|%0, %a2}";

case TYPE_INCDEC:
  if (! rtx_equal_p (operands[0], operands[1]))
abort ();
  if (operands[2] == const1_rtx)
    return "inc{l}\t%0";
  else if (operands[2] == constm1_rtx)
    return "dec{l}\t%0";
  else
abort();

default:
  if (! rtx_equal_p (operands[0], operands[1]))
abort ();

  /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
 Exceptions: -128 encodes smaller than 128, so swap sign and op.  */
  if (GET_CODE (operands[2]) == CONST_INT
      && (INTVAL (operands[2]) == 128
      || (INTVAL (operands[2]) < 0
	  && INTVAL (operands[2]) != -128)))
    {
      operands[2] = GEN_INT (-INTVAL (operands[2]));
      return "sub{l}\t{%2, %0|%0, %2}";
    }
  return "add{l}\t{%2, %0|%0, %2}";
}

} [(set (attr "type") (cond [(eq_attr "alternative" "2") (const_string "lea") ; Current assemblers are broken and do not allow @GOTOFF in ; ought but a memory context. (match_operand:SI 2 "pic_symbolic_operand" "") (const_string "lea") (match_operand:SI 2 "incdec_operand" "") (const_string "incdec") ] (const_string "alu"))) (set_attr "mode" "SI")])

;; Convert lea to the lea pattern to avoid flags dependency. (define_split [(set (match_operand 0 "register_operand" "") (plus (match_operand 1 "register_operand" "") (match_operand 2 "nonmemory_operand" ""))) (clobber (reg:CC 17))] "reload_completed && true_regnum (operands[0]) != true_regnum (operands[1])" [(const_int 0)] { rtx pat; /* In -fPIC mode the constructs like (const (unspec [symbol_ref])) may confuse gen_lowpart. */ if (GET_MODE (operands[0]) != Pmode) { operands[1] = gen_lowpart (Pmode, operands[1]); operands[2] = gen_lowpart (Pmode, operands[2]); } operands[0] = gen_lowpart (SImode, operands[0]); pat = gen_rtx_PLUS (Pmode, operands[1], operands[2]); if (Pmode != SImode) pat = gen_rtx_SUBREG (SImode, pat, 0); emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat)); DONE; })

;; It may seem that nonimmediate operand is proper one for operand 1. ;; The addsi_1 pattern allows nonimmediate operand at that place and ;; we take care in ix86_binary_operator_ok to not allow two memory ;; operands so proper swapping will be done in reload. This allow ;; patterns constructed from addsi_1 to match. (define_insn "addsi_1_zext" [(set (match_operand:DI 0 "register_operand" "=r,r") (zero_extend:DI (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,r") (match_operand:SI 2 "general_operand" "rmni,rni")))) (clobber (reg:CC 17))] "TARGET_64BIT && ix86_binary_operator_ok (PLUS, SImode, operands)" { switch (get_attr_type (insn)) { case TYPE_LEA: operands[2] = SET_SRC (XVECEXP (PATTERN (insn), 0, 0)); return "lea{l}\t{%a2, %k0|%k0, %a2}";

case TYPE_INCDEC:
  if (operands[2] == const1_rtx)
    return "inc{l}\t%k0";
  else if (operands[2] == constm1_rtx)
    return "dec{l}\t%k0";
  else
abort();

default:
  /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
 Exceptions: -128 encodes smaller than 128, so swap sign and op.  */
  if (GET_CODE (operands[2]) == CONST_INT
      && (INTVAL (operands[2]) == 128
      || (INTVAL (operands[2]) < 0
	  && INTVAL (operands[2]) != -128)))
    {
      operands[2] = GEN_INT (-INTVAL (operands[2]));
      return "sub{l}\t{%2, %k0|%k0, %2}";
    }
  return "add{l}\t{%2, %k0|%k0, %2}";
}

} [(set (attr "type") (cond [(eq_attr "alternative" "1") (const_string "lea") ; Current assemblers are broken and do not allow @GOTOFF in ; ought but a memory context. (match_operand:SI 2 "pic_symbolic_operand" "") (const_string "lea") (match_operand:SI 2 "incdec_operand" "") (const_string "incdec") ] (const_string "alu"))) (set_attr "mode" "SI")])

;; Convert lea to the lea pattern to avoid flags dependency. (define_split [(set (match_operand:DI 0 "register_operand" "") (zero_extend:DI (plus:SI (match_operand:SI 1 "register_operand" "") (match_operand:SI 2 "nonmemory_operand" "")))) (clobber (reg:CC 17))] "TARGET_64BIT && reload_completed && true_regnum (operands[0]) != true_regnum (operands[1])" [(set (match_dup 0) (zero_extend:DI (subreg:SI (plus:DI (match_dup 1) (match_dup 2)) 0)))] { operands[1] = gen_lowpart (Pmode, operands[1]); operands[2] = gen_lowpart (Pmode, operands[2]); })

(define_insn "addsi_2" [(set (reg 17) (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0") (match_operand:SI 2 "general_operand" "rmni,rni")) (const_int 0))) (set (match_operand:SI 0 "nonimmediate_operand" "=r,rm") (plus:SI (match_dup 1) (match_dup 2)))] "ix86_match_ccmode (insn, CCGOCmode) && ix86_binary_operator_ok (PLUS, SImode, operands) / Current assemblers are broken and do not allow @GOTOFF in ought but a memory context. */ && ! pic_symbolic_operand (operands[2], VOIDmode)" { switch (get_attr_type (insn)) { case TYPE_INCDEC: if (! rtx_equal_p (operands[0], operands[1])) abort (); if (operands[2] == const1_rtx) return "inc{l}\t%0"; else if (operands[2] == constm1_rtx) return "dec{l}\t%0"; else abort();

default:
  if (! rtx_equal_p (operands[0], operands[1]))
abort ();
  /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
 Exceptions: -128 encodes smaller than 128, so swap sign and op.  */
  if (GET_CODE (operands[2]) == CONST_INT
      && (INTVAL (operands[2]) == 128
      || (INTVAL (operands[2]) < 0
	  && INTVAL (operands[2]) != -128)))
    {
      operands[2] = GEN_INT (-INTVAL (operands[2]));
      return "sub{l}\t{%2, %0|%0, %2}";
    }
  return "add{l}\t{%2, %0|%0, %2}";
}