Alan Cox 46a7f2ebd4 According to Section D5.10.3 "Maintenance requirements on changing System ... register values" of the architecture manual, an isb instruction should be executed after updating ttbr0_el1 and before invalidating the TLB. The lack of this instruction in pmap_activate() appears to be the reason why andrew@ and I have observed an unexpected TLB entry for an invalid PTE on entry to pmap_enter_quick_locked(). Thus, we should now be able to revert the workaround committed in r349442. Reviewed by: markj MFC after: 1 week Differential Revision: https://reviews.freebsd.org/D20904		2019-07-11 02:43:23 +00:00
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acpica	arm64 acpi_iort: add some error handling	2019-06-24 21:24:55 +00:00
arm64	According to Section D5.10.3 "Maintenance requirements on changing System	2019-07-11 02:43:23 +00:00
cavium	Rename the ThunderX CPU identification macros to include the X. This is the	2018-06-13 12:17:11 +00:00
cloudabi32	Remove sv_pagesize, originally introduced with r100384.	2019-03-01 16:16:38 +00:00
cloudabi64	Remove sv_pagesize, originally introduced with r100384.	2019-03-01 16:16:38 +00:00
conf	sys: Remove DEV_RANDOM device option	2019-06-21 00:16:30 +00:00
coresight	Extract eventfilter declarations to sys/_eventfilter.h	2019-05-20 00:38:23 +00:00
include	Lightly hide the 'var' inside the macros to read the arm special registers.	2019-06-15 00:47:39 +00:00
linux	makesyscalls.sh: always use absolute path for syscalls.conf	2019-05-30 20:56:23 +00:00
qualcomm	Enable Qualcomm Debug Subsystem (QDSS) block on MSM8916 SoC.	2018-04-10 12:53:48 +00:00
rockchip	Subclass Rockchip's General Register Files driver from Simple MFD driver.	2019-07-03 03:42:51 +00:00