960e65d23a
This is a very simple implementation of Qualcomm's SCM API. It is just the structure/field definitions and the atomic SCM call which doesn't use the structs yet - it uses the field definitions inside registers. I've tested that setting the cold boot address via the atomic API is fine - Linux does the same thing. But not all SCM calls can be done via the legacy API. This is a reimplementation based on the Linux qualcomm SCM legacy code and definitions. Tested: * Qualcomm IPQ4018 AP, as part of other changes for doing SMP bring-up Reviewed by: andrew, manu, imp Differential Revision: https://reviews.freebsd.org/D32723
150 lines
4.9 KiB
C
150 lines
4.9 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*
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* Copyright (c) 2021 Adrian Chadd <adrian@FreeBSD.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef __QCOM_SCM_LEGACY_DEFS_H__
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#define __QCOM_SCM_LEGACY_DEFS_H__
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/*
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* These definitions are specific to the 32 bit legacy SCM interface
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* used by the IPQ806x and IPQ401x SoCs.
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*/
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/*
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* Mapping of the SCM service/command fields into the a0 argument
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* in an SMC instruction call.
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*
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* This is particular to the legacy SCM interface, and is not the
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* same as the non-legacy 32/64 bit FNID mapping layout.
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*/
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#define QCOM_SCM_LEGACY_SMC_FNID(s, c) (((s) << 10) | ((c) & 0x3ff))
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/*
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* There are two kinds of SCM calls in this legacy path.
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*
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* The first kind are the normal ones - up to a defined max of arguments,
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* a defined max of responses and some identifiers for all of it.
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* They can be issues in parallel on different cores, can be interrupted,
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* etc.
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*
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* The second kind are what are termed "atomic" SCM calls -
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* up to 5 argument DWORDs, up to 3 response DWORDs, done atomically,
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* not interruptable/parallel.
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*
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* The former use the structures below to represent the request and response
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* in memory. The latter use defines and a direct SMC call with the
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* arguments in registers.
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*/
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struct qcom_scm_legacy_smc_args {
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uint32_t args[8];
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};
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/*
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* Atomic SCM call command/response buffer definitions.
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*/
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#define QCOM_SCM_LEGACY_ATOMIC_MAX_ARGCOUNT 5
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#define QCOM_SCM_LEGACY_CLASS_REGISTER (0x2 << 8)
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#define QCOM_SCM_LEGACY_MASK_IRQS (1U << 5)
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/*
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* Mapping an SCM service/command/argcount into the a0 register
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* for an SMC instruction call.
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*/
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#define QCOM_SCM_LEGACY_ATOMIC_ID(svc, cmd, n) \
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((QCOM_SCM_LEGACY_SMC_FNID((svc), cmd) << 12) | \
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QCOM_SCM_LEGACY_CLASS_REGISTER | \
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QCOM_SCM_LEGACY_MASK_IRQS | \
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((n) & 0xf))
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/*
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* Legacy command/response buffer definitions.
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*
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* The legacy path contains up to the defined maximum arguments
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* but only a single command/response pair per call.
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*
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* A command and response buffer is laid out in memory as such:
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*
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* | command header |
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* | (buffer payload) |
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* | response header |
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* | (response payload) |
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*/
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/*
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* The command header.
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*
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* len - the length of the total command and response, including
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* the headers.
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*
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* buf_offset - the offset inside the buffer, starting at the
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* beginning of this command header, where the command buffer
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* is found. The end is the byte before the response_header_offset.
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*
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* response_header_offset - the offset inside the buffer where
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* the response header is found.
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*
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* id - the QCOM_SCM_LEGACY_SMC_FNID() - service/command ids
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*/
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struct qcom_scm_legacy_command_header {
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uint32_t len;
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uint32_t buf_offset;
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uint32_t response_header_offset;
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uint32_t id;
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};
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/*
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* The response header.
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*
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* This is found immediately after the command header and command
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* buffer payload.
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*
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* len - the total amount of memory available for the response.
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* Linux doesn't set this; it always passes in a response
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* buffer large enough to store MAX_QCOM_SCM_RETS * DWORD
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* bytes.
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*
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* It's also possible this is set by the firmware.
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*
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* buf_offset - start of response buffer, relative to the beginning
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* of the command header. This also isn't set in Linux before
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* calling the SMC instruction, but it is checked afterwards
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* to assemble a pointer to the response data. The firmware
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* likely sets this.
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*
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* is_complete - true if complete. Linux loops over DMA sync to
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* check if this is complete even after the SMC call returns.
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*/
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struct qcom_scm_legacy_response_header {
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uint32_t len;
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uint32_t buf_offset;
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uint32_t is_complete;
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};
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#endif /* __QCOM_SCM_LEGACY_DEFS_H__ */
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