Alexander Motin 5a49f19141 Do not expose to scheduler caches of single CPU. ... Before this change my dual-Xeon(R) Gold 6242R always reported 3 levels or topology (root, package/L3 and core/L2). But with SMT disabled core/L2 matches thread, so additional topology level only causes more traversal work. With this change SMT case is reported same as before, while non-SMT is reported with only 2 much more simple levels. MFC after: 2 weeks		2021-07-28 16:38:01 -04:00
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acpica	Disable x2APIC for SandyBridge laptops with Samsung BIOS	2021-06-03 22:47:31 +03:00
bios	smbios: Move smbios driver out from x86 machdep code	2021-02-23 21:17:09 +00:00
conf	Use envvar rather than nonstandard hint. lines	2020-09-23 19:18:53 +00:00
cpufreq	hwpstate_intel: don't unconditionally print the error message	2020-11-29 01:43:04 +00:00
include	xen: introduce xen_has_percpu_evtchn()	2021-07-28 17:27:05 +02:00
iommu	dmar: reserve memory windows of PCIe root port	2020-12-09 18:43:58 +00:00
isa	amd64: Add MD bits for KASAN	2021-04-13 17:42:20 -04:00
linux	Drop "All rights reserved" from my copyright statements.	2021-07-20 10:05:50 +03:00
pci	x86: clean up empty lines in .c and .h files	2020-09-01 21:23:59 +00:00
x86	Do not expose to scheduler caches of single CPU.	2021-07-28 16:38:01 -04:00
xen	xen: introduce xen_has_percpu_evtchn()	2021-07-28 17:27:05 +02:00