243 lines
7.1 KiB
C
243 lines
7.1 KiB
C
/*
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* Copyright (C) 2001 Eduardo Horvath.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* from: NetBSD: gemvar.h,v 1.5 2001/10/18 15:19:22 thorpej Exp
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*
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* $FreeBSD$
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*/
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#ifndef _IF_GEMVAR_H
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#define _IF_GEMVAR_H
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#include <sys/queue.h>
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#include <sys/callout.h>
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/*
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* Misc. definitions for the Sun ``Gem'' Ethernet controller family driver.
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*/
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/*
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* Transmit descriptor list size. This is arbitrary, but allocate
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* enough descriptors for 64 pending transmissions and 16 segments
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* per packet.
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*/
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#define GEM_NTXSEGS 16
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#define GEM_TXQUEUELEN 64
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#define GEM_NTXDESC (GEM_TXQUEUELEN * GEM_NTXSEGS)
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#define GEM_NTXDESC_MASK (GEM_NTXDESC - 1)
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#define GEM_NEXTTX(x) ((x + 1) & GEM_NTXDESC_MASK)
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/*
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* Receive descriptor list size. We have one Rx buffer per incoming
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* packet, so this logic is a little simpler.
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*/
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#define GEM_NRXDESC 128
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#define GEM_NRXDESC_MASK (GEM_NRXDESC - 1)
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#define GEM_NEXTRX(x) ((x + 1) & GEM_NRXDESC_MASK)
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/*
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* Control structures are DMA'd to the GEM chip. We allocate them in
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* a single clump that maps to a single DMA segment to make several things
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* easier.
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*/
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struct gem_control_data {
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/*
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* The transmit descriptors.
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*/
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struct gem_desc gcd_txdescs[GEM_NTXDESC];
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/*
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* The receive descriptors.
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*/
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struct gem_desc gcd_rxdescs[GEM_NRXDESC];
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};
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#define GEM_CDOFF(x) offsetof(struct gem_control_data, x)
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#define GEM_CDTXOFF(x) GEM_CDOFF(gcd_txdescs[(x)])
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#define GEM_CDRXOFF(x) GEM_CDOFF(gcd_rxdescs[(x)])
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/*
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* Software state for transmit job mbufs (may be elements of mbuf chains).
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*/
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struct gem_txsoft {
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struct mbuf *txs_mbuf; /* head of our mbuf chain */
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bus_dmamap_t txs_dmamap; /* our DMA map */
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int txs_firstdesc; /* first descriptor in packet */
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int txs_lastdesc; /* last descriptor in packet */
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int txs_ndescs; /* number of descriptors */
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STAILQ_ENTRY(gem_txsoft) txs_q;
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};
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STAILQ_HEAD(gem_txsq, gem_txsoft);
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/* Argument structure for busdma callback */
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struct gem_txdma {
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struct gem_softc *txd_sc;
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int txd_nexttx;
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int txd_lasttx;
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int txd_nsegs;
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int txd_flags;
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#define GTXD_FIRST 1
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#define GTXD_LAST 2
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int txd_error;
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};
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/* Transmit job descriptor */
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struct gem_txjob {
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int txj_nexttx;
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int txj_lasttx;
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int txj_nsegs;
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STAILQ_HEAD(, gem_txsoft) txj_txsq;
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};
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/*
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* Software state for receive jobs.
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*/
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struct gem_rxsoft {
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struct mbuf *rxs_mbuf; /* head of our mbuf chain */
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bus_dmamap_t rxs_dmamap; /* our DMA map */
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bus_addr_t rxs_paddr; /* physical address of the segment */
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};
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/*
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* Software state per device.
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*/
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struct gem_softc {
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struct arpcom sc_arpcom; /* arp common data */
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device_t sc_miibus;
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struct mii_data *sc_mii; /* MII media control */
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device_t sc_dev; /* generic device information */
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struct callout sc_tick_ch; /* tick callout */
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/* The following bus handles are to be provided by the bus front-end */
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bus_space_tag_t sc_bustag; /* bus tag */
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bus_dma_tag_t sc_pdmatag; /* parent bus dma tag */
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bus_dma_tag_t sc_dmatag; /* bus dma tag */
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bus_dma_tag_t sc_cdmatag; /* control data bus dma tag */
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bus_dmamap_t sc_dmamap; /* bus dma handle */
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bus_space_handle_t sc_h; /* bus space handle for all regs */
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int sc_phys[2]; /* MII instance -> PHY map */
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int sc_mif_config; /* Selected MII reg setting */
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int sc_pci; /* XXXXX -- PCI buses are LE. */
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/*
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* Ring buffer DMA stuff.
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*/
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bus_dma_segment_t sc_cdseg; /* control data memory */
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int sc_cdnseg; /* number of segments */
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bus_dmamap_t sc_cddmamap; /* control data DMA map */
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bus_addr_t sc_cddma;
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/*
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* Software state for transmit and receive descriptors.
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*/
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struct gem_txsoft sc_txsoft[GEM_TXQUEUELEN];
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struct gem_rxsoft sc_rxsoft[GEM_NRXDESC];
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/*
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* Control data structures.
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*/
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struct gem_control_data *sc_control_data;
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#define sc_txdescs sc_control_data->gcd_txdescs
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#define sc_rxdescs sc_control_data->gcd_rxdescs
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int sc_txfree; /* number of free Tx descriptors */
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int sc_txnext; /* next ready Tx descriptor */
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struct gem_txsq sc_txfreeq; /* free Tx descsofts */
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struct gem_txsq sc_txdirtyq; /* dirty Tx descsofts */
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int sc_rxptr; /* next ready RX descriptor/descsoft */
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/* ========== */
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int sc_inited;
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int sc_debug;
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int sc_flags;
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/* Special hardware hooks */
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void (*sc_hwreset) __P((struct gem_softc *));
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void (*sc_hwinit) __P((struct gem_softc *));
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};
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#define GEM_DMA_READ(sc, v) (((sc)->sc_pci) ? le64toh(v) : be64toh(v))
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#define GEM_DMA_WRITE(sc, v) (((sc)->sc_pci) ? htole64(v) : htobe64(v))
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#define GEM_CDTXADDR(sc, x) ((sc)->sc_cddma + GEM_CDTXOFF((x)))
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#define GEM_CDRXADDR(sc, x) ((sc)->sc_cddma + GEM_CDRXOFF((x)))
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#define GEM_CDSPADDR(sc) ((sc)->sc_cddma + GEM_CDSPOFF)
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#define GEM_CDTXSYNC(sc, x, n, ops) \
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bus_dmamap_sync((sc)->sc_dmatag, (sc)->sc_cddmamap, (ops)); \
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#define GEM_CDRXSYNC(sc, x, ops) \
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bus_dmamap_sync((sc)->sc_dmatag, (sc)->sc_cddmamap, (ops))
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#define GEM_CDSPSYNC(sc, ops) \
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bus_dmamap_sync((sc)->sc_dmatag, (sc)->sc_cddmamap, (ops))
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#define GEM_INIT_RXDESC(sc, x) \
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do { \
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struct gem_rxsoft *__rxs = &sc->sc_rxsoft[(x)]; \
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struct gem_desc *__rxd = &sc->sc_rxdescs[(x)]; \
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struct mbuf *__m = __rxs->rxs_mbuf; \
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\
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__m->m_data = __m->m_ext.ext_buf; \
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__rxd->gd_addr = \
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GEM_DMA_WRITE((sc), __rxs->rxs_paddr); \
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__rxd->gd_flags = \
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GEM_DMA_WRITE((sc), \
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(((__m->m_ext.ext_size)<<GEM_RD_BUFSHIFT) \
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& GEM_RD_BUFSIZE) | GEM_RD_OWN); \
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GEM_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \
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} while (0)
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#ifdef _KERNEL
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extern devclass_t gem_devclass;
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int gem_attach __P((struct gem_softc *));
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int gem_detach __P((struct gem_softc *));
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void gem_intr __P((void *));
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int gem_mediachange __P((struct ifnet *));
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void gem_mediastatus __P((struct ifnet *, struct ifmediareq *));
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void gem_reset __P((struct gem_softc *));
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/* MII methods & callbacks */
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int gem_mii_readreg __P((device_t, int, int));
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int gem_mii_writereg __P((device_t, int, int, int));
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void gem_mii_statchg __P((device_t));
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#endif /* _KERNEL */
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#endif
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