4587b6e9fd
devices. This is a nop, except for what's reported by atmelbus for the resources. It would be nice if we could dymanically allocated these things, but the pmap_mapdev panics if we don't keep the static mappings, so we still need to play the carefully allocate VA space between all supported SoC game. User's with their own devices may need to make adjustments.
307 lines
9.3 KiB
C
307 lines
9.3 KiB
C
/*-
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* Copyright (c) 2005 Olivier Houchard. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/* $FreeBSD$ */
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#ifndef AT91RM92REG_H_
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#define AT91RM92REG_H_
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/* Chip Specific limits */
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#define RM9200_PLL_A_MIN_IN_FREQ 1000000 /* 1 MHz */
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#define RM9200_PLL_A_MAX_IN_FREQ 32000000 /* 32 MHz */
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#define RM9200_PLL_A_MIN_OUT_FREQ 80000000 /* 80 MHz */
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#define RM9200_PLL_A_MAX_OUT_FREQ 180000000 /* 180 MHz */
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#define RM9200_PLL_A_MUL_SHIFT 16
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#define RM9200_PLL_A_MUL_MASK 0x7FF
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#define RM9200_PLL_A_DIV_SHIFT 0
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#define RM9200_PLL_A_DIV_MASK 0xFF
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/*
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* PLL B input frequency spec sheet says it must be between 1MHz and 32MHz,
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* but it works down as low as 100kHz, a frequency necessary for some
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* output frequencies to work.
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*
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* PLL Max output frequency is 240MHz. The errata says 180MHz is the max
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* for some revisions of this part. Be more permissive and optimistic.
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*/
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#define RM9200_PLL_B_MIN_IN_FREQ 100000 /* 100 KHz */
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#define RM9200_PLL_B_MAX_IN_FREQ 32000000 /* 32 MHz */
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#define RM9200_PLL_B_MIN_OUT_FREQ 30000000 /* 30 MHz */
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#define RM9200_PLL_B_MAX_OUT_FREQ 240000000 /* 240 MHz */
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#define RM9200_PLL_B_MUL_SHIFT 16
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#define RM9200_PLL_B_MUL_MASK 0x7FF
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#define RM9200_PLL_B_DIV_SHIFT 0
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#define RM9200_PLL_B_DIV_MASK 0xFF
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/*
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* Memory map, from datasheet :
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* 0x00000000 - 0x0ffffffff : Internal Memories
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* 0x10000000 - 0x1ffffffff : Chip Select 0
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* 0x20000000 - 0x2ffffffff : Chip Select 1
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* 0x30000000 - 0x3ffffffff : Chip Select 2
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* 0x40000000 - 0x4ffffffff : Chip Select 3
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* 0x50000000 - 0x5ffffffff : Chip Select 4
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* 0x60000000 - 0x6ffffffff : Chip Select 5
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* 0x70000000 - 0x7ffffffff : Chip Select 6
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* 0x80000000 - 0x8ffffffff : Chip Select 7
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* 0x90000000 - 0xeffffffff : Undefined (Abort)
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* 0xf0000000 - 0xfffffffff : Peripherals
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*/
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/* Usart */
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#define AT91RM92_USART_SIZE 0x4000
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#define AT91RM92_USART0_BASE 0xffc0000
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#define AT91RM92_USART0_PDC 0xffc0100
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#define AT91RM92_USART0_SIZE AT91RM92_USART_SIZE
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#define AT91RM92_USART1_BASE 0xffc4000
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#define AT91RM92_USART1_PDC 0xffc4100
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#define AT91RM92_USART1_SIZE AT91RM92_USART_SIZE
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#define AT91RM92_USART2_BASE 0xffc8000
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#define AT91RM92_USART2_PDC 0xffc8100
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#define AT91RM92_USART2_SIZE AT91RM92_USART_SIZE
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#define AT91RM92_USART3_BASE 0xffcc000
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#define AT91RM92_USART3_PDC 0xffcc100
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#define AT91RM92_USART3_SIZE AT91RM92_USART_SIZE
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/* System Registers */
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#define AT91RM92_SYS_BASE 0xffff000
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#define AT91RM92_SYS_SIZE 0x1000
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/*
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* PIO
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*/
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#define AT91RM92_PIO_SIZE 0x200
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#define AT91RM92_PIOA_BASE 0xffff400
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#define AT91RM92_PIOA_SIZE AT91RM92_PIO_SIZE
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#define AT91RM92_PIOB_BASE 0xffff600
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#define AT91RM92_PIOB_SIZE AT91RM92_PIO_SIZE
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#define AT91RM92_PIOC_BASE 0xffff800
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#define AT91RM92_PIOC_SIZE AT91RM92_PIO_SIZE
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#define AT91RM92_PIOD_BASE 0xffffa00
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#define AT91RM92_PIOD_SIZE AT91RM92_PIO_SIZE
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/*
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* PMC
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*/
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#define AT91RM92_PMC_BASE 0xffffc00
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#define AT91RM92_PMC_SIZE 0x100
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/* IRQs : */
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/*
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* 0: AIC
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* 1: System peripheral (System timer, RTC, DBGU)
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* 2: PIO Controller A
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* 3: PIO Controller B
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* 4: PIO Controller C
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* 5: PIO Controller D
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* 6: USART 0
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* 7: USART 1
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* 8: USART 2
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* 9: USART 3
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* 10: MMC Interface
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* 11: USB device port
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* 12: Two-wirte interface
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* 13: SPI
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* 14: SSC
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* 15: SSC
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* 16: SSC
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* 17: Timer Counter 0
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* 18: Timer Counter 1
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* 19: Timer Counter 2
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* 20: Timer Counter 3
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* 21: Timer Counter 4
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* 22: Timer Counter 6
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* 23: USB Host port
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* 24: Ethernet
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* 25: AIC
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* 26: AIC
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* 27: AIC
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* 28: AIC
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* 29: AIC
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* 30: AIC
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* 31: AIC
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*/
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#define AT91RM92_IRQ_SYSTEM 1
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#define AT91RM92_IRQ_PIOA 2
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#define AT91RM92_IRQ_PIOB 3
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#define AT91RM92_IRQ_PIOC 4
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#define AT91RM92_IRQ_PIOD 5
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#define AT91RM92_IRQ_USART0 6
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#define AT91RM92_IRQ_USART1 7
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#define AT91RM92_IRQ_USART2 8
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#define AT91RM92_IRQ_USART3 9
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#define AT91RM92_IRQ_MCI 10
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#define AT91RM92_IRQ_UDP 11
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#define AT91RM92_IRQ_TWI 12
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#define AT91RM92_IRQ_SPI 13
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#define AT91RM92_IRQ_SSC0 14
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#define AT91RM92_IRQ_SSC1 15
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#define AT91RM92_IRQ_SSC2 16
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#define AT91RM92_IRQ_TC0 17,18,19
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#define AT91RM92_IRQ_TC0C0 17
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#define AT91RM92_IRQ_TC0C1 18
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#define AT91RM92_IRQ_TC0C2 19
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#define AT91RM92_IRQ_TC1 20,21,22
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#define AT91RM92_IRQ_TC1C1 20
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#define AT91RM92_IRQ_TC1C2 21
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#define AT91RM92_IRQ_TC1C3 22
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#define AT91RM92_IRQ_UHP 23
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#define AT91RM92_IRQ_EMAC 24
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#define AT91RM92_IRQ_AIC_IRQ0 25
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#define AT91RM92_IRQ_AIC_IRQ1 26
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#define AT91RM92_IRQ_AIC_IRQ2 27
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#define AT91RM92_IRQ_AIC_IRQ3 28
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#define AT91RM92_IRQ_AIC_IRQ4 29
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#define AT91RM92_IRQ_AIC_IRQ5 30
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#define AT91RM92_IRQ_AIC_IRQ6 31
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/* Alias */
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#define AT91RM92_IRQ_DBGU AT91RM92_IRQ_SYSTEM
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#define AT91RM92_IRQ_PMC AT91RM92_IRQ_SYSTEM
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#define AT91RM92_IRQ_ST AT91RM92_IRQ_SYSTEM
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#define AT91RM92_IRQ_RTC AT91RM92_IRQ_SYSTEM
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#define AT91RM92_IRQ_MC AT91RM92_IRQ_SYSTEM
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#define AT91RM92_IRQ_OHCI AT91RM92_IRQ_UHP
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#define AT91RM92_IRQ_AIC -1
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#define AT91RM92_IRQ_CF -1
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/* Timer */
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#define AT91RM92_AIC_BASE 0xffff000
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#define AT91RM92_AIC_SIZE 0x200
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/* DBGU */
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#define AT91RM92_DBGU_BASE 0xffff200
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#define AT91RM92_DBGU_SIZE 0x200
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#define AT91RM92_RTC_BASE 0xffffe00
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#define AT91RM92_RTC_SIZE 0x100
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#define AT91RM92_MC_BASE 0xfffff00
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#define AT91RM92_MC_SIZE 0x100
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#define AT91RM92_ST_BASE 0xffffd00
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#define AT91RM92_ST_SIZE 0x100
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#define AT91RM92_SPI_BASE 0xffe0000
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#define AT91RM92_SPI_SIZE 0x4000
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#define AT91RM92_SPI_PDC 0xffe0100
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#define AT91RM92_SSC_SIZE 0x4000
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#define AT91RM92_SSC0_BASE 0xffd0000
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#define AT91RM92_SSC0_PDC 0xffd0100
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#define AT91RM92_SSC0_SIZE AT91RM92_SSC_SIZE
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#define AT91RM92_SSC1_BASE 0xffd4000
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#define AT91RM92_SSC1_PDC 0xffd4100
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#define AT91RM92_SSC1_SIZE AT91RM92_SSC_SIZE
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#define AT91RM92_SSC2_BASE 0xffd8000
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#define AT91RM92_SSC2_PDC 0xffd8100
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#define AT91RM92_SSC2_SIZE AT91RM92_SSC_SIZE
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#define AT91RM92_EMAC_BASE 0xffbc000
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#define AT91RM92_EMAC_SIZE 0x4000
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#define AT91RM92_TWI_BASE 0xffb8000
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#define AT91RM92_TWI_SIZE 0x4000
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#define AT91RM92_MCI_BASE 0xffb4000
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#define AT91RM92_MCI_PDC 0xffb4100
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#define AT91RM92_MCI_SIZE 0x4000
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#define AT91RM92_UDP_BASE 0xffb0000
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#define AT91RM92_UDP_SIZE 0x4000
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#define AT91RM92_TC_SIZE 0x4000
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#define AT91RM92_TC0_BASE 0xffa0000
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#define AT91RM92_TC0_SIZE AT91RM92_TC_SIZE
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#define AT91RM92_TC0C0_BASE 0xffa0000
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#define AT91RM92_TC0C1_BASE 0xffa0040
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#define AT91RM92_TC0C2_BASE 0xffa0080
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#define AT91RM92_TC1_BASE 0xffa4000
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#define AT91RM92_TC1_SIZE AT91RM92_TC_SIZE
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#define AT91RM92_TC1C0_BASE 0xffa4000
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#define AT91RM92_TC1C1_BASE 0xffa4040
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#define AT91RM92_TC1C2_BASE 0xffa4080
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/* XXX Needs to be carfully coordinated with
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* other * soc's so phyical and vm address
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* mapping are unique. XXX
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*/
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#define AT91RM92_OHCI_VA_BASE 0xdfe00000
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#define AT91RM92_OHCI_BASE 0x00300000
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#define AT91RM92_OHCI_SIZE 0x00100000
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#define AT91RM92_CF_VA_BASE 0xdfd00000
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#define AT91RM92_CF_BASE 0x51400000
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#define AT91RM92_CF_SIZE 0x00100000
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/* SDRAMC */
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#define AT91RM92_SDRAMC_BASE 0xfffff90
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#define AT91RM92_SDRAMC_MR 0x00
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#define AT91RM92_SDRAMC_MR_MODE_NORMAL 0
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#define AT91RM92_SDRAMC_MR_MODE_NOP 1
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#define AT91RM92_SDRAMC_MR_MODE_PRECHARGE 2
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#define AT91RM92_SDRAMC_MR_MODE_LOAD_MODE_REGISTER 3
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#define AT91RM92_SDRAMC_MR_MODE_REFRESH 4
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#define AT91RM92_SDRAMC_MR_DBW_16 0x10
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#define AT91RM92_SDRAMC_TR 0x04
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#define AT91RM92_SDRAMC_CR 0x08
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#define AT91RM92_SDRAMC_CR_NC_8 0x0
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#define AT91RM92_SDRAMC_CR_NC_9 0x1
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#define AT91RM92_SDRAMC_CR_NC_10 0x2
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#define AT91RM92_SDRAMC_CR_NC_11 0x3
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#define AT91RM92_SDRAMC_CR_NC_MASK 0x00000003
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#define AT91RM92_SDRAMC_CR_NR_11 0x0
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#define AT91RM92_SDRAMC_CR_NR_12 0x4
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#define AT91RM92_SDRAMC_CR_NR_13 0x8
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#define AT91RM92_SDRAMC_CR_NR_RES 0xc
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#define AT91RM92_SDRAMC_CR_NR_MASK 0x0000000c
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#define AT91RM92_SDRAMC_CR_NB_2 0x00
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#define AT91RM92_SDRAMC_CR_NB_4 0x10
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#define AT91RM92_SDRAMC_CR_NB_MASK 0x00000010
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#define AT91RM92_SDRAMC_CR_NCAS_MASK 0x00000060
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#define AT91RM92_SDRAMC_CR_TWR_MASK 0x00000780
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#define AT91RM92_SDRAMC_CR_TRC_MASK 0x00007800
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#define AT91RM92_SDRAMC_CR_TRP_MASK 0x00078000
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#define AT91RM92_SDRAMC_CR_TRCD_MASK 0x00780000
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#define AT91RM92_SDRAMC_CR_TRAS_MASK 0x07800000
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#define AT91RM92_SDRAMC_CR_TXSR_MASK 0x78000000
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#define AT91RM92_SDRAMC_SRR 0x0c
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#define AT91RM92_SDRAMC_LPR 0x10
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#define AT91RM92_SDRAMC_IER 0x14
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#define AT91RM92_SDRAMC_IDR 0x18
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#define AT91RM92_SDRAMC_IMR 0x1c
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#define AT91RM92_SDRAMC_ISR 0x20
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#define AT91RM92_SDRAMC_IER_RES 0x1
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#endif /* AT91RM92REG_H_ */
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