919133a8ef
- MPSAFE. No more recursive lock required. - bus_dma(9) conversion. I think it should work on all architectures. - optimized Rx handler for each normal and jumbo frames. Previously sk(4) used jumbo frame management code to handle normal sized frames. As the handler needs an additional lock to protect jumbo frame management structure from races, it used two lock operations for each received packet. Now sk(4) uses single lock operation for normal frame.(Jumbo frame still needs two lock operations as before.) The hardware supports DMA scatter operations for Rx descriptors such that it's possible to take advantagee of m_cljget(9) for jumbo frames. However, due to a unknown reasons it resulted in poor performance on sparc64. So I dropped m_cljget(9) approach. This should be revisited since it would reduce one lock operation for jumbo frame handling. - Tx TCP/Rx IP checksum offload support. According to the data sheet of SK-NET GENESIS the hardware supports Rx IP/TCP/UDP offload. But I couldn't make it work on my Yukon hardware. So Rx TCP/UDP was disabled at the moment. It seems that newer Yukon chips can support Tx UDP checksum offload too. But I need more documentation first. - Added more wait time in reading VPD data. It seems that ASUS LOM takes a very long time to respond VPD read signal. - Added an additional lock for MII register access callbacks. - Added more strict received packet validation routine. Previously it passed corrupted packets to upper layers under certain conditions. - A new function sk_yukon_tick() to handle auto-negotiation properly. - Interrupt handler now checks shared interrupt source and protects the interrupt handler from NULL pointer dereference which was caused by odd status word value. The status word can returns 0xffffffff if cable is unplugged while Rx/Tx/auto-negotiation is in progress. - suspend/resume support(not tested). - Added Rx/Tx FIFO flush routine for Yukon - Activate Tx descriptor poll timer in order to protect possible loss of SK_TXBMU_TX_START command. Previously the driver continuously issued SK_TXBMU_TX_START when it notices pending Tx descriptors not processed yet in interrupt handler. That approach would add additional PCI write access overhead under high Tx load situations and it might fail if the first SK_TXBMU_TX_START was lost and no interrupt is generated from the first SK_TXBMU_TX_START command. - s/printf/if_printf/, s/printf/device_printf/, Axe sk_unit in softc. - Setting multicast/station address is now safe on strict-alignment architectures. - Fix long standing bug in VLAN header length setup. - Added/corrected register definitions for Yukon. (Register information from Linux skge driver.) - Added Rx status definition for Marvell Yukon/XaQti XMAC. (Rx status register information from Linux skge driver.) - Update if_oerrors if we encounter watchdog error. - callout(9) conversion Special thanks to jkim who let me know RX status differences between Yukon and XaQti XMAC. It seems that there is still occasional watchdog timeout error but I couldn't reproduce it and need more information to analyze it from users. Tested by: bz(amd64), me(i386, sparc64), current ML Frank Behrens frank ! pinky ( sax $ de
191 lines
7.6 KiB
C
191 lines
7.6 KiB
C
/* $OpenBSD: yukonreg.h,v 1.2 2003/08/12 05:23:06 nate Exp $ */
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/*-
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* Copyright (c) 2003 Nathan L. Binkert <binkertn@umich.edu>
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*
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* Permission to use, copy, modify, and distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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* $FreeBSD$
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*/
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/* General Purpose Status Register (GPSR) */
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#define YUKON_GPSR 0x0000
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#define YU_GPSR_SPEED 0x8000 /* speed 0 - 10Mbps, 1 - 100Mbps */
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#define YU_GPSR_DUPLEX 0x4000 /* 0 - half duplex, 1 - full duplex */
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#define YU_GPSR_FCTL_TX 0x2000 /* Tx flow control, 1 - disabled */
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#define YU_GPSR_LINK 0x1000 /* link status (down/up) */
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#define YU_GPSR_PAUSE 0x0800 /* flow control enable/disable */
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#define YU_GPSR_TX_IN_PROG 0x0400 /* transmit in progress */
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#define YU_GPSR_EXCESS_COL 0x0200 /* excessive collisions occurred */
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#define YU_GPSR_LATE_COL 0x0100 /* late collision occurred */
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#define YU_GPSR_MII_PHY_STC 0x0020 /* MII PHY status change */
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#define YU_GPSR_GIG_SPEED 0x0010 /* Gigabit Speed (0 - use speed bit) */
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#define YU_GPSR_PARTITION 0x0008 /* partition mode */
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#define YU_GPSR_FCTL_RX 0x0004 /* Rx flow control, 1 - disabled */
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#define YU_GPSR_PROMS_EN 0x0002 /* promiscuous mode, 1 - enabled */
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/* General Purpose Control Register (GPCR) */
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#define YUKON_GPCR 0x0004
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#define YU_GPCR_FCTL_TX_DIS 0x2000 /* Disable Tx flow control 802.3x */
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#define YU_GPCR_TXEN 0x1000 /* Transmit Enable */
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#define YU_GPCR_RXEN 0x0800 /* Receive Enable */
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#define YU_GPCR_BURSTEN 0x0400 /* Burst Mode Enable */
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#define YU_GPCR_LPBK 0x0200 /* MAC Loopback Enable */
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#define YU_GPCR_PAR 0x0100 /* Partition Enable */
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#define YU_GPCR_GIG 0x0080 /* Gigabit Speed 1000Mbps */
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#define YU_GPCR_FLP 0x0040 /* Force Link Pass */
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#define YU_GPCR_DUPLEX 0x0020 /* Duplex Enable */
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#define YU_GPCR_FCTL_RX_DIS 0x0010 /* Disable Rx flow control 802.3x */
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#define YU_GPCR_SPEED 0x0008 /* Port Speed 100Mbps */
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#define YU_GPCR_DPLX_DIS 0x0004 /* Disable Auto-Update for duplex */
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#define YU_GPCR_FCTL_DIS 0x0002 /* Disable Auto-Update for 802.3x */
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#define YU_GPCR_SPEED_DIS 0x0001 /* Disable Auto-Update for speed */
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/* Transmit Control Register (TCR) */
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#define YUKON_TCR 0x0008
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#define YU_TCR_FJ 0x8000 /* force jam / flow control */
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#define YU_TCR_CRCD 0x4000 /* insert CRC (0 - enable) */
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#define YU_TCR_PADD 0x2000 /* pad packets to 64b (0 - enable) */
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#define YU_TCR_COLTH 0x1c00 /* collision threshold */
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/* Receive Control Register (RCR) */
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#define YUKON_RCR 0x000c
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#define YU_RCR_UFLEN 0x8000 /* unicast filter enable */
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#define YU_RCR_MUFLEN 0x4000 /* multicast filter enable */
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#define YU_RCR_CRCR 0x2000 /* remove CRC */
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#define YU_RCR_PASSFC 0x1000 /* pass flow control packets */
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/* Transmit Flow Control Register (TFCR) */
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#define YUKON_TFCR 0x0010 /* Pause Time */
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/* Transmit Parameter Register (TPR) */
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#define YUKON_TPR 0x0014
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#define YU_TPR_JAM_LEN(x) (((x) & 0x3) << 14)
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#define YU_TPR_JAM_IPG(x) (((x) & 0x1f) << 9)
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#define YU_TPR_JAM2DATA_IPG(x) (((x) & 0x1f) << 4)
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/* Serial Mode Register (SMR) */
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#define YUKON_SMR 0x0018
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#define YU_SMR_DATA_BLIND(x) (((x) & 0x1f) << 11)
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#define YU_SMR_LIMIT4 0x0400 /* reset after 16 / 4 collisions */
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#define YU_SMR_MFL_JUMBO 0x0100 /* max frame length for jumbo frames */
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#define YU_SMR_MFL_VLAN 0x0200 /* max frame length + vlan tag */
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#define YU_SMR_IPG_DATA(x) ((x) & 0x1f)
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/* Source Address Low #1 (SAL1) */
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#define YUKON_SAL1 0x001c /* SA1[15:0] */
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/* Source Address Middle #1 (SAM1) */
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#define YUKON_SAM1 0x0020 /* SA1[31:16] */
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/* Source Address High #1 (SAH1) */
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#define YUKON_SAH1 0x0024 /* SA1[47:32] */
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/* Source Address Low #2 (SAL2) */
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#define YUKON_SAL2 0x0028 /* SA2[15:0] */
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/* Source Address Middle #2 (SAM2) */
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#define YUKON_SAM2 0x002c /* SA2[31:16] */
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/* Source Address High #2 (SAH2) */
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#define YUKON_SAH2 0x0030 /* SA2[47:32] */
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/* Multicatst Address Hash Register 1 (MCAH1) */
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#define YUKON_MCAH1 0x0034
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/* Multicatst Address Hash Register 2 (MCAH2) */
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#define YUKON_MCAH2 0x0038
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/* Multicatst Address Hash Register 3 (MCAH3) */
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#define YUKON_MCAH3 0x003c
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/* Multicatst Address Hash Register 4 (MCAH4) */
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#define YUKON_MCAH4 0x0040
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/* Transmit Interrupt Register (TIR) */
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#define YUKON_TIR 0x0044
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#define YU_TIR_OUT_UNICAST 0x0001 /* Num Unicast Packets Transmitted */
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#define YU_TIR_OUT_BROADCAST 0x0002 /* Num Broadcast Packets Transmitted */
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#define YU_TIR_OUT_PAUSE 0x0004 /* Num Pause Packets Transmitted */
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#define YU_TIR_OUT_MULTICAST 0x0008 /* Num Multicast Packets Transmitted */
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#define YU_TIR_OUT_OCTETS 0x0030 /* Num Bytes Transmitted */
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#define YU_TIR_OUT_64_OCTETS 0x0000 /* Num Packets Transmitted */
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#define YU_TIR_OUT_127_OCTETS 0x0000 /* Num Packets Transmitted */
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#define YU_TIR_OUT_255_OCTETS 0x0000 /* Num Packets Transmitted */
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#define YU_TIR_OUT_511_OCTETS 0x0000 /* Num Packets Transmitted */
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#define YU_TIR_OUT_1023_OCTETS 0x0000 /* Num Packets Transmitted */
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#define YU_TIR_OUT_1518_OCTETS 0x0000 /* Num Packets Transmitted */
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#define YU_TIR_OUT_MAX_OCTETS 0x0000 /* Num Packets Transmitted */
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#define YU_TIR_OUT_SPARE 0x0000 /* Num Packets Transmitted */
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#define YU_TIR_OUT_COLLISIONS 0x0000 /* Num Packets Transmitted */
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#define YU_TIR_OUT_LATE 0x0000 /* Num Packets Transmitted */
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/* Receive Interrupt Register (RIR) */
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#define YUKON_RIR 0x0048
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/* Transmit and Receive Interrupt Register (TRIR) */
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#define YUKON_TRIR 0x004c
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/* Transmit Interrupt Mask Register (TIMR) */
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#define YUKON_TIMR 0x0050
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/* Receive Interrupt Mask Register (RIMR) */
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#define YUKON_RIMR 0x0054
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/* Transmit and Receive Interrupt Mask Register (TRIMR) */
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#define YUKON_TRIMR 0x0058
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/* SMI Control Register (SMICR) */
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#define YUKON_SMICR 0x0080
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#define YU_SMICR_PHYAD(x) (((x) & 0x1f) << 11)
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#define YU_SMICR_REGAD(x) (((x) & 0x1f) << 6)
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#define YU_SMICR_OPCODE 0x0020 /* opcode (0 - write, 1 - read) */
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#define YU_SMICR_OP_READ 0x0020 /* opcode read */
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#define YU_SMICR_OP_WRITE 0x0000 /* opcode write */
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#define YU_SMICR_READ_VALID 0x0010 /* read valid */
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#define YU_SMICR_BUSY 0x0008 /* busy (writing) */
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/* SMI Data Register (SMIDR) */
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#define YUKON_SMIDR 0x0084
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/* PHY Addres Register (PAR) */
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#define YUKON_PAR 0x0088
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#define YU_PAR_MIB_CLR 0x0020 /* MIB Counters Clear Mode */
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#define YU_PAR_LOAD_TSTCNT 0x0010 /* Load count 0xfffffff0 into cntr */
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/* Receive status */
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#define YU_RXSTAT_FOFL 0x00000001 /* Rx FIFO overflow */
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#define YU_RXSTAT_CRCERR 0x00000002 /* CRC error */
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#define YU_RXSTAT_FRAGMENT 0x00000008 /* fragment */
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#define YU_RXSTAT_LONGERR 0x00000010 /* too long packet */
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#define YU_RXSTAT_MIIERR 0x00000020 /* MII error */
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#define YU_RXSTAT_BADFC 0x00000040 /* bad flow-control packet */
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#define YU_RXSTAT_GOODFC 0x00000080 /* good flow-control packet */
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#define YU_RXSTAT_RXOK 0x00000100 /* receice OK (Good packet) */
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#define YU_RXSTAT_BROADCAST 0x00000200 /* broadcast packet */
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#define YU_RXSTAT_MULTICAST 0x00000400 /* multicast packet */
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#define YU_RXSTAT_RUNT 0x00000800 /* undersize packet */
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#define YU_RXSTAT_JABBER 0x00001000 /* jabber packet */
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#define YU_RXSTAT_VLAN 0x00002000 /* VLAN packet */
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#define YU_RXSTAT_LENSHIFT 16
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#define YU_RXSTAT_BYTES(x) ((x) >> YU_RXSTAT_LENSHIFT)
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