395 lines
13 KiB
C++
395 lines
13 KiB
C++
//===- CodeEmitterGen.cpp - Code Emitter Generator ------------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// CodeEmitterGen uses the descriptions of instructions and their fields to
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// construct an automated code emitter: a function that, given a MachineInstr,
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// returns the (currently, 32-bit unsigned) value of the instruction.
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//
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//===----------------------------------------------------------------------===//
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#include "CodeGenInstruction.h"
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#include "CodeGenTarget.h"
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#include "SubtargetFeatureInfo.h"
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#include "llvm/ADT/ArrayRef.h"
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#include "llvm/ADT/StringExtras.h"
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#include "llvm/Support/Casting.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/TableGen/Record.h"
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#include "llvm/TableGen/TableGenBackend.h"
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#include <cassert>
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#include <cstdint>
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#include <map>
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#include <set>
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#include <string>
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#include <utility>
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#include <vector>
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using namespace llvm;
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namespace {
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class CodeEmitterGen {
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RecordKeeper &Records;
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public:
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CodeEmitterGen(RecordKeeper &R) : Records(R) {}
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void run(raw_ostream &o);
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private:
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int getVariableBit(const std::string &VarName, BitsInit *BI, int bit);
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std::string getInstructionCase(Record *R, CodeGenTarget &Target);
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void AddCodeToMergeInOperand(Record *R, BitsInit *BI,
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const std::string &VarName,
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unsigned &NumberedOp,
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std::set<unsigned> &NamedOpIndices,
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std::string &Case, CodeGenTarget &Target);
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};
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// If the VarBitInit at position 'bit' matches the specified variable then
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// return the variable bit position. Otherwise return -1.
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int CodeEmitterGen::getVariableBit(const std::string &VarName,
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BitsInit *BI, int bit) {
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if (VarBitInit *VBI = dyn_cast<VarBitInit>(BI->getBit(bit))) {
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if (VarInit *VI = dyn_cast<VarInit>(VBI->getBitVar()))
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if (VI->getName() == VarName)
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return VBI->getBitNum();
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} else if (VarInit *VI = dyn_cast<VarInit>(BI->getBit(bit))) {
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if (VI->getName() == VarName)
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return 0;
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}
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return -1;
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}
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void CodeEmitterGen::
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AddCodeToMergeInOperand(Record *R, BitsInit *BI, const std::string &VarName,
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unsigned &NumberedOp,
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std::set<unsigned> &NamedOpIndices,
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std::string &Case, CodeGenTarget &Target) {
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CodeGenInstruction &CGI = Target.getInstruction(R);
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// Determine if VarName actually contributes to the Inst encoding.
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int bit = BI->getNumBits()-1;
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// Scan for a bit that this contributed to.
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for (; bit >= 0; ) {
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if (getVariableBit(VarName, BI, bit) != -1)
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break;
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--bit;
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}
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// If we found no bits, ignore this value, otherwise emit the call to get the
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// operand encoding.
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if (bit < 0) return;
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// If the operand matches by name, reference according to that
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// operand number. Non-matching operands are assumed to be in
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// order.
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unsigned OpIdx;
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if (CGI.Operands.hasOperandNamed(VarName, OpIdx)) {
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// Get the machine operand number for the indicated operand.
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OpIdx = CGI.Operands[OpIdx].MIOperandNo;
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assert(!CGI.Operands.isFlatOperandNotEmitted(OpIdx) &&
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"Explicitly used operand also marked as not emitted!");
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} else {
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unsigned NumberOps = CGI.Operands.size();
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/// If this operand is not supposed to be emitted by the
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/// generated emitter, skip it.
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while (NumberedOp < NumberOps &&
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(CGI.Operands.isFlatOperandNotEmitted(NumberedOp) ||
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(!NamedOpIndices.empty() && NamedOpIndices.count(
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CGI.Operands.getSubOperandNumber(NumberedOp).first)))) {
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++NumberedOp;
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if (NumberedOp >= CGI.Operands.back().MIOperandNo +
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CGI.Operands.back().MINumOperands) {
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errs() << "Too few operands in record " << R->getName() <<
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" (no match for variable " << VarName << "):\n";
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errs() << *R;
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errs() << '\n';
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return;
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}
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}
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OpIdx = NumberedOp++;
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}
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std::pair<unsigned, unsigned> SO = CGI.Operands.getSubOperandNumber(OpIdx);
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std::string &EncoderMethodName = CGI.Operands[SO.first].EncoderMethodName;
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// If the source operand has a custom encoder, use it. This will
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// get the encoding for all of the suboperands.
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if (!EncoderMethodName.empty()) {
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// A custom encoder has all of the information for the
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// sub-operands, if there are more than one, so only
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// query the encoder once per source operand.
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if (SO.second == 0) {
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Case += " // op: " + VarName + "\n" +
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" op = " + EncoderMethodName + "(MI, " + utostr(OpIdx);
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Case += ", Fixups, STI";
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Case += ");\n";
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}
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} else {
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Case += " // op: " + VarName + "\n" +
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" op = getMachineOpValue(MI, MI.getOperand(" + utostr(OpIdx) + ")";
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Case += ", Fixups, STI";
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Case += ");\n";
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}
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for (; bit >= 0; ) {
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int varBit = getVariableBit(VarName, BI, bit);
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// If this bit isn't from a variable, skip it.
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if (varBit == -1) {
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--bit;
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continue;
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}
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// Figure out the consecutive range of bits covered by this operand, in
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// order to generate better encoding code.
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int beginInstBit = bit;
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int beginVarBit = varBit;
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int N = 1;
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for (--bit; bit >= 0;) {
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varBit = getVariableBit(VarName, BI, bit);
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if (varBit == -1 || varBit != (beginVarBit - N)) break;
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++N;
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--bit;
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}
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uint64_t opMask = ~(uint64_t)0 >> (64-N);
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int opShift = beginVarBit - N + 1;
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opMask <<= opShift;
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opShift = beginInstBit - beginVarBit;
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if (opShift > 0) {
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Case += " Value |= (op & UINT64_C(" + utostr(opMask) + ")) << " +
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itostr(opShift) + ";\n";
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} else if (opShift < 0) {
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Case += " Value |= (op & UINT64_C(" + utostr(opMask) + ")) >> " +
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itostr(-opShift) + ";\n";
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} else {
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Case += " Value |= op & UINT64_C(" + utostr(opMask) + ");\n";
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}
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}
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}
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std::string CodeEmitterGen::getInstructionCase(Record *R,
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CodeGenTarget &Target) {
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std::string Case;
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BitsInit *BI = R->getValueAsBitsInit("Inst");
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unsigned NumberedOp = 0;
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std::set<unsigned> NamedOpIndices;
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// Collect the set of operand indices that might correspond to named
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// operand, and skip these when assigning operands based on position.
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if (Target.getInstructionSet()->
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getValueAsBit("noNamedPositionallyEncodedOperands")) {
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CodeGenInstruction &CGI = Target.getInstruction(R);
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for (const RecordVal &RV : R->getValues()) {
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unsigned OpIdx;
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if (!CGI.Operands.hasOperandNamed(RV.getName(), OpIdx))
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continue;
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NamedOpIndices.insert(OpIdx);
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}
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}
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// Loop over all of the fields in the instruction, determining which are the
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// operands to the instruction.
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for (const RecordVal &RV : R->getValues()) {
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// Ignore fixed fields in the record, we're looking for values like:
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// bits<5> RST = { ?, ?, ?, ?, ? };
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if (RV.getPrefix() || RV.getValue()->isComplete())
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continue;
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AddCodeToMergeInOperand(R, BI, RV.getName(), NumberedOp,
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NamedOpIndices, Case, Target);
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}
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StringRef PostEmitter = R->getValueAsString("PostEncoderMethod");
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if (!PostEmitter.empty()) {
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Case += " Value = ";
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Case += PostEmitter;
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Case += "(MI, Value";
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Case += ", STI";
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Case += ");\n";
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}
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return Case;
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}
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void CodeEmitterGen::run(raw_ostream &o) {
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CodeGenTarget Target(Records);
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std::vector<Record*> Insts = Records.getAllDerivedDefinitions("Instruction");
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// For little-endian instruction bit encodings, reverse the bit order
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Target.reverseBitsForLittleEndianEncoding();
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ArrayRef<const CodeGenInstruction*> NumberedInstructions =
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Target.getInstructionsByEnumValue();
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// Emit function declaration
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o << "uint64_t " << Target.getName();
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o << "MCCodeEmitter::getBinaryCodeForInstr(const MCInst &MI,\n"
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<< " SmallVectorImpl<MCFixup> &Fixups,\n"
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<< " const MCSubtargetInfo &STI) const {\n";
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// Emit instruction base values
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o << " static const uint64_t InstBits[] = {\n";
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for (const CodeGenInstruction *CGI : NumberedInstructions) {
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Record *R = CGI->TheDef;
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if (R->getValueAsString("Namespace") == "TargetOpcode" ||
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R->getValueAsBit("isPseudo")) {
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o << " UINT64_C(0),\n";
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continue;
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}
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BitsInit *BI = R->getValueAsBitsInit("Inst");
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// Start by filling in fixed values.
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uint64_t Value = 0;
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for (unsigned i = 0, e = BI->getNumBits(); i != e; ++i) {
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if (BitInit *B = dyn_cast<BitInit>(BI->getBit(e-i-1)))
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Value |= (uint64_t)B->getValue() << (e-i-1);
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}
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o << " UINT64_C(" << Value << ")," << '\t' << "// " << R->getName() << "\n";
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}
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o << " UINT64_C(0)\n };\n";
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// Map to accumulate all the cases.
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std::map<std::string, std::vector<std::string>> CaseMap;
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// Construct all cases statement for each opcode
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for (std::vector<Record*>::iterator IC = Insts.begin(), EC = Insts.end();
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IC != EC; ++IC) {
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Record *R = *IC;
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if (R->getValueAsString("Namespace") == "TargetOpcode" ||
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R->getValueAsBit("isPseudo"))
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continue;
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std::string InstName =
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(R->getValueAsString("Namespace") + "::" + R->getName()).str();
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std::string Case = getInstructionCase(R, Target);
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CaseMap[Case].push_back(std::move(InstName));
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}
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// Emit initial function code
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o << " const unsigned opcode = MI.getOpcode();\n"
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<< " uint64_t Value = InstBits[opcode];\n"
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<< " uint64_t op = 0;\n"
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<< " (void)op; // suppress warning\n"
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<< " switch (opcode) {\n";
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// Emit each case statement
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std::map<std::string, std::vector<std::string>>::iterator IE, EE;
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for (IE = CaseMap.begin(), EE = CaseMap.end(); IE != EE; ++IE) {
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const std::string &Case = IE->first;
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std::vector<std::string> &InstList = IE->second;
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for (int i = 0, N = InstList.size(); i < N; i++) {
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if (i) o << "\n";
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o << " case " << InstList[i] << ":";
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}
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o << " {\n";
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o << Case;
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o << " break;\n"
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<< " }\n";
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}
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// Default case: unhandled opcode
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o << " default:\n"
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<< " std::string msg;\n"
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<< " raw_string_ostream Msg(msg);\n"
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<< " Msg << \"Not supported instr: \" << MI;\n"
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<< " report_fatal_error(Msg.str());\n"
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<< " }\n"
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<< " return Value;\n"
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<< "}\n\n";
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const auto &All = SubtargetFeatureInfo::getAll(Records);
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std::map<Record *, SubtargetFeatureInfo, LessRecordByID> SubtargetFeatures;
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SubtargetFeatures.insert(All.begin(), All.end());
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o << "#ifdef ENABLE_INSTR_PREDICATE_VERIFIER\n"
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<< "#undef ENABLE_INSTR_PREDICATE_VERIFIER\n"
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<< "#include <sstream>\n\n";
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// Emit the subtarget feature enumeration.
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SubtargetFeatureInfo::emitSubtargetFeatureFlagEnumeration(SubtargetFeatures,
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o);
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// Emit the name table for error messages.
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o << "#ifndef NDEBUG\n";
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SubtargetFeatureInfo::emitNameTable(SubtargetFeatures, o);
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o << "#endif // NDEBUG\n";
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// Emit the available features compute function.
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SubtargetFeatureInfo::emitComputeAssemblerAvailableFeatures(
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Target.getName(), "MCCodeEmitter", "computeAvailableFeatures",
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SubtargetFeatures, o);
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// Emit the predicate verifier.
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o << "void " << Target.getName()
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<< "MCCodeEmitter::verifyInstructionPredicates(\n"
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<< " const MCInst &Inst, uint64_t AvailableFeatures) const {\n"
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<< "#ifndef NDEBUG\n"
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<< " static uint64_t RequiredFeatures[] = {\n";
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unsigned InstIdx = 0;
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for (const CodeGenInstruction *Inst : Target.getInstructionsByEnumValue()) {
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o << " ";
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for (Record *Predicate : Inst->TheDef->getValueAsListOfDefs("Predicates")) {
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const auto &I = SubtargetFeatures.find(Predicate);
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if (I != SubtargetFeatures.end())
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o << I->second.getEnumName() << " | ";
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}
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o << "0, // " << Inst->TheDef->getName() << " = " << InstIdx << "\n";
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InstIdx++;
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}
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o << " };\n\n";
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o << " assert(Inst.getOpcode() < " << InstIdx << ");\n";
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o << " uint64_t MissingFeatures =\n"
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<< " (AvailableFeatures & RequiredFeatures[Inst.getOpcode()]) ^\n"
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<< " RequiredFeatures[Inst.getOpcode()];\n"
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<< " if (MissingFeatures) {\n"
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<< " std::ostringstream Msg;\n"
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<< " Msg << \"Attempting to emit \" << "
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"MCII.getName(Inst.getOpcode()).str()\n"
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<< " << \" instruction but the \";\n"
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<< " for (unsigned i = 0; i < 8 * sizeof(MissingFeatures); ++i)\n"
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<< " if (MissingFeatures & (1ULL << i))\n"
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<< " Msg << SubtargetFeatureNames[i] << \" \";\n"
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<< " Msg << \"predicate(s) are not met\";\n"
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<< " report_fatal_error(Msg.str());\n"
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<< " }\n"
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<< "#else\n"
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<< "// Silence unused variable warning on targets that don't use MCII for "
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"other purposes (e.g. BPF).\n"
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<< "(void)MCII;\n"
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<< "#endif // NDEBUG\n";
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o << "}\n";
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o << "#endif\n";
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}
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} // end anonymous namespace
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namespace llvm {
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void EmitCodeEmitter(RecordKeeper &RK, raw_ostream &OS) {
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emitSourceFileHeader("Machine Code Emitter", OS);
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CodeEmitterGen(RK).run(OS);
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}
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} // end namespace llvm
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