c232a6c2f7
[X86] Add FPSW as a Def on some FP instructions that were missing it. Pull in r352608 from upstream llvm trunk (by Craig Topper): [X86] Remove a couple places where we unnecessarily pass 0 to the EmitPriority of some FP instruction aliases. NFC As far as I can tell we already won't emit these aliases due to an operand count check in the tablegen code. Removing these because I couldn't make sense of the inconsistency between fadd and fmul from reading the code. I checked the AsmMatcher and AsmWriter files before and after this change and there were no differences. Pull in r353015 from upstream llvm trunk (by Craig Topper): [X86] Print %st(0) as %st when its implicit to the instruction. Continue printing it as %st(0) when its encoded in the instruction. This is a step back from the change I made in r352985. This appears to be more consistent with gcc and objdump behavior. Pull in r353061 from upstream llvm trunk (by Craig Topper): [X86] Print all register forms of x87 fadd/fsub/fdiv/fmul as having two arguments where on is %st. All of these instructions consume one encoded register and the other register is %st. They either write the result to %st or the encoded register. Previously we printed both arguments when the encoded register was written. And we printed one argument when the result was written to %st. For the stack popping forms the encoded register is always the destination and we didn't print both operands. This was inconsistent with gcc and objdump and just makes the output assembly code harder to read. This patch changes things to always print both operands making us consistent with gcc and objdump. The parser should still be able to handle the single register forms just as it did before. This also matches the GNU assembler behavior. Pull in r353141 from upstream llvm trunk (by Craig Topper): [X86] Connect the default fpsr and dirflag clobbers in inline assembly to the registers we have defined for them. Summary: We don't currently map these constraints to physical register numbers so they don't make it to the MachineIR representation of inline assembly. This could have problems for proper dependency tracking in the machine schedulers though I don't have a test case that shows that. Reviewers: rnk Reviewed By: rnk Subscribers: eraman, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D57641 Pull in r353489 from upstream llvm trunk (by Craig Topper): [X86] Add FPCW as a register and start using it as an implicit use on floating point instructions. Summary: FPCW contains the rounding mode control which we manipulate to implement fp to integer conversion by changing the roudning mode, storing the value to the stack, and then changing the rounding mode back. Because we didn't model FPCW and its dependency chain, other instructions could be scheduled into the middle of the sequence. This patch introduces the register and adds it as an implciit def of FLDCW and implicit use of the FP binary arithmetic instructions and store instructions. There are more instructions that need to be updated, but this is a good start. I believe this fixes at least the reduced test case from PR40529. Reviewers: RKSimon, spatel, rnk, efriedma, andrew.w.kaylor Subscribers: dim, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D57735 These should fix a problem in clang 7.0 where it would sometimes emit long double floating point instructions in a slightly wrong order, leading to failures in our libm tests. In particular, the cbrt_test test case 'cbrtl_powl' and the trig_test test case 'reduction'. Reported by: lwhsu PR: 234040 Upstream PR: https://bugs.llvm.org/show_bug.cgi?id=40206 |
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.. | ||
AsmMatcherEmitter.cpp | ||
AsmWriterEmitter.cpp | ||
AsmWriterInst.cpp | ||
AsmWriterInst.h | ||
Attributes.cpp | ||
CallingConvEmitter.cpp | ||
CodeEmitterGen.cpp | ||
CodeGenDAGPatterns.cpp | ||
CodeGenDAGPatterns.h | ||
CodeGenHwModes.cpp | ||
CodeGenHwModes.h | ||
CodeGenInstruction.cpp | ||
CodeGenInstruction.h | ||
CodeGenIntrinsics.h | ||
CodeGenMapTable.cpp | ||
CodeGenRegisters.cpp | ||
CodeGenRegisters.h | ||
CodeGenSchedule.cpp | ||
CodeGenSchedule.h | ||
CodeGenTarget.cpp | ||
CodeGenTarget.h | ||
CTagsEmitter.cpp | ||
DAGISelEmitter.cpp | ||
DAGISelMatcher.cpp | ||
DAGISelMatcher.h | ||
DAGISelMatcherEmitter.cpp | ||
DAGISelMatcherGen.cpp | ||
DAGISelMatcherOpt.cpp | ||
DFAPacketizerEmitter.cpp | ||
DisassemblerEmitter.cpp | ||
ExegesisEmitter.cpp | ||
FastISelEmitter.cpp | ||
FixedLenDecoderEmitter.cpp | ||
GlobalISelEmitter.cpp | ||
InfoByHwMode.cpp | ||
InfoByHwMode.h | ||
InstrDocsEmitter.cpp | ||
InstrInfoEmitter.cpp | ||
IntrinsicEmitter.cpp | ||
OptParserEmitter.cpp | ||
PredicateExpander.cpp | ||
PredicateExpander.h | ||
PseudoLoweringEmitter.cpp | ||
RegisterBankEmitter.cpp | ||
RegisterInfoEmitter.cpp | ||
RISCVCompressInstEmitter.cpp | ||
SDNodeProperties.cpp | ||
SDNodeProperties.h | ||
SearchableTableEmitter.cpp | ||
SequenceToOffsetTable.h | ||
SubtargetEmitter.cpp | ||
SubtargetFeatureInfo.cpp | ||
SubtargetFeatureInfo.h | ||
TableGen.cpp | ||
TableGenBackends.h | ||
Types.cpp | ||
Types.h | ||
WebAssemblyDisassemblerEmitter.cpp | ||
WebAssemblyDisassemblerEmitter.h | ||
X86DisassemblerShared.h | ||
X86DisassemblerTables.cpp | ||
X86DisassemblerTables.h | ||
X86EVEX2VEXTablesEmitter.cpp | ||
X86FoldTablesEmitter.cpp | ||
X86ModRMFilters.cpp | ||
X86ModRMFilters.h | ||
X86RecognizableInstr.cpp | ||
X86RecognizableInstr.h |